Commit 23fbee9d authored by Ralf Baechle's avatar Ralf Baechle

Support for Toshiba's RBHMA4500 eval board for the TX4938.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 13294040
...@@ -695,6 +695,24 @@ config SOC_AU1500 ...@@ -695,6 +695,24 @@ config SOC_AU1500
config SOC_AU1550 config SOC_AU1550
bool "SOC_AU1550" bool "SOC_AU1550"
config TOSHIBA_RBTX4938
bool "Support for Toshiba RBTX4938 board"
select HAVE_STD_PC_SERIAL_PORT
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select HAS_TXX9_SERIAL
select HW_HAS_PCI
select I8259
select ISA
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
select TOSHIBA_BOARDS
help
This Toshiba board is based on the TX4938 processor. Say Y here to
support this machine type
endchoice endchoice
choice choice
...@@ -837,6 +855,7 @@ config TOSHIBA_FPCIB0 ...@@ -837,6 +855,7 @@ config TOSHIBA_FPCIB0
source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig" source "arch/mips/sibyte/Kconfig"
source "arch/mips/tx4938/Kconfig"
source "arch/mips/philips/pnx8550/common/Kconfig" source "arch/mips/philips/pnx8550/common/Kconfig"
config RWSEM_GENERIC_SPINLOCK config RWSEM_GENERIC_SPINLOCK
......
...@@ -690,6 +690,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ ...@@ -690,6 +690,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/
core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/
load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000
#
# Toshiba RBTX4938 board
#
core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/
core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/
load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000
cflags-y += -Iinclude/asm-mips/mach-generic cflags-y += -Iinclude/asm-mips/mach-generic
drivers-$(CONFIG_PCI) += arch/mips/pci/ drivers-$(CONFIG_PCI) += arch/mips/pci/
......
...@@ -52,5 +52,6 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o ...@@ -52,5 +52,6 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o
obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
/*
* Toshiba rbtx4938 pci routines
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/tx4938/rbtx4938.h>
extern struct pci_controller tx4938_pci_controller[];
int pci_get_irq(struct pci_dev *dev, int pin)
{
int irq = pin;
u8 slot = PCI_SLOT(dev->devfn);
struct pci_controller *controller = (struct pci_controller *)dev->sysdata;
if (controller == &tx4938_pci_controller[1]) {
/* TX4938 PCIC1 */
switch (slot) {
case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL)
return RBTX4938_IRQ_IRC + TX4938_IR_ETH0;
break;
case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL)
return RBTX4938_IRQ_IRC + TX4938_IR_ETH1;
break;
}
return 0;
}
/* IRQ rotation */
irq--; /* 0-3 */
if (dev->bus->parent == NULL &&
(slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) {
/* PCI CardSlot (IDSEL=A23) */
/* PCIA => PCIA (IDSEL=A23) */
irq = (irq + 0 + slot) % 4;
} else {
/* PCI Backplane */
irq = (irq + 33 - slot) % 4;
}
irq++; /* 1-4 */
switch (irq) {
case 1:
irq = RBTX4938_IRQ_IOC_PCIA;
break;
case 2:
irq = RBTX4938_IRQ_IOC_PCIB;
break;
case 3:
irq = RBTX4938_IRQ_IOC_PCIC;
break;
case 4:
irq = RBTX4938_IRQ_IOC_PCID;
break;
}
return irq;
}
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
unsigned char irq = 0;
irq = pci_get_irq(dev, pin);
printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
PCI_FUNC(dev->devfn), irq);
return irq;
}
/*
* Do platform specific device initialization at pci_enable_device() time
*/
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
/*
* Define the pci_ops for the Toshiba rbtx4938
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#include <asm/tx4938/rbtx4938.h>
/* initialize in setup */
struct resource pci_io_resource = {
.name = "pci IO space",
.start = 0,
.end = 0,
.flags = IORESOURCE_IO
};
/* initialize in setup */
struct resource pci_mem_resource = {
.name = "pci memory space",
.start = 0,
.end = 0,
.flags = IORESOURCE_MEM
};
struct resource tx4938_pcic1_pci_io_resource = {
.name = "PCI1 IO",
.start = 0,
.end = 0,
.flags = IORESOURCE_IO
};
struct resource tx4938_pcic1_pci_mem_resource = {
.name = "PCI1 mem",
.start = 0,
.end = 0,
.flags = IORESOURCE_MEM
};
static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
{
if (bus > 0) {
/* Type 1 configuration */
tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
} else {
if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
return -1;
/* Type 0 configuration */
tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
((dev_fn & 0xff) << 0x08) | (where & 0xfc);
}
/* clear M_ABORT and Disable M_ABORT Int. */
tx4938_pcicptr->pcistatus =
(tx4938_pcicptr->pcistatus & 0x0000ffff) |
(PCI_STATUS_REC_MASTER_ABORT << 16);
tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
return 0;
}
static int check_abort(int flags)
{
int code = PCIBIOS_SUCCESSFUL;
/* wait write cycle completion before checking error status */
while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
;
if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
tx4938_pcicptr->pcistatus =
(tx4938_pcicptr->
pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
<< 16);
tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
code = PCIBIOS_DEVICE_NOT_FOUND;
}
return code;
}
static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
int flags, retval, dev, busno, func;
dev = PCI_SLOT(devfn);
func = PCI_FUNC(devfn);
/* check if the bus is top-level */
if (bus->parent != NULL)
busno = bus->number;
else {
busno = 0;
}
if (mkaddr(busno, devfn, where, &flags))
return -1;
switch (size) {
case 1:
*val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
#ifdef __BIG_ENDIAN
((where & 3) ^ 3));
#else
(where & 3));
#endif
break;
case 2:
*val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
#ifdef __BIG_ENDIAN
((where & 3) ^ 2));
#else
(where & 3));
#endif
break;
case 4:
*val = tx4938_pcicptr->g2pcfgdata;
break;
}
retval = check_abort(flags);
if (retval == PCIBIOS_DEVICE_NOT_FOUND)
*val = 0xffffffff;
return retval;
}
static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
int flags, dev, busno, func;
busno = bus->number;
dev = PCI_SLOT(devfn);
func = PCI_FUNC(devfn);
/* check if the bus is top-level */
if (bus->parent != NULL) {
busno = bus->number;
} else {
busno = 0;
}
if (mkaddr(busno, devfn, where, &flags))
return -1;
switch (size) {
case 1:
*(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
#ifdef __BIG_ENDIAN
((where & 3) ^ 3)) = val;
#else
(where & 3)) = val;
#endif
break;
case 2:
*(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
#ifdef __BIG_ENDIAN
((where & 0x3) ^ 0x2)) = val;
#else
(where & 3)) = val;
#endif
break;
case 4:
tx4938_pcicptr->g2pcfgdata = val;
break;
}
return check_abort(flags);
}
struct pci_ops tx4938_pci_ops = {
tx4938_pcibios_read_config,
tx4938_pcibios_write_config
};
struct pci_controller tx4938_pci_controller[] = {
/* h/w only supports devices 0x00 to 0x14 */
{
.pci_ops = &tx4938_pci_ops,
.io_resource = &pci_io_resource,
.mem_resource = &pci_mem_resource,
},
/* h/w only supports devices 0x00 to 0x14 */
{
.pci_ops = &tx4938_pci_ops,
.io_resource = &tx4938_pcic1_pci_io_resource,
.mem_resource = &tx4938_pcic1_pci_mem_resource,
}
};
if TOSHIBA_RBTX4938
comment "Multiplex Pin Select"
choice
prompt "PIO[58:61]"
default TOSHIBA_RBTX4938_MPLEX_PIO58_61
config TOSHIBA_RBTX4938_MPLEX_PIO58_61
bool "PIO"
config TOSHIBA_RBTX4938_MPLEX_NAND
bool "NAND"
config TOSHIBA_RBTX4938_MPLEX_ATA
bool "ATA"
endchoice
config TX4938_NAND_BOOT
depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND
bool "NAND Boot Support (EXPERIMENTAL)"
help
This is only for Toshiba RBTX4938 reference board, which has NAND IPL.
Select this option if you need to use NAND boot.
endif
#
# Makefile for common code for Toshiba TX4927 based systems
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
obj-y += prom.o setup.o irq.o irq_handler.o rtc_rx5c348.o
obj-$(CONFIG_KGDB) += dbgio.o
/*
* linux/arch/mips/tx4938/common/dbgio.c
*
* kgdb interface for gdb
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2005 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
*/
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/tx4938/tx4938_mips.h>
extern u8 txx9_sio_kdbg_rd(void);
extern int txx9_sio_kdbg_wr( u8 ch );
u8 getDebugChar(void)
{
return (txx9_sio_kdbg_rd());
}
int putDebugChar(u8 byte)
{
return (txx9_sio_kdbg_wr(byte));
}
/*
* linux/arch/mps/tx4938/common/irq.c
*
* Common tx4938 irq handler
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/irq.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/tx4938/rbtx4938.h>
/**********************************************************************************/
/* Forwad definitions for all pic's */
/**********************************************************************************/
static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
static void tx4938_irq_cp0_shutdown(unsigned int irq);
static void tx4938_irq_cp0_enable(unsigned int irq);
static void tx4938_irq_cp0_disable(unsigned int irq);
static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
static void tx4938_irq_cp0_end(unsigned int irq);
static unsigned int tx4938_irq_pic_startup(unsigned int irq);
static void tx4938_irq_pic_shutdown(unsigned int irq);
static void tx4938_irq_pic_enable(unsigned int irq);
static void tx4938_irq_pic_disable(unsigned int irq);
static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
static void tx4938_irq_pic_end(unsigned int irq);
/**********************************************************************************/
/* Kernel structs for all pic's */
/**********************************************************************************/
DEFINE_SPINLOCK(tx4938_cp0_lock);
DEFINE_SPINLOCK(tx4938_pic_lock);
#define TX4938_CP0_NAME "TX4938-CP0"
static struct hw_interrupt_type tx4938_irq_cp0_type = {
.typename = TX4938_CP0_NAME,
.startup = tx4938_irq_cp0_startup,
.shutdown = tx4938_irq_cp0_shutdown,
.enable = tx4938_irq_cp0_enable,
.disable = tx4938_irq_cp0_disable,
.ack = tx4938_irq_cp0_mask_and_ack,
.end = tx4938_irq_cp0_end,
.set_affinity = NULL
};
#define TX4938_PIC_NAME "TX4938-PIC"
static struct hw_interrupt_type tx4938_irq_pic_type = {
.typename = TX4938_PIC_NAME,
.startup = tx4938_irq_pic_startup,
.shutdown = tx4938_irq_pic_shutdown,
.enable = tx4938_irq_pic_enable,
.disable = tx4938_irq_pic_disable,
.ack = tx4938_irq_pic_mask_and_ack,
.end = tx4938_irq_pic_end,
.set_affinity = NULL
};
static struct irqaction tx4938_irq_pic_action = {
.handler = no_action,
.flags = 0,
.mask = CPU_MASK_NONE,
.name = TX4938_PIC_NAME
};
/**********************************************************************************/
/* Functions for cp0 */
/**********************************************************************************/
#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
static void __init
tx4938_irq_cp0_init(void)
{
int i;
for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &tx4938_irq_cp0_type;
}
return;
}
static unsigned int
tx4938_irq_cp0_startup(unsigned int irq)
{
tx4938_irq_cp0_enable(irq);
return (0);
}
static void
tx4938_irq_cp0_shutdown(unsigned int irq)
{
tx4938_irq_cp0_disable(irq);
}
static void
tx4938_irq_cp0_enable(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&tx4938_cp0_lock, flags);
set_c0_status(tx4938_irq_cp0_mask(irq));
spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
}
static void
tx4938_irq_cp0_disable(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&tx4938_cp0_lock, flags);
clear_c0_status(tx4938_irq_cp0_mask(irq));
spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
return;
}
static void
tx4938_irq_cp0_mask_and_ack(unsigned int irq)
{
tx4938_irq_cp0_disable(irq);
return;
}
static void
tx4938_irq_cp0_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
tx4938_irq_cp0_enable(irq);
}
return;
}
/**********************************************************************************/
/* Functions for pic */
/**********************************************************************************/
u32
tx4938_irq_pic_addr(int irq)
{
/* MVMCP -- need to formulize this */
irq -= TX4938_IRQ_PIC_BEG;
switch (irq) {
case 17:
case 16:
case 1:
case 0:{
return (TX4938_MKA(TX4938_IRC_IRLVL0));
}
case 19:
case 18:
case 3:
case 2:{
return (TX4938_MKA(TX4938_IRC_IRLVL1));
}
case 21:
case 20:
case 5:
case 4:{
return (TX4938_MKA(TX4938_IRC_IRLVL2));
}
case 23:
case 22:
case 7:
case 6:{
return (TX4938_MKA(TX4938_IRC_IRLVL3));
}
case 25:
case 24:
case 9:
case 8:{
return (TX4938_MKA(TX4938_IRC_IRLVL4));
}
case 27:
case 26:
case 11:
case 10:{
return (TX4938_MKA(TX4938_IRC_IRLVL5));
}
case 29:
case 28:
case 13:
case 12:{
return (TX4938_MKA(TX4938_IRC_IRLVL6));
}
case 31:
case 30:
case 15:
case 14:{
return (TX4938_MKA(TX4938_IRC_IRLVL7));
}
}
return (0);
}
u32
tx4938_irq_pic_mask(int irq)
{
/* MVMCP -- need to formulize this */
irq -= TX4938_IRQ_PIC_BEG;
switch (irq) {
case 31:
case 29:
case 27:
case 25:
case 23:
case 21:
case 19:
case 17:{
return (0x07000000);
}
case 30:
case 28:
case 26:
case 24:
case 22:
case 20:
case 18:
case 16:{
return (0x00070000);
}
case 15:
case 13:
case 11:
case 9:
case 7:
case 5:
case 3:
case 1:{
return (0x00000700);
}
case 14:
case 12:
case 10:
case 8:
case 6:
case 4:
case 2:
case 0:{
return (0x00000007);
}
}
return (0x00000000);
}
static void
tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
{
unsigned long val = 0;
val = TX4938_RD(pic_reg);
val &= (~clr_bits);
val |= (set_bits);
TX4938_WR(pic_reg, val);
mmiowb();
TX4938_RD(pic_reg);
return;
}
static void __init
tx4938_irq_pic_init(void)
{
unsigned long flags;
int i;
for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 2;
irq_desc[i].handler = &tx4938_irq_pic_type;
}
setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
spin_lock_irqsave(&tx4938_pic_lock, flags);
TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
spin_unlock_irqrestore(&tx4938_pic_lock, flags);
return;
}
static unsigned int
tx4938_irq_pic_startup(unsigned int irq)
{
tx4938_irq_pic_enable(irq);
return (0);
}
static void
tx4938_irq_pic_shutdown(unsigned int irq)
{
tx4938_irq_pic_disable(irq);
return;
}
static void
tx4938_irq_pic_enable(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&tx4938_pic_lock, flags);
tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
tx4938_irq_pic_mask(irq));
spin_unlock_irqrestore(&tx4938_pic_lock, flags);
return;
}
static void
tx4938_irq_pic_disable(unsigned int irq)
{
unsigned long flags;
spin_lock_irqsave(&tx4938_pic_lock, flags);
tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
tx4938_irq_pic_mask(irq), 0);
spin_unlock_irqrestore(&tx4938_pic_lock, flags);
return;
}
static void
tx4938_irq_pic_mask_and_ack(unsigned int irq)
{
tx4938_irq_pic_disable(irq);
return;
}
static void
tx4938_irq_pic_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
tx4938_irq_pic_enable(irq);
}
return;
}
/**********************************************************************************/
/* Main init functions */
/**********************************************************************************/
void __init
tx4938_irq_init(void)
{
extern asmlinkage void tx4938_irq_handler(void);
tx4938_irq_cp0_init();
tx4938_irq_pic_init();
set_except_vector(0, tx4938_irq_handler);
return;
}
int
tx4938_irq_nested(void)
{
int sw_irq = 0;
u32 level2;
level2 = TX4938_RD(0xff1ff6a0);
if ((level2 & 0x10000) == 0) {
level2 &= 0x1f;
sw_irq = TX4938_IRQ_PIC_BEG + level2;
if (sw_irq == 26) {
{
extern int toshiba_rbtx4938_irq_nested(int sw_irq);
sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
}
}
}
wbflush();
return (sw_irq);
}
/*
* linux/arch/mips/tx4938/common/handler.S
*
* Primary interrupt handler for tx4938 based systems
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/tx4938/rbtx4938.h>
.align 5
NESTED(tx4938_irq_handler, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
mfc0 t0, CP0_CAUSE
mfc0 t1, CP0_STATUS
and t0, t1
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_ip7
/* IP6..IP3 multiplexed -- do not use */
andi t1, t0, STATUSF_IP2 /* tx4938 pic */
bnez t1, ll_ip2
andi t1, t0, STATUSF_IP1 /* user line 1 */
bnez t1, ll_ip1
andi t1, t0, STATUSF_IP0 /* user line 0 */
bnez t1, ll_ip0
.set reorder
nop
END(tx4938_irq_handler)
.align 5
ll_ip7:
li a0, TX4938_IRQ_CPU_TIMER
move a1, sp
jal do_IRQ
j ret_from_irq
ll_ip2:
jal tx4938_irq_nested
nop
beqz v0, goto_spurious_interrupt
nop
move a0, v0
move a1, sp
jal do_IRQ
j ret_from_irq
goto_spurious_interrupt:
j ret_from_irq
ll_ip1:
li a0, TX4938_IRQ_USER1
move a1, sp
jal do_IRQ
j ret_from_irq
ll_ip0:
li a0, TX4938_IRQ_USER0
move a1, sp
jal do_IRQ
j ret_from_irq
/*
* linux/arch/mips/tx4938/common/prom.c
*
* common tx4938 memory interface
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/tx4938/tx4938.h>
static unsigned int __init
tx4938_process_sdccr(u64 * addr)
{
u64 val;
unsigned int sdccr_ce;
unsigned int sdccr_rs;
unsigned int sdccr_cs;
unsigned int sdccr_mw;
unsigned int rs = 0;
unsigned int cs = 0;
unsigned int mw = 0;
unsigned int bc = 4;
unsigned int msize = 0;
val = (*((vu64 *) (addr)));
/* MVMCP -- need #defs for these bits masks */
sdccr_ce = ((val & (1 << 10)) >> 10);
sdccr_rs = ((val & (3 << 5)) >> 5);
sdccr_cs = ((val & (7 << 2)) >> 2);
sdccr_mw = ((val & (1 << 0)) >> 0);
if (sdccr_ce) {
switch (sdccr_rs) {
case 0:{
rs = 2048;
break;
}
case 1:{
rs = 4096;
break;
}
case 2:{
rs = 8192;
break;
}
default:{
rs = 0;
break;
}
}
switch (sdccr_cs) {
case 0:{
cs = 256;
break;
}
case 1:{
cs = 512;
break;
}
case 2:{
cs = 1024;
break;
}
case 3:{
cs = 2048;
break;
}
case 4:{
cs = 4096;
break;
}
default:{
cs = 0;
break;
}
}
switch (sdccr_mw) {
case 0:{
mw = 8;
break;
} /* 8 bytes = 64 bits */
case 1:{
mw = 4;
break;
} /* 4 bytes = 32 bits */
}
}
/* bytes per chip MB per chip bank count */
msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
/* MVMCP -- bc hard coded to 4 from table 9.3.1 */
/* boad supports bc=2 but no way to detect */
return (msize);
}
unsigned int __init
tx4938_get_mem_size(void)
{
unsigned int c0;
unsigned int c1;
unsigned int c2;
unsigned int c3;
unsigned int total;
/* MVMCP -- need #defs for these registers */
c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
total = c0 + c1 + c2 + c3;
return (total);
}
/*
* RTC routines for RICOH Rx5C348 SPI chip.
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/rtc.h>
#include <linux/time.h>
#include <asm/time.h>
#include <asm/tx4938/spi.h>
#define EPOCH 2000
/* registers */
#define Rx5C348_REG_SECOND 0
#define Rx5C348_REG_MINUTE 1
#define Rx5C348_REG_HOUR 2
#define Rx5C348_REG_WEEK 3
#define Rx5C348_REG_DAY 4
#define Rx5C348_REG_MONTH 5
#define Rx5C348_REG_YEAR 6
#define Rx5C348_REG_ADJUST 7
#define Rx5C348_REG_ALARM_W_MIN 8
#define Rx5C348_REG_ALARM_W_HOUR 9
#define Rx5C348_REG_ALARM_W_WEEK 10
#define Rx5C348_REG_ALARM_D_MIN 11
#define Rx5C348_REG_ALARM_D_HOUR 12
#define Rx5C348_REG_CTL1 14
#define Rx5C348_REG_CTL2 15
/* register bits */
#define Rx5C348_BIT_PM 0x20 /* REG_HOUR */
#define Rx5C348_BIT_Y2K 0x80 /* REG_MONTH */
#define Rx5C348_BIT_24H 0x20 /* REG_CTL1 */
#define Rx5C348_BIT_XSTP 0x10 /* REG_CTL2 */
/* commands */
#define Rx5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
#define Rx5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
#define Rx5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
#define Rx5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
static struct spi_dev_desc srtc_dev_desc = {
.baud = 1000000, /* 1.0Mbps @ Vdd 2.0V */
.tcss = 31,
.tcsh = 1,
.tcsr = 62,
/* 31us for Tcss (62us for Tcsr) is required for carry operation) */
.byteorder = 1, /* MSB-First */
.polarity = 0, /* High-Active */
.phase = 1, /* Shift-Then-Sample */
};
static int srtc_chipid;
static int srtc_24h;
static inline int
spi_rtc_io(unsigned char *inbuf, unsigned char *outbuf, unsigned int count)
{
unsigned char *inbufs[1], *outbufs[1];
unsigned int incounts[2], outcounts[2];
inbufs[0] = inbuf;
incounts[0] = count;
incounts[1] = 0;
outbufs[0] = outbuf;
outcounts[0] = count;
outcounts[1] = 0;
return txx9_spi_io(srtc_chipid, &srtc_dev_desc,
inbufs, incounts, outbufs, outcounts, 0);
}
/*
* Conversion between binary and BCD.
*/
#ifndef BCD_TO_BIN
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
#endif
#ifndef BIN_TO_BCD
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
#endif
/* RTC-dependent code for time.c */
static int
rtc_rx5c348_set_time(unsigned long t)
{
unsigned char inbuf[8];
struct rtc_time tm;
u8 year, month, day, hour, minute, second, century;
/* convert */
to_tm(t, &tm);
year = tm.tm_year % 100;
month = tm.tm_mon+1; /* tm_mon starts from 0 to 11 */
day = tm.tm_mday;
hour = tm.tm_hour;
minute = tm.tm_min;
second = tm.tm_sec;
century = tm.tm_year / 100;
inbuf[0] = Rx5C348_CMD_MW(Rx5C348_REG_SECOND);
BIN_TO_BCD(second);
inbuf[1] = second;
BIN_TO_BCD(minute);
inbuf[2] = minute;
if (srtc_24h) {
BIN_TO_BCD(hour);
inbuf[3] = hour;
} else {
/* hour 0 is AM12, noon is PM12 */
inbuf[3] = 0;
if (hour >= 12)
inbuf[3] = Rx5C348_BIT_PM;
hour = (hour + 11) % 12 + 1;
BIN_TO_BCD(hour);
inbuf[3] |= hour;
}
inbuf[4] = 0; /* ignore week */
BIN_TO_BCD(day);
inbuf[5] = day;
BIN_TO_BCD(month);
inbuf[6] = month;
if (century >= 20)
inbuf[6] |= Rx5C348_BIT_Y2K;
BIN_TO_BCD(year);
inbuf[7] = year;
/* write in one transfer to avoid data inconsistency */
return spi_rtc_io(inbuf, NULL, 8);
}
static unsigned long
rtc_rx5c348_get_time(void)
{
unsigned char inbuf[8], outbuf[8];
unsigned int year, month, day, hour, minute, second;
inbuf[0] = Rx5C348_CMD_MR(Rx5C348_REG_SECOND);
memset(inbuf + 1, 0, 7);
/* read in one transfer to avoid data inconsistency */
if (spi_rtc_io(inbuf, outbuf, 8))
return 0;
second = outbuf[1];
BCD_TO_BIN(second);
minute = outbuf[2];
BCD_TO_BIN(minute);
if (srtc_24h) {
hour = outbuf[3];
BCD_TO_BIN(hour);
} else {
hour = outbuf[3] & ~Rx5C348_BIT_PM;
BCD_TO_BIN(hour);
hour %= 12;
if (outbuf[3] & Rx5C348_BIT_PM)
hour += 12;
}
day = outbuf[5];
BCD_TO_BIN(day);
month = outbuf[6] & ~Rx5C348_BIT_Y2K;
BCD_TO_BIN(month);
year = outbuf[7];
BCD_TO_BIN(year);
year += EPOCH;
return mktime(year, month, day, hour, minute, second);
}
void __init
rtc_rx5c348_init(int chipid)
{
unsigned char inbuf[2], outbuf[2];
srtc_chipid = chipid;
/* turn on RTC if it is not on */
inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL2);
inbuf[1] = 0;
spi_rtc_io(inbuf, outbuf, 2);
if (outbuf[1] & Rx5C348_BIT_XSTP) {
inbuf[0] = Rx5C348_CMD_W(Rx5C348_REG_CTL2);
inbuf[1] = 0;
spi_rtc_io(inbuf, NULL, 2);
}
inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL1);
inbuf[1] = 0;
spi_rtc_io(inbuf, outbuf, 2);
if (outbuf[1] & Rx5C348_BIT_24H)
srtc_24h = 1;
/* set the function pointers */
rtc_get_time = rtc_rx5c348_get_time;
rtc_set_time = rtc_rx5c348_set_time;
}
/*
* linux/arch/mips/tx4938/common/setup.c
*
* common tx4938 setup routines
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/irq.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/time.h>
#include <asm/tx4938/rbtx4938.h>
extern void toshiba_rbtx4938_setup(void);
extern void rbtx4938_time_init(void);
void __init tx4938_setup(void);
void __init tx4938_time_init(void);
void __init tx4938_timer_setup(struct irqaction *irq);
void dump_cp0(char *key);
void (*__wbflush) (void);
static void
tx4938_write_buffer_flush(void)
{
mmiowb();
__asm__ __volatile__(
".set push\n\t"
".set noreorder\n\t"
"lw $0,%0\n\t"
"nop\n\t"
".set pop"
: /* no output */
: "m" (*(int *)KSEG1)
: "memory");
}
void __init
plat_setup(void)
{
board_time_init = tx4938_time_init;
board_timer_setup = tx4938_timer_setup;
__wbflush = tx4938_write_buffer_flush;
toshiba_rbtx4938_setup();
}
void __init
tx4938_time_init(void)
{
rbtx4938_time_init();
}
void __init
tx4938_timer_setup(struct irqaction *irq)
{
u32 count;
u32 c1;
u32 c2;
setup_irq(TX4938_IRQ_CPU_TIMER, irq);
c1 = read_c0_count();
count = c1 + (mips_hpt_frequency / HZ);
write_c0_compare(count);
c2 = read_c0_count();
}
#
# Makefile for common code for Toshiba TX4927 based systems
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
obj-y += prom.o setup.o irq.o spi_eeprom.o spi_txx9.o
/*
* linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c
*
* Toshiba RBTX4938 specific interrupt handlers
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
/*
IRQ Device
16 TX4938-CP0/00 Software 0
17 TX4938-CP0/01 Software 1
18 TX4938-CP0/02 Cascade TX4938-CP0
19 TX4938-CP0/03 Multiplexed -- do not use
20 TX4938-CP0/04 Multiplexed -- do not use
21 TX4938-CP0/05 Multiplexed -- do not use
22 TX4938-CP0/06 Multiplexed -- do not use
23 TX4938-CP0/07 CPU TIMER
24 TX4938-PIC/00
25 TX4938-PIC/01
26 TX4938-PIC/02 Cascade RBTX4938-IOC
27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
28 TX4938-PIC/04
29 TX4938-PIC/05 TX4938 ETH1
30 TX4938-PIC/06 TX4938 ETH0
31 TX4938-PIC/07
32 TX4938-PIC/08 TX4938 SIO 0
33 TX4938-PIC/09 TX4938 SIO 1
34 TX4938-PIC/10 TX4938 DMA0
35 TX4938-PIC/11 TX4938 DMA1
36 TX4938-PIC/12 TX4938 DMA2
37 TX4938-PIC/13 TX4938 DMA3
38 TX4938-PIC/14
39 TX4938-PIC/15
40 TX4938-PIC/16 TX4938 PCIC
41 TX4938-PIC/17 TX4938 TMR0
42 TX4938-PIC/18 TX4938 TMR1
43 TX4938-PIC/19 TX4938 TMR2
44 TX4938-PIC/20
45 TX4938-PIC/21
46 TX4938-PIC/22 TX4938 PCIERR
47 TX4938-PIC/23
48 TX4938-PIC/24
49 TX4938-PIC/25
50 TX4938-PIC/26
51 TX4938-PIC/27
52 TX4938-PIC/28
53 TX4938-PIC/29
54 TX4938-PIC/30
55 TX4938-PIC/31 TX4938 SPI
56 RBTX4938-IOC/00 PCI-D
57 RBTX4938-IOC/01 PCI-C
58 RBTX4938-IOC/02 PCI-B
59 RBTX4938-IOC/03 PCI-A
60 RBTX4938-IOC/04 RTC
61 RBTX4938-IOC/05 ATA
62 RBTX4938-IOC/06 MODEM
63 RBTX4938-IOC/07 SWINT
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timex.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <linux/version.h>
#include <linux/bootmem.h>
#include <asm/tx4938/rbtx4938.h>
static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq);
static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq);
static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq);
static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock);
#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
static struct hw_interrupt_type toshiba_rbtx4938_irq_ioc_type = {
.typename = TOSHIBA_RBTX4938_IOC_NAME,
.startup = toshiba_rbtx4938_irq_ioc_startup,
.shutdown = toshiba_rbtx4938_irq_ioc_shutdown,
.enable = toshiba_rbtx4938_irq_ioc_enable,
.disable = toshiba_rbtx4938_irq_ioc_disable,
.ack = toshiba_rbtx4938_irq_ioc_mask_and_ack,
.end = toshiba_rbtx4938_irq_ioc_end,
.set_affinity = NULL
};
#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a
int
toshiba_rbtx4938_irq_nested(int sw_irq)
{
u8 level3;
level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff;
if (level3) {
/* must use fls so onboard ATA has priority */
sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
}
wbflush();
return sw_irq;
}
static struct irqaction toshiba_rbtx4938_irq_ioc_action = {
.handler = no_action,
.flags = 0,
.mask = CPU_MASK_NONE,
.name = TOSHIBA_RBTX4938_IOC_NAME,
};
/**********************************************************************************/
/* Functions for ioc */
/**********************************************************************************/
static void __init
toshiba_rbtx4938_irq_ioc_init(void)
{
int i;
for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 3;
irq_desc[i].handler = &toshiba_rbtx4938_irq_ioc_type;
}
setup_irq(RBTX4938_IRQ_IOCINT,
&toshiba_rbtx4938_irq_ioc_action);
}
static unsigned int
toshiba_rbtx4938_irq_ioc_startup(unsigned int irq)
{
toshiba_rbtx4938_irq_ioc_enable(irq);
return 0;
}
static void
toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq)
{
toshiba_rbtx4938_irq_ioc_disable(irq);
}
static void
toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
{
unsigned long flags;
volatile unsigned char v;
spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
mmiowb();
TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
}
static void
toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
{
unsigned long flags;
volatile unsigned char v;
spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
mmiowb();
TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
}
static void
toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq)
{
toshiba_rbtx4938_irq_ioc_disable(irq);
}
static void
toshiba_rbtx4938_irq_ioc_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
toshiba_rbtx4938_irq_ioc_enable(irq);
}
}
extern void __init txx9_spi_irqinit(int irc_irq);
void __init arch_init_irq(void)
{
extern void tx4938_irq_init(void);
/* Now, interrupt control disabled, */
/* all IRC interrupts are masked, */
/* all IRC interrupt mode are Low Active. */
/* mask all IOC interrupts */
*rbtx4938_imask_ptr = 0;
/* clear SoftInt interrupts */
*rbtx4938_softint_ptr = 0;
tx4938_irq_init();
toshiba_rbtx4938_irq_ioc_init();
/* Onboard 10M Ether: High Active */
TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040);
if (tx4938_ccfgptr->pcfg & TX4938_PCFG_SPI_SEL) {
txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI);
}
wbflush();
}
/*
* linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c
*
* rbtx4938 specific prom routines
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/tx4938/tx4938.h>
void __init prom_init_cmdline(void)
{
int argc = (int) fw_arg0;
char **argv = (char **) fw_arg1;
int i;
/* ignore all built-in args if any f/w args given */
if (argc > 1) {
*arcs_cmdline = '\0';
}
for (i = 1; i < argc; i++) {
if (i != 1) {
strcat(arcs_cmdline, " ");
}
strcat(arcs_cmdline, argv[i]);
}
}
void __init prom_init(void)
{
extern int tx4938_get_mem_size(void);
int msize;
#ifndef CONFIG_TX4938_NAND_BOOT
prom_init_cmdline();
#endif
mips_machgroup = MACH_GROUP_TOSHIBA;
mips_machtype = MACH_TOSHIBA_RBTX4938;
msize = tx4938_get_mem_size();
add_memory_region(0, msize << 20, BOOT_MEM_RAM);
return;
}
unsigned long __init prom_free_prom_memory(void)
{
return 0;
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
return;
}
const char *get_system_type(void)
{
return "Toshiba RBTX4938";
}
char * __init prom_getcmdline(void)
{
return &(arcs_cmdline[0]);
}
This diff is collapsed.
/*
* linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/spinlock.h>
#include <asm/tx4938/spi.h>
#include <asm/tx4938/tx4938.h>
/* ATMEL 250x0 instructions */
#define ATMEL_WREN 0x06
#define ATMEL_WRDI 0x04
#define ATMEL_RDSR 0x05
#define ATMEL_WRSR 0x01
#define ATMEL_READ 0x03
#define ATMEL_WRITE 0x02
#define ATMEL_SR_BSY 0x01
#define ATMEL_SR_WEN 0x02
#define ATMEL_SR_BP0 0x04
#define ATMEL_SR_BP1 0x08
DEFINE_SPINLOCK(spi_eeprom_lock);
static struct spi_dev_desc seeprom_dev_desc = {
.baud = 1500000, /* 1.5Mbps */
.tcss = 1,
.tcsh = 1,
.tcsr = 1,
.byteorder = 1, /* MSB-First */
.polarity = 0, /* High-Active */
.phase = 0, /* Sample-Then-Shift */
};
static inline int
spi_eeprom_io(int chipid,
unsigned char **inbufs, unsigned int *incounts,
unsigned char **outbufs, unsigned int *outcounts)
{
return txx9_spi_io(chipid, &seeprom_dev_desc,
inbufs, incounts, outbufs, outcounts, 0);
}
int spi_eeprom_write_enable(int chipid, int enable)
{
unsigned char inbuf[1];
unsigned char *inbufs[1];
unsigned int incounts[2];
unsigned long flags;
int stat;
inbuf[0] = enable ? ATMEL_WREN : ATMEL_WRDI;
inbufs[0] = inbuf;
incounts[0] = sizeof(inbuf);
incounts[1] = 0;
spin_lock_irqsave(&spi_eeprom_lock, flags);
stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
return stat;
}
static int spi_eeprom_read_status_nolock(int chipid)
{
unsigned char inbuf[2], outbuf[2];
unsigned char *inbufs[1], *outbufs[1];
unsigned int incounts[2], outcounts[2];
int stat;
inbuf[0] = ATMEL_RDSR;
inbuf[1] = 0;
inbufs[0] = inbuf;
incounts[0] = sizeof(inbuf);
incounts[1] = 0;
outbufs[0] = outbuf;
outcounts[0] = sizeof(outbuf);
outcounts[1] = 0;
stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
if (stat < 0)
return stat;
return outbuf[1];
}
int spi_eeprom_read_status(int chipid)
{
unsigned long flags;
int stat;
spin_lock_irqsave(&spi_eeprom_lock, flags);
stat = spi_eeprom_read_status_nolock(chipid);
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
return stat;
}
int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len)
{
unsigned char inbuf[2];
unsigned char *inbufs[2], *outbufs[2];
unsigned int incounts[2], outcounts[3];
unsigned long flags;
int stat;
inbuf[0] = ATMEL_READ;
inbuf[1] = address;
inbufs[0] = inbuf;
inbufs[1] = NULL;
incounts[0] = sizeof(inbuf);
incounts[1] = 0;
outbufs[0] = NULL;
outbufs[1] = buf;
outcounts[0] = 2;
outcounts[1] = len;
outcounts[2] = 0;
spin_lock_irqsave(&spi_eeprom_lock, flags);
stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
return stat;
}
int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len)
{
unsigned char inbuf[2];
unsigned char *inbufs[2];
unsigned int incounts[3];
unsigned long flags;
int i, stat;
if (address / 8 != (address + len - 1) / 8)
return -EINVAL;
stat = spi_eeprom_write_enable(chipid, 1);
if (stat < 0)
return stat;
stat = spi_eeprom_read_status(chipid);
if (stat < 0)
return stat;
if (!(stat & ATMEL_SR_WEN))
return -EPERM;
inbuf[0] = ATMEL_WRITE;
inbuf[1] = address;
inbufs[0] = inbuf;
inbufs[1] = buf;
incounts[0] = sizeof(inbuf);
incounts[1] = len;
incounts[2] = 0;
spin_lock_irqsave(&spi_eeprom_lock, flags);
stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
if (stat < 0)
goto unlock_return;
/* write start. max 10ms */
for (i = 10; i > 0; i--) {
int stat = spi_eeprom_read_status_nolock(chipid);
if (stat < 0)
goto unlock_return;
if (!(stat & ATMEL_SR_BSY))
break;
mdelay(1);
}
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
if (i == 0)
return -EIO;
return len;
unlock_return:
spin_unlock_irqrestore(&spi_eeprom_lock, flags);
return stat;
}
#ifdef CONFIG_PROC_FS
#define MAX_SIZE 0x80 /* for ATMEL 25010 */
static int spi_eeprom_read_proc(char *page, char **start, off_t off,
int count, int *eof, void *data)
{
unsigned int size = MAX_SIZE;
if (spi_eeprom_read((int)data, 0, (unsigned char *)page, size) < 0)
size = 0;
return size;
}
static int spi_eeprom_write_proc(struct file *file, const char *buffer,
unsigned long count, void *data)
{
unsigned int size = MAX_SIZE;
int i;
if (file->f_pos >= size)
return -EIO;
if (file->f_pos + count > size)
count = size - file->f_pos;
for (i = 0; i < count; i += 8) {
int len = count - i < 8 ? count - i : 8;
if (spi_eeprom_write((int)data, file->f_pos,
(unsigned char *)buffer, len) < 0) {
count = -EIO;
break;
}
buffer += len;
file->f_pos += len;
}
return count;
}
__init void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid)
{
struct proc_dir_entry *entry;
char name[128];
sprintf(name, "seeprom-%d", chipid);
entry = create_proc_entry(name, 0600, dir);
if (entry) {
entry->read_proc = spi_eeprom_read_proc;
entry->write_proc = spi_eeprom_write_proc;
entry->data = (void *)chipid;
}
}
#endif /* CONFIG_PROC_FS */
/*
* linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <asm/tx4938/spi.h>
#include <asm/tx4938/tx4938.h>
static int (*txx9_spi_cs_func)(int chipid, int on);
static DEFINE_SPINLOCK(txx9_spi_lock);
extern unsigned int txx9_gbus_clock;
#define SPI_FIFO_SIZE 4
void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on))
{
txx9_spi_cs_func = cs_func;
/* enter config mode */
tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
}
static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
static void txx9_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
/* disable rx intr */
tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
wake_up(&txx9_spi_wait);
}
static struct irqaction txx9_spi_action = {
txx9_spi_interrupt, 0, 0, "spi", NULL, NULL,
};
void __init txx9_spi_irqinit(int irc_irq)
{
setup_irq(irc_irq, &txx9_spi_action);
}
int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
unsigned char **inbufs, unsigned int *incounts,
unsigned char **outbufs, unsigned int *outcounts,
int cansleep)
{
unsigned int incount, outcount;
unsigned char *inp, *outp;
int ret;
unsigned long flags;
spin_lock_irqsave(&txx9_spi_lock, flags);
if ((tx4938_spiptr->mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE) {
spin_unlock_irqrestore(&txx9_spi_lock, flags);
return -EBUSY;
}
/* enter config mode */
tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
tx4938_spiptr->cr0 =
(desc->byteorder ? TXx9_SPCR0_SBOS : 0) |
(desc->polarity ? TXx9_SPCR0_SPOL : 0) |
(desc->phase ? TXx9_SPCR0_SPHA : 0) |
0x08;
tx4938_spiptr->cr1 =
(((TXX9_IMCLK + desc->baud) / (2 * desc->baud) - 1) << 8) |
0x08 /* 8 bit only */;
/* enter active mode */
tx4938_spiptr->mcr = TXx9_SPMCR_ACTIVE;
spin_unlock_irqrestore(&txx9_spi_lock, flags);
/* CS ON */
if ((ret = txx9_spi_cs_func(chipid, 1)) < 0) {
spin_unlock_irqrestore(&txx9_spi_lock, flags);
return ret;
}
udelay(desc->tcss);
/* do scatter IO */
inp = inbufs ? *inbufs : NULL;
outp = outbufs ? *outbufs : NULL;
incount = 0;
outcount = 0;
while (1) {
unsigned char data;
unsigned int count;
int i;
if (!incount) {
incount = incounts ? *incounts++ : 0;
inp = (incount && inbufs) ? *inbufs++ : NULL;
}
if (!outcount) {
outcount = outcounts ? *outcounts++ : 0;
outp = (outcount && outbufs) ? *outbufs++ : NULL;
}
if (!inp && !outp)
break;
count = SPI_FIFO_SIZE;
if (incount)
count = min(count, incount);
if (outcount)
count = min(count, outcount);
/* now tx must be idle... */
while (!(tx4938_spiptr->sr & TXx9_SPSR_SIDLE))
;
tx4938_spiptr->cr0 =
(tx4938_spiptr->cr0 & ~TXx9_SPCR0_RXIFL_MASK) |
((count - 1) << 12);
if (cansleep) {
/* enable rx intr */
tx4938_spiptr->cr0 |= TXx9_SPCR0_RBSIE;
}
/* send */
for (i = 0; i < count; i++)
tx4938_spiptr->dr = inp ? *inp++ : 0;
/* wait all rx data */
if (cansleep) {
wait_event(txx9_spi_wait,
tx4938_spiptr->sr & TXx9_SPSR_SRRDY);
} else {
while (!(tx4938_spiptr->sr & TXx9_SPSR_RBSI))
;
}
/* receive */
for (i = 0; i < count; i++) {
data = tx4938_spiptr->dr;
if (outp)
*outp++ = data;
}
if (incount)
incount -= count;
if (outcount)
outcount -= count;
}
/* CS OFF */
udelay(desc->tcsh);
txx9_spi_cs_func(chipid, 0);
udelay(desc->tcsr);
spin_lock_irqsave(&txx9_spi_lock, flags);
/* enter config mode */
tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
spin_unlock_irqrestore(&txx9_spi_lock, flags);
return 0;
}
...@@ -161,6 +161,7 @@ ...@@ -161,6 +161,7 @@
#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ #define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */
#define MACH_TOSHIBA_RBTX4927 4 #define MACH_TOSHIBA_RBTX4927 4
#define MACH_TOSHIBA_RBTX4937 5 #define MACH_TOSHIBA_RBTX4937 5
#define MACH_TOSHIBA_RBTX4938 6
#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ #define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
"RBTX4927", "RBTX4937" } "RBTX4927", "RBTX4937" }
......
/*
* linux/include/asm-mips/tx4938/rbtx4938.h
* Definitions for TX4937/TX4938
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#ifndef __ASM_TX_BOARDS_RBTX4938_H
#define __ASM_TX_BOARDS_RBTX4938_H
#include <asm/addrspace.h>
#include <asm/tx4938/tx4938.h>
/* CS */
#define RBTX4938_CE0 0x1c000000 /* 64M */
#define RBTX4938_CE2 0x17f00000 /* 1M */
/* Address map */
#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000)
#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002)
#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004)
#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006)
#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008)
#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000)
#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002)
#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004)
#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000)
#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002)
#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004)
#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006)
#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008)
#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a)
#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c)
#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000)
#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000)
#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002)
#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008)
#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a)
#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002)
#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004)
#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000)
/* Ethernet port address (Jumperless Mode (W12:Open)) */
#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
/* bits for ISTAT/IMASK/IMSTAT */
#define RBTX4938_INTB_PCID 0
#define RBTX4938_INTB_PCIC 1
#define RBTX4938_INTB_PCIB 2
#define RBTX4938_INTB_PCIA 3
#define RBTX4938_INTB_RTC 4
#define RBTX4938_INTB_ATA 5
#define RBTX4938_INTB_MODEM 6
#define RBTX4938_INTB_SWINT 7
#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
#define rbtx4938_fpga_rev_ptr \
((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
#define rbtx4938_led_ptr \
((volatile unsigned char *)RBTX4938_LED_ADDR)
#define rbtx4938_dipsw_ptr \
((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
#define rbtx4938_bdipsw_ptr \
((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
#define rbtx4938_imask_ptr \
((volatile unsigned char *)RBTX4938_IMASK_ADDR)
#define rbtx4938_imask2_ptr \
((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
#define rbtx4938_intpol_ptr \
((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
#define rbtx4938_istat_ptr \
((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
#define rbtx4938_istat2_ptr \
((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
#define rbtx4938_imstat_ptr \
((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
#define rbtx4938_imstat2_ptr \
((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
#define rbtx4938_softint_ptr \
((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
#define rbtx4938_piosel_ptr \
((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
#define rbtx4938_spics_ptr \
((volatile unsigned char *)RBTX4938_SPICS_ADDR)
#define rbtx4938_sfpwr_ptr \
((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
#define rbtx4938_sfvol_ptr \
((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
#define rbtx4938_softreset_ptr \
((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
#define rbtx4938_softresetlock_ptr \
((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
#define rbtx4938_pcireset_ptr \
((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
/* SPI */
#define RBTX4938_SEEPROM1_CHIPID 0
#define RBTX4938_SEEPROM2_CHIPID 1
#define RBTX4938_SEEPROM3_CHIPID 2
#define RBTX4938_SRTC_CHIPID 3
/*
* IRQ mappings
*/
#define RBTX4938_SOFT_INT0 0 /* not used */
#define RBTX4938_SOFT_INT1 1 /* not used */
#define RBTX4938_IRC_INT 2
#define RBTX4938_TIMER_INT 7
/* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
* IRQ hardware is supported.
*/
#define RBTX4938_NR_IRQ_LOCAL 8
#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
#define RBTX4938_NR_IRQ_IOC 8
#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */
#define MI8259_IRQ_ISA_RAW_END 15
#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */
#define TX4938_IRQ_CP0_RAW_END 7
#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */
#define TX4938_IRQ_PIC_RAW_END 31
#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */
#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */
#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */
#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */
#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */
#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */
#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1)
#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7)
#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0
#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7
#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG
#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n))
#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
/* IOC (PCI, etc) */
#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC)
/* Onboard 10M Ether */
#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
/* IRCR : Int. Control */
#define TX4938_IRCR_LOW 0x00000000
#define TX4938_IRCR_HIGH 0x00000001
#define TX4938_IRCR_DOWN 0x00000002
#define TX4938_IRCR_UP 0x00000003
#endif /* __ASM_TX_BOARDS_RBTX4938_H */
/*
* linux/include/asm-mips/tx4938/spi.h
* Definitions for TX4937/TX4938 SPI
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
#define __ASM_TX_BOARDS_TX4938_SPI_H
/* SPI */
struct spi_dev_desc {
unsigned int baud;
unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */
unsigned int polarity:1; /* 0:High-Active */
unsigned int phase:1; /* 0:Sample-Then-Shift */
};
extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
extern void txx9_spi_irqinit(int irc_irq) __init;
extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
unsigned char **inbufs, unsigned int *incounts,
unsigned char **outbufs, unsigned int *outcounts,
int cansleep);
extern int spi_eeprom_write_enable(int chipid, int enable);
extern int spi_eeprom_read_status(int chipid);
extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
#define TXX9_IMCLK (txx9_gbus_clock / 2)
/*
* SPI
*/
/* SPMCR : SPI Master Control */
#define TXx9_SPMCR_OPMODE 0xc0
#define TXx9_SPMCR_CONFIG 0x40
#define TXx9_SPMCR_ACTIVE 0x80
#define TXx9_SPMCR_SPSTP 0x02
#define TXx9_SPMCR_BCLR 0x01
/* SPCR0 : SPI Status */
#define TXx9_SPCR0_TXIFL_MASK 0xc000
#define TXx9_SPCR0_RXIFL_MASK 0x3000
#define TXx9_SPCR0_SIDIE 0x0800
#define TXx9_SPCR0_SOEIE 0x0400
#define TXx9_SPCR0_RBSIE 0x0200
#define TXx9_SPCR0_TBSIE 0x0100
#define TXx9_SPCR0_IFSPSE 0x0010
#define TXx9_SPCR0_SBOS 0x0004
#define TXx9_SPCR0_SPHA 0x0002
#define TXx9_SPCR0_SPOL 0x0001
/* SPSR : SPI Status */
#define TXx9_SPSR_TBSI 0x8000
#define TXx9_SPSR_RBSI 0x4000
#define TXx9_SPSR_TBS_MASK 0x3800
#define TXx9_SPSR_RBS_MASK 0x0700
#define TXx9_SPSR_SPOE 0x0080
#define TXx9_SPSR_IFSD 0x0008
#define TXx9_SPSR_SIDLE 0x0004
#define TXx9_SPSR_STRDY 0x0002
#define TXx9_SPSR_SRRDY 0x0001
#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
This diff is collapsed.
/*
* linux/include/asm-mips/tx4938/tx4938_bitmask.h
* Generic bitmask definitions
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*/
#ifndef TX4938_TX4938_MIPS_H
#define TX4938_TX4938_MIPS_H
#ifndef __ASSEMBLY__
#define reg_rd08(r) ((u8 )(*((vu8 *)(r))))
#define reg_rd16(r) ((u16)(*((vu16*)(r))))
#define reg_rd32(r) ((u32)(*((vu32*)(r))))
#define reg_rd64(r) ((u64)(*((vu64*)(r))))
#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v)))
#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v)))
#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v)))
#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v)))
typedef volatile __signed char vs8;
typedef volatile unsigned char vu8;
typedef volatile __signed short vs16;
typedef volatile unsigned short vu16;
typedef volatile __signed int vs32;
typedef volatile unsigned int vu32;
typedef s8 s08;
typedef vs8 vs08;
typedef u8 u08;
typedef vu8 vu08;
#if (_MIPS_SZLONG == 64)
typedef volatile __signed__ long vs64;
typedef volatile unsigned long vu64;
#else
typedef volatile __signed__ long long vs64;
typedef volatile unsigned long long vu64;
#endif
#endif
#endif
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment