Commit 2480c914 authored by WANG Xuerui's avatar WANG Xuerui Committed by Thomas Bogendoerfer

MIPS: add definitions for Loongson-specific CP0.Diag1 register

This 32-bit CP0 register is named GSCause in Loongson manuals. It carries
Loongson extended exception information. We name it Diag1 because we
fear the "GSCause" name might get changed in the future.
Reviewed-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarWANG Xuerui <git@xen0n.name>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent efd1b4ad
...@@ -86,6 +86,7 @@ ...@@ -86,6 +86,7 @@
#define CP0_XCONTEXT $20 #define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21 #define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22 #define CP0_DIAGNOSTIC $22
#define CP0_DIAGNOSTIC1 $22, 1
#define CP0_DEBUG $23 #define CP0_DEBUG $23
#define CP0_DEPC $24 #define CP0_DEPC $24
#define CP0_PERFORMANCE $25 #define CP0_PERFORMANCE $25
...@@ -1051,6 +1052,13 @@ ...@@ -1051,6 +1052,13 @@
/* Flush FTLB */ /* Flush FTLB */
#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13) #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
/*
* Diag1 (GSCause in Loongson-speak) fields
*/
/* Loongson-specific exception code (GSExcCode) */
#define LOONGSON_DIAG1_EXCCODE_SHIFT 2
#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)
/* CvmCtl register field definitions */ /* CvmCtl register field definitions */
#define CVMCTL_IPPCI_SHIFT 7 #define CVMCTL_IPPCI_SHIFT 7
#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT) #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment