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Commit 24e904bd authored by Kai Germaschewski's avatar Kai Germaschewski
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ISDN/HiSax: Simplify readreg()/writereg() use 

In many cases, readreg()/writereg() users can be simplified by
passing struct IsdnCardState instead of individual register
addresses.
parent e54c19cf
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Showing with 454 additions and 443 deletions
drivers/isdn/hisax/asuscom.c
View file @ 24e904bd
This diff is collapsed.
drivers/isdn/hisax/avm_a1p.c
View file @ 24e904bd
......@@ -59,55 +59,77 @@
static const char *avm_revision = "$Revision: 2.7.6.2 $";
static spinlock_t avm_a1p_lock = SPIN_LOCK_UNLOCKED;
static inline u_char
ReadISAC(struct IsdnCardState *cs, u_char offset)
static inline u8
readreg(struct IsdnCardState *cs, int offset, u8 adr)
{
unsigned long flags;
u_char ret;
u8 ret;
offset -= 0x20;
spin_lock_irqsave(&avm_a1p_lock, flags);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset);
ret = bytein(cs->hw.avm.cfg_reg+DATAREG_OFFSET);
byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, offset + adr - 0x20);
ret = bytein(cs->hw.avm.cfg_reg + DATAREG_OFFSET);
spin_unlock_irqrestore(&avm_a1p_lock, flags);
return ret;
}
static inline void
WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
writereg(struct IsdnCardState *cs, int offset, u8 adr, u8 value)
{
unsigned long flags;
offset -= 0x20;
spin_lock_irqsave(&avm_a1p_lock, flags);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET, offset + adr - 0x20);
byteout(cs->hw.avm.cfg_reg+DATAREG_OFFSET, value);
spin_unlock_irqrestore(&avm_a1p_lock, flags);
}
static inline void
ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
readfifo(struct IsdnCardState *cs, int offset, u8 *data, int size)
{
unsigned long flags;
spin_lock_irqsave(&avm_a1p_lock, flags);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET);
insb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size);
byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, offset);
insb(cs->hw.avm.cfg_reg + DATAREG_OFFSET, data, size);
spin_unlock_irqrestore(&avm_a1p_lock, flags);
return;
}
static inline void
WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
writefifo(struct IsdnCardState *cs, int offset, u8 *data, int size)
{
unsigned long flags;
spin_lock_irqsave(&avm_a1p_lock, flags);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET, offset);
outsb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size);
spin_unlock_irqrestore(&avm_a1p_lock, flags);
}
static inline u_char
ReadISAC(struct IsdnCardState *cs, u_char adr)
{
return readreg(cs, ISAC_REG_OFFSET, adr);
}
static inline void
WriteISAC(struct IsdnCardState *cs, u_char adr, u_char value)
{
writereg(cs, ISAC_REG_OFFSET, adr, value);
}
static inline void
ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
readfifo(cs, ISAC_FIFO_OFFSET, data, size);
}
static inline void
WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
writefifo(cs, ISAC_FIFO_OFFSET, data, size);
}
static struct dc_hw_ops isac_ops = {
.read_reg = ReadISAC,
.write_reg = WriteISAC,
......@@ -116,57 +138,27 @@ static struct dc_hw_ops isac_ops = {
};
static inline u_char
ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
ReadHSCX(struct IsdnCardState *cs, int hscx, u_char adr)
{
u_char ret;
unsigned long flags;
offset -= 0x20;
spin_lock_irqsave(&avm_a1p_lock, flags);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,
HSCX_REG_OFFSET+hscx*HSCX_CH_DIFF+offset);
ret = bytein(cs->hw.avm.cfg_reg+DATAREG_OFFSET);
spin_unlock_irqrestore(&avm_a1p_lock, flags);
return ret;
return readreg(cs, HSCX_REG_OFFSET + hscx*HSCX_CH_DIFF, adr);
}
static inline void
WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
WriteHSCX(struct IsdnCardState *cs, int hscx, u_char adr, u_char value)
{
unsigned long flags;
offset -= 0x20;
spin_lock_irqsave(&avm_a1p_lock, flags);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,
HSCX_REG_OFFSET+hscx*HSCX_CH_DIFF+offset);
byteout(cs->hw.avm.cfg_reg+DATAREG_OFFSET, value);
spin_unlock_irqrestore(&avm_a1p_lock, flags);
writereg(cs, HSCX_REG_OFFSET + hscx*HSCX_CH_DIFF, adr, value);
}
static inline void
ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u_char * data, int size)
{
unsigned long flags;
spin_lock_irqsave(&avm_a1p_lock, flags);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,
HSCX_FIFO_OFFSET+hscx*HSCX_CH_DIFF);
insb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size);
spin_unlock_irqrestore(&avm_a1p_lock, flags);
return readfifo(cs, HSCX_FIFO_OFFSET + hscx*HSCX_CH_DIFF, data, size);
}
static inline void
WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u_char * data, int size)
{
unsigned long flags;
spin_lock_irqsave(&avm_a1p_lock, flags);
byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,
HSCX_FIFO_OFFSET+hscx*HSCX_CH_DIFF);
outsb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size);
spin_unlock_irqrestore(&avm_a1p_lock, flags);
writefifo(cs, HSCX_FIFO_OFFSET + hscx*HSCX_CH_DIFF, data, size);
}
static struct bc_hw_ops hscx_ops = {
......
drivers/isdn/hisax/bkm_a8.c
View file @ 24e904bd
......@@ -41,47 +41,53 @@ static const char *sct_quadro_subtypes[] =
#define wordout(addr,val) outw(val,addr)
#define wordin(addr) inw(addr)
static inline u_char
readreg(unsigned int ale, unsigned int adr, u_char off)
static inline u8
readreg(struct IsdnCardState *cs, u8 off)
{
register u_char ret;
u8 ret;
unsigned long flags;
spin_lock_irqsave(&bkm_a8_lock, flags);
wordout(ale, off);
ret = wordin(adr) & 0xFF;
wordout(cs->hw.ax.base, off);
ret = wordin(cs->hw.ax.data_adr) & 0xFF;
spin_unlock_irqrestore(&bkm_a8_lock, flags);
return (ret);
}
static inline void
readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writereg(struct IsdnCardState *cs, u8 off, u8 data)
{
/* fifo read without cli because it's allready done */
int i;
wordout(ale, off);
for (i = 0; i < size; i++)
data[i] = wordin(adr) & 0xFF;
unsigned long flags;
spin_lock_irqsave(&bkm_a8_lock, flags);
wordout(cs->hw.ax.base, off);
wordout(cs->hw.ax.data_adr, data);
spin_unlock_irqrestore(&bkm_a8_lock, flags);
}
static inline void
writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
readfifo(struct IsdnCardState *cs, u8 off, u8 *data, int size)
{
int i;
unsigned long flags;
spin_lock_irqsave(&bkm_a8_lock, flags);
wordout(ale, off);
wordout(adr, data);
wordout(cs->hw.ax.base, off);
for (i = 0; i < size; i++)
data[i] = wordin(cs->hw.ax.data_adr) & 0xFF;
spin_unlock_irqrestore(&bkm_a8_lock, flags);
}
static inline void
writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writefifo(struct IsdnCardState *cs, u8 off, u8 *data, int size)
{
/* fifo write without cli because it's allready done */
int i;
wordout(ale, off);
unsigned long flags;
spin_lock_irqsave(&bkm_a8_lock, flags);
wordout(cs->hw.ax.base, off);
for (i = 0; i < size; i++)
wordout(adr, data[i]);
wordout(cs->hw.ax.data_adr, data[i]);
spin_unlock_irqrestore(&bkm_a8_lock, flags);
}
/* Interface functions */
......@@ -89,25 +95,25 @@ writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int siz
static u_char
ReadISAC(struct IsdnCardState *cs, u_char offset)
{
return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
return readreg(cs, offset | 0x80);
}
static void
WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
writereg(cs, offset | 0x80, value);
}
static void
ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
readfifo(cs, 0x80, data, size);
}
static void
WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
writefifo(cs, 0x80, data, size);
}
static struct dc_hw_ops isac_ops = {
......@@ -120,13 +126,13 @@ static struct dc_hw_ops isac_ops = {
static u_char
ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
return readreg(cs, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
writereg(cs, offset + (hscx ? 0x40 : 0), value);
}
static struct bc_hw_ops hscx_ops = {
......@@ -139,22 +145,21 @@ static void
set_ipac_active(struct IsdnCardState *cs, u_int active)
{
/* set irq mask */
writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
active ? 0xc0 : 0xff);
writereg(cs, IPAC_MASK, active ? 0xc0 : 0xff);
}
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
#define READHSCX(cs, nr, reg) readreg(cs, \
reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
(nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
(nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
......@@ -165,14 +170,14 @@ bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs)
u_char ista, val, icnt = 5;
spin_lock(&cs->lock);
ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
ista = readreg(cs, IPAC_ISTA);
if (!(ista & 0x3f)) /* not this IPAC */
goto unlock;
Start_IPAC:
if (cs->debug & L1_DEB_IPAC)
debugl1(cs, "IPAC ISTA %02X", ista);
if (ista & 0x0f) {
val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
val = readreg(cs, HSCX_ISTA + 0x40);
if (ista & 0x01)
val |= 0x01;
if (ista & 0x04)
......@@ -184,7 +189,7 @@ bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs)
}
}
if (ista & 0x20) {
val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
val = 0xfe & readreg(cs, ISAC_ISTA | 0x80);
if (val) {
isac_interrupt(cs, val);
}
......@@ -193,7 +198,7 @@ bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs)
val = 0x01;
isac_interrupt(cs, val);
}
ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
ista = readreg(cs, IPAC_ISTA);
if ((ista & 0x3f) && icnt) {
icnt--;
goto Start_IPAC;
......@@ -202,8 +207,8 @@ bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs)
printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n",
CardType[cs->typ],
sct_quadro_subtypes[cs->subtyp]);
writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
writereg(cs, IPAC_MASK, 0xFF);
writereg(cs, IPAC_MASK, 0xC0);
unlock:
spin_unlock(&cs->lock);
}
......@@ -402,15 +407,6 @@ setup_sct_quadro(struct IsdnCard *card)
return(0);
if (sct_alloc_io(pci_ioaddr5, 64))
return(0);
/* disable all IPAC */
writereg(pci_ioaddr5, pci_ioaddr5 + 4,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
IPAC_MASK, 0xFF);
writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
IPAC_MASK, 0xFF);
break;
case 2:
cs->hw.ax.base = pci_ioaddr4 + 0x08;
......@@ -428,8 +424,8 @@ setup_sct_quadro(struct IsdnCard *card)
return(0);
break;
}
/* For isac and hscx data path */
cs->hw.ax.data_adr = cs->hw.ax.base + 4;
writereg(cs, IPAC_MASK, 0xFF);
printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
CardType[card->typ],
......@@ -450,7 +446,7 @@ setup_sct_quadro(struct IsdnCard *card)
printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
CardType[card->typ],
sct_quadro_subtypes[cs->subtyp],
readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
readreg(cs, IPAC_ID));
return (1);
#else
printk(KERN_ERR "HiSax: bkm_a8 only supported on PCI Systems\n");
......
drivers/isdn/hisax/elsa.c
View file @ 24e904bd
This diff is collapsed.
drivers/isdn/hisax/ix1_micro.c
View file @ 24e904bd
......@@ -40,46 +40,51 @@ static spinlock_t ix1_micro_lock = SPIN_LOCK_UNLOCKED;
#define TIMEOUT 50
static inline u_char
readreg(unsigned int ale, unsigned int adr, u_char off)
static inline u8
readreg(struct IsdnCardState *cs, unsigned int adr, u8 off)
{
register u_char ret;
u8 ret;
unsigned long flags;
spin_lock_irqsave(&ix1_micro_lock, flags);
byteout(ale, off);
byteout(cs->hw.ix1.isac_ale, off);
ret = bytein(adr);
spin_unlock_irqrestore(&ix1_micro_lock, flags);
return (ret);
}
static inline void
readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
readfifo(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 * data, int size)
{
/* fifo read without cli because it's allready done */
unsigned long flags;
byteout(ale, off);
spin_lock_irqsave(&ix1_micro_lock, flags);
byteout(cs->hw.ix1.isac_ale, off);
insb(adr, data, size);
spin_unlock_irqrestore(&ix1_micro_lock, flags);
}
static inline void
writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
writereg(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 data)
{
unsigned long flags;
spin_lock_irqsave(&ix1_micro_lock, flags);
byteout(ale, off);
byteout(cs->hw.ix1.isac_ale, off);
byteout(adr, data);
spin_unlock_irqrestore(&ix1_micro_lock, flags);
}
static inline void
writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writefifo(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 * data, int size)
{
/* fifo write without cli because it's allready done */
byteout(ale, off);
unsigned long flags;
spin_lock_irqsave(&ix1_micro_lock, flags);
byteout(cs->hw.ix1.isac_ale, off);
outsb(adr, data, size);
spin_unlock_irqrestore(&ix1_micro_lock, flags);
}
/* Interface functions */
......@@ -87,25 +92,25 @@ writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int siz
static u_char
ReadISAC(struct IsdnCardState *cs, u_char offset)
{
return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset));
return readreg(cs, cs->hw.ix1.isac, offset);
}
static void
WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value);
writereg(cs, cs->hw.ix1.isac, offset, value);
}
static void
ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
readfifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size);
readfifo(cs, cs->hw.ix1.isac, 0, data, size);
}
static void
WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
writefifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size);
writefifo(cs, cs->hw.ix1.isac, 0, data, size);
}
static struct dc_hw_ops isac_ops = {
......@@ -118,15 +123,13 @@ static struct dc_hw_ops isac_ops = {
static u_char
ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return (readreg(cs->hw.ix1.hscx_ale,
cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0)));
return readreg(cs, cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
writereg(cs->hw.ix1.hscx_ale,
cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value);
writereg(cs, cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value);
}
static struct bc_hw_ops hscx_ops = {
......@@ -134,15 +137,15 @@ static struct bc_hw_ops hscx_ops = {
.write_reg = WriteHSCX,
};
#define READHSCX(cs, nr, reg) readreg(cs->hw.ix1.hscx_ale, \
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ix1.hscx_ale, \
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ix1.hscx_ale, \
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
......@@ -154,32 +157,32 @@ ix1micro_interrupt(int intno, void *dev_id, struct pt_regs *regs)
u_char val;
spin_lock(&cs->lock);
val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40);
val = readreg(cs, cs->hw.ix1.hscx, HSCX_ISTA + 0x40);
Start_HSCX:
if (val)
hscx_int_main(cs, val);
val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA);
val = readreg(cs, cs->hw.ix1.isac, ISAC_ISTA);
Start_ISAC:
if (val)
isac_interrupt(cs, val);
val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40);
val = readreg(cs, cs->hw.ix1.hscx, HSCX_ISTA + 0x40);
if (val) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX IntStat after IntRoutine");
goto Start_HSCX;
}
val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA);
val = readreg(cs, cs->hw.ix1.isac, ISAC_ISTA);
if (val) {
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ISAC IntStat after IntRoutine");
goto Start_ISAC;
}
writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF);
writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF);
writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF);
writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0);
writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0);
writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0);
writereg(cs, cs->hw.ix1.hscx, HSCX_MASK, 0xFF);
writereg(cs, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF);
writereg(cs, cs->hw.ix1.isac, ISAC_MASK, 0xFF);
writereg(cs, cs->hw.ix1.isac, ISAC_MASK, 0);
writereg(cs, cs->hw.ix1.hscx, HSCX_MASK, 0);
writereg(cs, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0);
spin_unlock(&cs->lock);
}
......@@ -291,7 +294,6 @@ setup_ix1micro(struct IsdnCard *card)
#endif
/* IO-Ports */
cs->hw.ix1.isac_ale = card->para[1] + ISAC_COMMAND_OFFSET;
cs->hw.ix1.hscx_ale = card->para[1] + HSCX_COMMAND_OFFSET;
cs->hw.ix1.isac = card->para[1] + ISAC_DATA_OFFSET;
cs->hw.ix1.hscx = card->para[1] + HSCX_DATA_OFFSET;
cs->hw.ix1.cfg_reg = card->para[1];
......
drivers/isdn/hisax/mic.c
View file @ 24e904bd
......@@ -31,14 +31,14 @@ static spinlock_t mic_lock = SPIN_LOCK_UNLOCKED;
/* CARD_ADR (Write) */
#define MIC_RESET 0x3 /* same as DOS driver */
static inline u_char
readreg(unsigned int ale, unsigned int adr, u_char off)
static inline u8
readreg(struct IsdnCardState *cs, unsigned int adr, u8 off)
{
register u_char ret;
u8 ret;
unsigned long flags;
spin_lock_irqsave(&mic_lock, flags);
byteout(ale, off);
byteout(cs->hw.mic.adr, off);
ret = bytein(adr);
spin_unlock_irqrestore(&mic_lock, flags);
......@@ -46,32 +46,36 @@ readreg(unsigned int ale, unsigned int adr, u_char off)
}
static inline void
readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writereg(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 data)
{
/* fifo read without cli because it's allready done */
unsigned long flags;
byteout(ale, off);
insb(adr, data, size);
spin_lock_irqsave(&mic_lock, flags);
byteout(cs->hw.mic.adr, off);
byteout(adr, data);
spin_unlock_irqrestore(&mic_lock, flags);
}
static inline void
writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
readfifo(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 * data, int size)
{
unsigned long flags;
spin_lock_irqsave(&mic_lock, flags);
byteout(ale, off);
byteout(adr, data);
byteout(cs->hw.mic.adr, off);
insb(adr, data, size);
spin_unlock_irqrestore(&mic_lock, flags);
}
static inline void
writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writefifo(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 * data, int size)
{
/* fifo write without cli because it's allready done */
byteout(ale, off);
unsigned long flags;
spin_lock_irqsave(&mic_lock, flags);
byteout(cs->hw.mic.adr, off);
outsb(adr, data, size);
spin_unlock_irqrestore(&mic_lock, flags);
}
/* Interface functions */
......@@ -79,25 +83,25 @@ writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int siz
static u_char
ReadISAC(struct IsdnCardState *cs, u_char offset)
{
return (readreg(cs->hw.mic.adr, cs->hw.mic.isac, offset));
return readreg(cs, cs->hw.mic.isac, offset);
}
static void
WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value);
writereg(cs, cs->hw.mic.isac, offset, value);
}
static void
ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
readfifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size);
readfifo(cs, cs->hw.mic.isac, 0, data, size);
}
static void
WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
writefifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size);
writefifo(cs, cs->hw.mic.isac, 0, data, size);
}
static struct dc_hw_ops isac_ops = {
......@@ -110,15 +114,13 @@ static struct dc_hw_ops isac_ops = {
static u_char
ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return (readreg(cs->hw.mic.adr,
cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0)));
return readreg(cs, cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
writereg(cs->hw.mic.adr,
cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value);
writereg(cs, cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value);
}
static struct bc_hw_ops hscx_ops = {
......@@ -130,15 +132,15 @@ static struct bc_hw_ops hscx_ops = {
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs->hw.mic.adr, \
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.mic.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.mic.adr, \
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.mic.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.mic.adr, \
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.mic.adr, \
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
......@@ -150,32 +152,32 @@ mic_interrupt(int intno, void *dev_id, struct pt_regs *regs)
u_char val;
spin_lock(&cs->lock);
val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40);
val = readreg(cs, cs->hw.mic.hscx, HSCX_ISTA + 0x40);
Start_HSCX:
if (val)
hscx_int_main(cs, val);
val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA);
val = readreg(cs, cs->hw.mic.isac, ISAC_ISTA);
Start_ISAC:
if (val)
isac_interrupt(cs, val);
val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40);
val = readreg(cs, cs->hw.mic.hscx, HSCX_ISTA + 0x40);
if (val) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX IntStat after IntRoutine");
goto Start_HSCX;
}
val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA);
val = readreg(cs, cs->hw.mic.isac, ISAC_ISTA);
if (val) {
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ISAC IntStat after IntRoutine");
goto Start_ISAC;
}
writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF);
writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF);
writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0xFF);
writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0x0);
writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0);
writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0);
writereg(cs, cs->hw.mic.hscx, HSCX_MASK, 0xFF);
writereg(cs, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF);
writereg(cs, cs->hw.mic.isac, ISAC_MASK, 0xFF);
writereg(cs, cs->hw.mic.isac, ISAC_MASK, 0x0);
writereg(cs, cs->hw.mic.hscx, HSCX_MASK, 0x0);
writereg(cs, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0);
spin_unlock(&cs->lock);
}
......
drivers/isdn/hisax/niccy.c
View file @ 24e904bd
......@@ -47,46 +47,50 @@ static spinlock_t niccy_lock = SPIN_LOCK_UNLOCKED;
#define PCI_IRQ_DISABLE 0xff0000
#define PCI_IRQ_ASSERT 0x800000
static inline u_char
readreg(unsigned int ale, unsigned int adr, u_char off)
static inline u8
readreg(unsigned int ale, unsigned int adr, u8 off)
{
register u_char ret;
u8 ret;
unsigned long flags;
spin_lock_irqsave(&niccy_lock, flags);
byteout(ale, off);
ret = bytein(adr);
spin_unlock_irqrestore(&niccy_lock, flags);
return (ret);
return ret;
}
static inline void
readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writereg(unsigned int ale, unsigned int adr, u8 off, u8 data)
{
/* fifo read without cli because it's allready done */
unsigned long flags;
spin_lock_irqsave(&niccy_lock, flags);
byteout(ale, off);
insb(adr, data, size);
byteout(adr, data);
spin_unlock_irqrestore(&niccy_lock, flags);
}
static inline void
writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
readfifo(unsigned int ale, unsigned int adr, u8 off, u8 * data, int size)
{
unsigned long flags;
spin_lock_irqsave(&niccy_lock, flags);
byteout(ale, off);
byteout(adr, data);
insb(adr, data, size);
spin_unlock_irqrestore(&niccy_lock, flags);
}
static inline void
writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writefifo(unsigned int ale, unsigned int adr, u8 off, u8 * data, int size)
{
/* fifo write without cli because it's allready done */
unsigned long flags;
spin_lock_irqsave(&niccy_lock, flags);
byteout(ale, off);
outsb(adr, data, size);
spin_unlock_irqrestore(&niccy_lock, flags);
}
/* Interface functions */
......
drivers/isdn/hisax/s0box.c
View file @ 24e904bd
......@@ -21,8 +21,10 @@ const char *s0box_revision = "$Revision: 2.4.6.2 $";
static spinlock_t s0box_lock = SPIN_LOCK_UNLOCKED;
static inline void
writereg(unsigned int padr, signed int addr, u_char off, u_char val) {
writereg(struct IsdnCardState *cs, int addr, u8 off, u8 val)
{
unsigned long flags;
unsigned long padr = cs->hw.teles3.cfg_reg;
spin_lock_irqsave(&s0box_lock, flags);
outb_p(0x1c,padr+2);
......@@ -36,14 +38,16 @@ writereg(unsigned int padr, signed int addr, u_char off, u_char val) {
spin_unlock_irqrestore(&s0box_lock, flags);
}
static u_char nibtab[] = { 1, 9, 5, 0xd, 3, 0xb, 7, 0xf,
static u8 nibtab[] = { 1, 9, 5, 0xd, 3, 0xb, 7, 0xf,
0, 0, 0, 0, 0, 0, 0, 0,
0, 8, 4, 0xc, 2, 0xa, 6, 0xe } ;
static inline u_char
readreg(unsigned int padr, signed int addr, u_char off) {
register u_char n1, n2;
static inline u8
readreg(struct IsdnCardState *cs, int addr, u8 off)
{
u8 n1, n2;
unsigned long flags;
unsigned long padr = cs->hw.teles3.cfg_reg;
spin_lock_irqsave(&s0box_lock, flags);
outb_p(0x1c,padr+2);
......@@ -61,10 +65,11 @@ readreg(unsigned int padr, signed int addr, u_char off) {
}
static inline void
read_fifo(unsigned int padr, signed int adr, u_char * data, int size)
read_fifo(struct IsdnCardState *cs, signed int adr, u8 * data, int size)
{
int i;
register u_char n1, n2;
u8 n1, n2;
unsigned long padr = cs->hw.teles3.cfg_reg;
outb_p(0x1c, padr+2);
outb_p(0x14, padr+2);
......@@ -79,13 +84,14 @@ read_fifo(unsigned int padr, signed int adr, u_char * data, int size)
}
outb_p(0x14,padr+2);
outb_p(0x1c,padr+2);
return;
}
static inline void
write_fifo(unsigned int padr, signed int adr, u_char * data, int size)
write_fifo(struct IsdnCardState *cs, signed int adr, u8 * data, int size)
{
int i;
unsigned long padr = cs->hw.teles3.cfg_reg;
outb_p(0x1c, padr+2);
outb_p(0x14, padr+2);
outb_p(adr&0x7f, padr);
......@@ -96,7 +102,6 @@ write_fifo(unsigned int padr, signed int adr, u_char * data, int size)
}
outb_p(0x14,padr+2);
outb_p(0x1c,padr+2);
return;
}
/* Interface functions */
......@@ -104,25 +109,25 @@ write_fifo(unsigned int padr, signed int adr, u_char * data, int size)
static u_char
ReadISAC(struct IsdnCardState *cs, u_char offset)
{
return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset));
return readreg(cs, cs->hw.teles3.isac, offset);
}
static void
WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value);
writereg(cs, cs->hw.teles3.isac, offset, value);
}
static void
ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size);
read_fifo(cs, cs->hw.teles3.isacfifo, data, size);
}
static void
WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size);
write_fifo(cs, cs->hw.teles3.isacfifo, data, size);
}
static struct dc_hw_ops isac_ops = {
......@@ -135,13 +140,13 @@ static struct dc_hw_ops isac_ops = {
static u_char
ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset));
return readreg(cs, cs->hw.teles3.hscx[hscx], offset);
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value);
writereg(cs, cs->hw.teles3.hscx[hscx], offset, value);
}
static struct bc_hw_ops hscx_ops = {
......@@ -153,10 +158,10 @@ static struct bc_hw_ops hscx_ops = {
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg)
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
#define READHSCX(cs, nr, reg) readreg(cs, cs->hw.teles3.hscx[nr], reg)
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, cs->hw.teles3.hscx[nr], reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
#include "hscx_irq.c"
......@@ -169,22 +174,22 @@ s0box_interrupt(int intno, void *dev_id, struct pt_regs *regs)
int count = 0;
spin_lock(&cs->lock);
val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA);
val = readreg(cs, cs->hw.teles3.hscx[1], HSCX_ISTA);
Start_HSCX:
if (val)
hscx_int_main(cs, val);
val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA);
val = readreg(cs, cs->hw.teles3.isac, ISAC_ISTA);
Start_ISAC:
if (val)
isac_interrupt(cs, val);
count++;
val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA);
val = readreg(cs, cs->hw.teles3.hscx[1], HSCX_ISTA);
if (val && count < MAXCOUNT) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX IntStat after IntRoutine");
goto Start_HSCX;
}
val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA);
val = readreg(cs, cs->hw.teles3.isac, ISAC_ISTA);
if (val && count < MAXCOUNT) {
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ISAC IntStat after IntRoutine");
......@@ -192,12 +197,12 @@ s0box_interrupt(int intno, void *dev_id, struct pt_regs *regs)
}
if (count >= MAXCOUNT)
printk(KERN_WARNING "S0Box: more than %d loops in s0box_interrupt\n", count);
writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF);
writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF);
writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0xFF);
writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0x0);
writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0);
writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0);
writereg(cs, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF);
writereg(cs, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF);
writereg(cs, cs->hw.teles3.isac, ISAC_MASK, 0xFF);
writereg(cs, cs->hw.teles3.isac, ISAC_MASK, 0x0);
writereg(cs, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0);
writereg(cs, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0);
spin_unlock(&cs->lock);
}
......
drivers/isdn/hisax/saphir.c
View file @ 24e904bd
......@@ -32,46 +32,50 @@ static spinlock_t saphir_lock = SPIN_LOCK_UNLOCKED;
#define SPARE_REG 4
#define RESET_REG 5
static inline u_char
readreg(unsigned int ale, unsigned int adr, u_char off)
static inline u8
readreg(struct IsdnCardState *cs, unsigned int adr, u8 off)
{
register u_char ret;
u8 ret;
unsigned long flags;
spin_lock_irqsave(&saphir_lock, flags);
byteout(ale, off);
byteout(cs->hw.saphir.ale, off);
ret = bytein(adr);
spin_unlock_irqrestore(&saphir_lock, flags);
return (ret);
return ret;
}
static inline void
readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writereg(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 data)
{
/* fifo read without cli because it's allready done */
unsigned long flags;
byteout(ale, off);
insb(adr, data, size);
spin_lock_irqsave(&saphir_lock, flags);
byteout(cs->hw.saphir.ale, off);
byteout(adr, data);
spin_unlock_irqrestore(&saphir_lock, flags);
}
static inline void
writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
readfifo(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 *data, int size)
{
unsigned long flags;
spin_lock_irqsave(&saphir_lock, flags);
byteout(ale, off);
byteout(adr, data);
byteout(cs->hw.saphir.ale, off);
insb(adr, data, size);
spin_unlock_irqrestore(&saphir_lock, flags);
}
static inline void
writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
writefifo(struct IsdnCardState *cs, unsigned int adr, u8 off, u8 *data, int size)
{
/* fifo write without cli because it's allready done */
byteout(ale, off);
unsigned long flags;
spin_lock_irqsave(&saphir_lock, flags);
byteout(cs->hw.saphir.ale, off);
outsb(adr, data, size);
spin_unlock_irqrestore(&saphir_lock, flags);
}
/* Interface functions */
......@@ -79,25 +83,25 @@ writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int siz
static u_char
ReadISAC(struct IsdnCardState *cs, u_char offset)
{
return (readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset));
return readreg(cs, cs->hw.saphir.isac, offset);
}
static void
WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
{
writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value);
writereg(cs, cs->hw.saphir.isac, offset, value);
}
static void
ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
readfifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size);
readfifo(cs, cs->hw.saphir.isac, 0, data, size);
}
static void
WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
{
writefifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size);
writefifo(cs, cs->hw.saphir.isac, 0, data, size);
}
static struct dc_hw_ops isac_ops = {
......@@ -110,15 +114,13 @@ static struct dc_hw_ops isac_ops = {
static u_char
ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
{
return (readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx,
offset + (hscx ? 0x40 : 0)));
return readreg(cs, cs->hw.saphir.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
{
writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx,
offset + (hscx ? 0x40 : 0), value);
writereg(cs, cs->hw.saphir.hscx, offset + (hscx ? 0x40 : 0), value);
}
static struct bc_hw_ops hscx_ops = {
......@@ -126,15 +128,15 @@ static struct bc_hw_ops hscx_ops = {
.write_reg = WriteHSCX,
};
#define READHSCX(cs, nr, reg) readreg(cs->hw.saphir.ale, \
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.saphir.ale, \
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.saphir.ale, \
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.saphir.ale, \
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
......@@ -146,21 +148,21 @@ saphir_interrupt(int intno, void *dev_id, struct pt_regs *regs)
u_char val;
spin_lock(&cs->lock);
val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40);
val = readreg(cs, cs->hw.saphir.hscx, HSCX_ISTA + 0x40);
Start_HSCX:
if (val)
hscx_int_main(cs, val);
val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA);
val = readreg(cs, cs->hw.saphir.isac, ISAC_ISTA);
Start_ISAC:
if (val)
isac_interrupt(cs, val);
val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40);
val = readreg(cs, cs->hw.saphir.hscx, HSCX_ISTA + 0x40);
if (val) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX IntStat after IntRoutine");
goto Start_HSCX;
}
val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA);
val = readreg(cs, cs->hw.saphir.isac, ISAC_ISTA);
if (val) {
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ISAC IntStat after IntRoutine");
......@@ -171,12 +173,12 @@ saphir_interrupt(int intno, void *dev_id, struct pt_regs *regs)
mod_timer(&cs->hw.saphir.timer, jiffies+1*HZ);
else
printk(KERN_WARNING "saphir: Spurious timer!\n");
writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF);
writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF);
writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF);
writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0);
writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0);
writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0);
writereg(cs, cs->hw.saphir.hscx, HSCX_MASK, 0xFF);
writereg(cs, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF);
writereg(cs, cs->hw.saphir.isac, ISAC_MASK, 0xFF);
writereg(cs, cs->hw.saphir.isac, ISAC_MASK, 0);
writereg(cs, cs->hw.saphir.hscx, HSCX_MASK, 0);
writereg(cs, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0);
spin_unlock(&cs->lock);
}
......
drivers/isdn/hisax/sedlbauer.c
View file @ 24e904bd
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