Commit 2539b258 authored by Will Deacon's avatar Will Deacon Committed by Greg Kroah-Hartman

drivers/base: cacheinfo: fix annoying typo when DT nodes are absent

s/hierarcy/hierarchy/

Maybe the typo will annoy people enough so that they add the missing
nodes to their device-tree files, but I still think this is better off
fixed.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Acked-by: default avatarSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ed1dc8a8
...@@ -243,7 +243,7 @@ Description: Parameters for the CPU cache attributes ...@@ -243,7 +243,7 @@ Description: Parameters for the CPU cache attributes
coherency_line_size: the minimum amount of data in bytes that gets coherency_line_size: the minimum amount of data in bytes that gets
transferred from memory to cache transferred from memory to cache
level: the cache hierarcy in the multi-level cache configuration level: the cache hierarchy in the multi-level cache configuration
number_of_sets: total number of sets in the cache, a set is a number_of_sets: total number of sets in the cache, a set is a
collection of cache lines with the same cache index collection of cache lines with the same cache index
......
...@@ -191,12 +191,12 @@ static int detect_cache_attributes(unsigned int cpu) ...@@ -191,12 +191,12 @@ static int detect_cache_attributes(unsigned int cpu)
if (ret) if (ret)
goto free_ci; goto free_ci;
/* /*
* For systems using DT for cache hierarcy, of_node and shared_cpu_map * For systems using DT for cache hierarchy, of_node and shared_cpu_map
* will be set up here only if they are not populated already * will be set up here only if they are not populated already
*/ */
ret = cache_shared_cpu_map_setup(cpu); ret = cache_shared_cpu_map_setup(cpu);
if (ret) { if (ret) {
pr_warn("Unable to detect cache hierarcy from DT for CPU %d\n", pr_warn("Unable to detect cache hierarchy from DT for CPU %d\n",
cpu); cpu);
goto free_ci; goto free_ci;
} }
......
...@@ -19,7 +19,7 @@ enum cache_type { ...@@ -19,7 +19,7 @@ enum cache_type {
/** /**
* struct cacheinfo - represent a cache leaf node * struct cacheinfo - represent a cache leaf node
* @type: type of the cache - data, inst or unified * @type: type of the cache - data, inst or unified
* @level: represents the hierarcy in the multi-level cache * @level: represents the hierarchy in the multi-level cache
* @coherency_line_size: size of each cache line usually representing * @coherency_line_size: size of each cache line usually representing
* the minimum amount of data that gets transferred from memory * the minimum amount of data that gets transferred from memory
* @number_of_sets: total number of sets, a set is a collection of cache * @number_of_sets: total number of sets, a set is a collection of cache
......
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