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Commit 254cd2e0 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
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drm/amdgpu: read hw register to check pg status. 

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d50e5c24
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Inline Side-by-side
Showing with 22 additions and 14 deletions
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View file @ 254cd2e0
......@@ -1037,7 +1037,6 @@ struct amdgpu_uvd {
bool use_ctx_buf;
struct amd_sched_entity entity;
uint32_t srbm_soft_reset;
bool is_powergated;
};
/*
......@@ -1066,7 +1065,6 @@ struct amdgpu_vce {
struct amd_sched_entity entity;
uint32_t srbm_soft_reset;
unsigned num_rings;
bool is_powergated;
};
/*
......
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
View file @ 254cd2e0
......@@ -723,7 +723,8 @@ static int uvd_v4_2_set_powergating_state(void *handle,
if (state == AMD_PG_STATE_GATE) {
uvd_v4_2_stop(adev);
if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4)) {
if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) {
WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK |
UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
......@@ -733,7 +734,8 @@ static int uvd_v4_2_set_powergating_state(void *handle,
return 0;
} else {
if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
if (RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4) {
if (RREG32_SMC(ixCURRENT_PG_STATUS) &
CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |
UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK |
UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
......
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
View file @ 254cd2e0
......@@ -825,12 +825,10 @@ static int uvd_v5_0_set_powergating_state(void *handle,
if (state == AMD_PG_STATE_GATE) {
uvd_v5_0_stop(adev);
adev->uvd.is_powergated = true;
} else {
ret = uvd_v5_0_start(adev);
if (ret)
goto out;
adev->uvd.is_powergated = false;
}
out:
......@@ -844,7 +842,8 @@ static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
mutex_lock(&adev->pm.mutex);
if (adev->uvd.is_powergated) {
if (RREG32_SMC(ixCURRENT_PG_STATUS) &
CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
goto out;
}
......
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
View file @ 254cd2e0
......@@ -1051,12 +1051,10 @@ static int uvd_v6_0_set_powergating_state(void *handle,
if (state == AMD_PG_STATE_GATE) {
uvd_v6_0_stop(adev);
adev->uvd.is_powergated = true;
} else {
ret = uvd_v6_0_start(adev);
if (ret)
goto out;
adev->uvd.is_powergated = false;
}
out:
......@@ -1070,7 +1068,8 @@ static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
mutex_lock(&adev->pm.mutex);
if (adev->uvd.is_powergated) {
if (RREG32_SMC(ixCURRENT_PG_STATUS) &
CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
goto out;
}
......
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
View file @ 254cd2e0
......@@ -768,12 +768,10 @@ static int vce_v3_0_set_powergating_state(void *handle,
ret = vce_v3_0_stop(adev);
if (ret)
goto out;
adev->vce.is_powergated = true;
} else {
ret = vce_v3_0_start(adev);
if (ret)
goto out;
adev->vce.is_powergated = false;
}
out:
......@@ -787,7 +785,8 @@ static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)
mutex_lock(&adev->pm.mutex);
if (adev->vce.is_powergated) {
if (RREG32_SMC(ixCURRENT_PG_STATUS) &
CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) {
DRM_INFO("Cannot get clockgating state when VCE is powergated.\n");
goto out;
}
......
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
View file @ 254cd2e0
......@@ -5452,5 +5452,7 @@
#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
#endif /* SMU_7_0_1_SH_MASK_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
View file @ 254cd2e0
......@@ -1121,5 +1121,6 @@
#define ixROM_SW_DATA_62 0xc060011c
#define ixROM_SW_DATA_63 0xc0600120
#define ixROM_SW_DATA_64 0xc0600124
#define ixCURRENT_PG_STATUS 0xc020029c
#endif /* SMU_7_1_1_D_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
View file @ 254cd2e0
......@@ -4860,5 +4860,7 @@
#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
#endif /* SMU_7_1_1_SH_MASK_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
View file @ 254cd2e0
......@@ -1271,5 +1271,6 @@
#define ixROM_SW_DATA_62 0xc060011c
#define ixROM_SW_DATA_63 0xc0600120
#define ixROM_SW_DATA_64 0xc0600124
#define ixCURRENT_PG_STATUS 0xc020029c
#endif /* SMU_7_1_2_D_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
View file @ 254cd2e0
......@@ -5830,5 +5830,7 @@
#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
#endif /* SMU_7_1_2_SH_MASK_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
View file @ 254cd2e0
......@@ -1244,5 +1244,5 @@
#define ixGC_CAC_ACC_CU14 0xc8
#define ixGC_CAC_ACC_CU15 0xc9
#define ixGC_CAC_OVRD_CU 0xe7
#define ixCURRENT_PG_STATUS 0xc020029c
#endif /* SMU_7_1_3_D_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
View file @ 254cd2e0
......@@ -6076,5 +6076,8 @@
#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000
#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10
#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
#endif /* SMU_7_1_3_SH_MASK_H */
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