Commit 25c0f301 authored by Miaoqing Pan's avatar Miaoqing Pan Committed by Kalle Valo

ath9k: clear bb filter calibration power threshold

JP WiFi certification for bandwidth of channel 14 failed, the OBW
is lower than the requirement. Clear the bb filter calibration power
threshold to increase OBW(+2). The fix only for qca9531 chip now.
Signed-off-by: default avatarMiaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent e9a26010
...@@ -976,9 +976,14 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, ...@@ -976,9 +976,14 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
/* /*
* JAPAN regulatory. * JAPAN regulatory.
*/ */
if (chan->channel == 2484) if (chan->channel == 2484) {
ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
if (AR_SREV_9531(ah))
REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
AR_PHY_FLC_PWR_THRESH, 0);
}
ah->modes_index = modesIndex; ah->modes_index = modesIndex;
ar9003_hw_override_ini(ah); ar9003_hw_override_ini(ah);
ar9003_hw_set_channel_regs(ah, chan); ar9003_hw_set_channel_regs(ah, chan);
......
...@@ -487,6 +487,9 @@ ...@@ -487,6 +487,9 @@
#define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150) #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)
#define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158) #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)
#define AR_PHY_FLC_PWR_THRESH 7
#define AR_PHY_FLC_PWR_THRESH_S 0
#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3
#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment