Commit 25c45d89 authored by Archit Taneja's avatar Archit Taneja Committed by Rob Clark

drm/msm/dsi: Add a PHY op that initializes version specific stuff

Create an init() op for dsi_phy which sets up things specific to
a given DSI PHY.

The dsi_phy driver probe expects every DSI version to get a
"dsi_phy_regulator" mmio base. This isn't the case for 8x96.
Creating an init() op will allow us to accommodate such
differences.
Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 3a3ff88a
...@@ -295,6 +295,24 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy) ...@@ -295,6 +295,24 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy)
return -EINVAL; return -EINVAL;
} }
int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
int ret = 0;
phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
"DSI_PHY_REG");
if (IS_ERR(phy->reg_base)) {
dev_err(&pdev->dev, "%s: failed to map phy regulator base\n",
__func__);
ret = -ENOMEM;
goto fail;
}
fail:
return ret;
}
static int dsi_phy_driver_probe(struct platform_device *pdev) static int dsi_phy_driver_probe(struct platform_device *pdev)
{ {
struct msm_dsi_phy *phy; struct msm_dsi_phy *phy;
...@@ -331,15 +349,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) ...@@ -331,15 +349,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
goto fail; goto fail;
} }
phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
"DSI_PHY_REG");
if (IS_ERR(phy->reg_base)) {
dev_err(dev, "%s: failed to map phy regulator base\n",
__func__);
ret = -ENOMEM;
goto fail;
}
ret = dsi_phy_regulator_init(phy); ret = dsi_phy_regulator_init(phy);
if (ret) { if (ret) {
dev_err(dev, "%s: failed to init regulator\n", __func__); dev_err(dev, "%s: failed to init regulator\n", __func__);
...@@ -353,6 +362,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) ...@@ -353,6 +362,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
goto fail; goto fail;
} }
if (phy->cfg->ops.init) {
ret = phy->cfg->ops.init(phy);
if (ret)
goto fail;
}
/* PLL init will call into clk_register which requires /* PLL init will call into clk_register which requires
* register access, so we need to enable power and ahb clock. * register access, so we need to enable power and ahb clock.
*/ */
......
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#define dsi_phy_write(offset, data) msm_writel((data), (offset)) #define dsi_phy_write(offset, data) msm_writel((data), (offset))
struct msm_dsi_phy_ops { struct msm_dsi_phy_ops {
int (*init) (struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
const unsigned long bit_rate, const unsigned long esc_rate); const unsigned long bit_rate, const unsigned long esc_rate);
void (*disable)(struct msm_dsi_phy *phy); void (*disable)(struct msm_dsi_phy *phy);
...@@ -87,6 +88,7 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, ...@@ -87,6 +88,7 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
const unsigned long bit_rate, const unsigned long esc_rate); const unsigned long bit_rate, const unsigned long esc_rate);
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
u32 bit_mask); u32 bit_mask);
int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
#endif /* __DSI_PHY_H__ */ #endif /* __DSI_PHY_H__ */
...@@ -145,6 +145,7 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { ...@@ -145,6 +145,7 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
.ops = { .ops = {
.enable = dsi_20nm_phy_enable, .enable = dsi_20nm_phy_enable,
.disable = dsi_20nm_phy_disable, .disable = dsi_20nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0xfd998300, 0xfd9a0300 }, .io_start = { 0xfd998300, 0xfd9a0300 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
......
...@@ -144,6 +144,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { ...@@ -144,6 +144,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.ops = { .ops = {
.enable = dsi_28nm_phy_enable, .enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable, .disable = dsi_28nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0xfd922b00, 0xfd923100 }, .io_start = { 0xfd922b00, 0xfd923100 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
...@@ -161,6 +162,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { ...@@ -161,6 +162,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.ops = { .ops = {
.enable = dsi_28nm_phy_enable, .enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable, .disable = dsi_28nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0x1a98500 }, .io_start = { 0x1a98500 },
.num_dsi_phy = 1, .num_dsi_phy = 1,
......
...@@ -191,6 +191,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { ...@@ -191,6 +191,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.ops = { .ops = {
.enable = dsi_28nm_phy_enable, .enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable, .disable = dsi_28nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0x4700300, 0x5800300 }, .io_start = { 0x4700300, 0x5800300 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
......
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