Commit 25eb433a authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Nicolas Pitre

ARM: mach-msm: hook special idle handlers to arm_pm_idle

Signed-off-by: default avatarNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: default avatarDavid Brown <davidb@codeaurora.org>
parent 4a3ea244
/* arch/arm/mach-msm/include/mach/idle.S /* arch/arm/mach-msm/idle.c
* *
* Idle processing for MSM7K - work around bugs with SWFI. * Idle processing for MSM7K - work around bugs with SWFI.
* *
* Copyright (c) 2007 QUALCOMM Incorporated. * Copyright (c) 2007 QUALCOMM Incorporated.
* Copyright (C) 2007 Google, Inc. * Copyright (C) 2007 Google, Inc.
* *
* This software is licensed under the terms of the GNU General Public * This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and * License version 2, as published by the Free Software Foundation, and
...@@ -14,23 +14,36 @@ ...@@ -14,23 +14,36 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
*/ */
#include <linux/linkage.h>
#include <asm/assembler.h>
ENTRY(arch_idle) #include <linux/init.h>
#include <asm/system.h>
static void msm_idle(void)
{
#ifdef CONFIG_MSM7X00A_IDLE #ifdef CONFIG_MSM7X00A_IDLE
mrc p15, 0, r1, c1, c0, 0 /* read current CR */ asm volatile (
bic r0, r1, #(1 << 2) /* clear dcache bit */
bic r0, r0, #(1 << 12) /* clear icache bit */ "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t"
mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t"
"bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t"
"mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t"
"mov r0, #0 /* prepare wfi value */ \n\t"
"mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t"
"mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t"
"mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t"
mov r0, #0 /* prepare wfi value */ "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t"
mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ : : : "r0","r1" );
#endif #endif
mov pc, lr }
static int __init msm_idle_init(void)
{
arm_pm_idle = msm_idle;
return 0;
}
arch_initcall(msm_idle_init);
...@@ -12,7 +12,10 @@ ...@@ -12,7 +12,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
* *
*/ */
void arch_idle(void); static inline void arch_idle(void)
{
cpu_do_idle();
}
/* low level hardware reset hook -- for example, hitting the /* low level hardware reset hook -- for example, hitting the
* PSHOLD line on the PMIC to hard reset the system * PSHOLD line on the PMIC to hard reset the system
......
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