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Commit 2660b81a authored by Sujith's avatar Sujith Committed by John W. Linville
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ath9k: Remove all the useless ah_ variable prefixes 

Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent f74df6fb
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Showing with 841 additions and 845 deletions
drivers/net/wireless/ath9k/ani.c
View file @ 2660b81a
This diff is collapsed.
drivers/net/wireless/ath9k/ani.h
View file @ 2660b81a
...@@ -20,12 +20,12 @@ ...@@ -20,12 +20,12 @@
#define HAL_PROCESS_ANI 0x00000001 #define HAL_PROCESS_ANI 0x00000001
#define ATH9K_RSSI_EP_MULTIPLIER (1<<7) #define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
#define DO_ANI(ah) (((ah)->ah_procPhyErr & HAL_PROCESS_ANI)) #define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI))
#define HAL_EP_RND(x, mul) \ #define HAL_EP_RND(x, mul) \
((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
#define BEACON_RSSI(ahp) \ #define BEACON_RSSI(ahp) \
HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ HAL_EP_RND(ahp->stats.ast_nodestats.ns_avgbrssi, \
ATH9K_RSSI_EP_MULTIPLIER) ATH9K_RSSI_EP_MULTIPLIER)
#define ATH9K_ANI_OFDM_TRIG_HIGH 500 #define ATH9K_ANI_OFDM_TRIG_HIGH 500
...@@ -118,7 +118,7 @@ struct ar5416Stats { ...@@ -118,7 +118,7 @@ struct ar5416Stats {
struct ath9k_mib_stats ast_mibstats; struct ath9k_mib_stats ast_mibstats;
struct ath9k_node_stats ast_nodestats; struct ath9k_node_stats ast_nodestats;
}; };
#define ah_mibStats ah_stats.ast_mibstats #define ah_mibStats stats.ast_mibstats
void ath9k_ani_reset(struct ath_hw *ah); void ath9k_ani_reset(struct ath_hw *ah);
void ath9k_hw_ani_monitor(struct ath_hw *ah, void ath9k_hw_ani_monitor(struct ath_hw *ah,
......
drivers/net/wireless/ath9k/ath9k.h
View file @ 2660b81a
...@@ -670,8 +670,8 @@ static inline void ath_ahb_exit(void) {}; ...@@ -670,8 +670,8 @@ static inline void ath_ahb_exit(void) {};
static inline void ath9k_ps_wakeup(struct ath_softc *sc) static inline void ath9k_ps_wakeup(struct ath_softc *sc)
{ {
if (atomic_inc_return(&sc->ps_usecount) == 1) if (atomic_inc_return(&sc->ps_usecount) == 1)
if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) { if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) {
sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode; sc->sc_ah->restore_mode = sc->sc_ah->power_mode;
ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
} }
} }
...@@ -681,6 +681,6 @@ static inline void ath9k_ps_restore(struct ath_softc *sc) ...@@ -681,6 +681,6 @@ static inline void ath9k_ps_restore(struct ath_softc *sc)
if (atomic_dec_and_test(&sc->ps_usecount)) if (atomic_dec_and_test(&sc->ps_usecount))
if (sc->hw->conf.flags & IEEE80211_CONF_PS) if (sc->hw->conf.flags & IEEE80211_CONF_PS)
ath9k_hw_setpower(sc->sc_ah, ath9k_hw_setpower(sc->sc_ah,
sc->sc_ah->ah_restore_mode); sc->sc_ah->restore_mode);
} }
#endif /* ATH9K_H */ #endif /* ATH9K_H */
drivers/net/wireless/ath9k/beacon.c
View file @ 2660b81a
...@@ -27,7 +27,7 @@ static int ath_beaconq_config(struct ath_softc *sc) ...@@ -27,7 +27,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
struct ath9k_tx_queue_info qi; struct ath9k_tx_queue_info qi;
ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
/* Always burst out beacon and CAB traffic. */ /* Always burst out beacon and CAB traffic. */
qi.tqi_aifs = 1; qi.tqi_aifs = 1;
qi.tqi_cwmin = 0; qi.tqi_cwmin = 0;
...@@ -82,8 +82,8 @@ static void ath_beacon_setup(struct ath_softc *sc, ...@@ -82,8 +82,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
flags = ATH9K_TXDESC_NOACK; flags = ATH9K_TXDESC_NOACK;
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC &&
(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { (ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
ds->ds_link = bf->bf_daddr; /* self-linked */ ds->ds_link = bf->bf_daddr; /* self-linked */
flags |= ATH9K_TXDESC_VEOL; flags |= ATH9K_TXDESC_VEOL;
/* Let hardware handle antenna switching. */ /* Let hardware handle antenna switching. */
...@@ -310,8 +310,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) ...@@ -310,8 +310,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
struct ath_buf, list); struct ath_buf, list);
list_del(&avp->av_bcbuf->list); list_del(&avp->av_bcbuf->list);
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
int slot; int slot;
/* /*
* Assign the vif to a beacon xmit slot. As * Assign the vif to a beacon xmit slot. As
...@@ -631,7 +631,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -631,7 +631,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
avp = (void *)vif->drv_priv; avp = (void *)vif->drv_priv;
opmode = avp->av_opmode; opmode = avp->av_opmode;
} else { } else {
opmode = sc->sc_ah->ah_opmode; opmode = sc->sc_ah->opmode;
} }
memset(&conf, 0, sizeof(struct ath_beacon_config)); memset(&conf, 0, sizeof(struct ath_beacon_config));
...@@ -647,7 +647,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -647,7 +647,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp); nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp);
/* XXX conditionalize multi-bss support? */ /* XXX conditionalize multi-bss support? */
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
/* /*
* For multi-bss ap support beacons are either staggered * For multi-bss ap support beacons are either staggered
* evenly over N slots or burst together. For the former * evenly over N slots or burst together. For the former
...@@ -670,7 +670,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -670,7 +670,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
nexttbtt, intval, conf.beacon_interval); nexttbtt, intval, conf.beacon_interval);
/* Check for NL80211_IFTYPE_AP and sc_nostabeacons for WDS client */ /* Check for NL80211_IFTYPE_AP and sc_nostabeacons for WDS client */
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) { if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
struct ath9k_beacon_state bs; struct ath9k_beacon_state bs;
u64 tsf; u64 tsf;
u32 tsftu; u32 tsftu;
...@@ -789,7 +789,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -789,7 +789,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
ath9k_hw_set_interrupts(ah, 0); ath9k_hw_set_interrupts(ah, 0);
if (nexttbtt == intval) if (nexttbtt == intval)
intval |= ATH9K_BEACON_RESET_TSF; intval |= ATH9K_BEACON_RESET_TSF;
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
/* /*
* Pull nexttbtt forward to reflect the current * Pull nexttbtt forward to reflect the current
* TSF * TSF
...@@ -818,10 +818,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -818,10 +818,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
* deal with things. * deal with things.
*/ */
intval |= ATH9K_BEACON_ENA; intval |= ATH9K_BEACON_ENA;
if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) if (!(ah->caps.hw_caps & ATH9K_HW_CAP_VEOL))
sc->imask |= ATH9K_INT_SWBA; sc->imask |= ATH9K_INT_SWBA;
ath_beaconq_config(sc); ath_beaconq_config(sc);
} else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
/* /*
* In AP mode we enable the beacon timers and * In AP mode we enable the beacon timers and
* SWBA interrupts to prepare beacon frames. * SWBA interrupts to prepare beacon frames.
...@@ -837,8 +837,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -837,8 +837,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
* When using a self-linked beacon descriptor in * When using a self-linked beacon descriptor in
* ibss mode load it once here. * ibss mode load it once here.
*/ */
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC &&
(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) (ah->caps.hw_caps & ATH9K_HW_CAP_VEOL))
ath_beacon_start_adhoc(sc, 0); ath_beacon_start_adhoc(sc, 0);
} }
} }
......
drivers/net/wireless/ath9k/calib.c
View file @ 2660b81a
...@@ -229,13 +229,13 @@ static void ath9k_hw_reset_calibration(struct ath_hw *ah, ...@@ -229,13 +229,13 @@ static void ath9k_hw_reset_calibration(struct ath_hw *ah,
currCal->calState = CAL_RUNNING; currCal->calState = CAL_RUNNING;
for (i = 0; i < AR5416_MAX_CHAINS; i++) { for (i = 0; i < AR5416_MAX_CHAINS; i++) {
ah->ah_Meas0.sign[i] = 0; ah->meas0.sign[i] = 0;
ah->ah_Meas1.sign[i] = 0; ah->meas1.sign[i] = 0;
ah->ah_Meas2.sign[i] = 0; ah->meas2.sign[i] = 0;
ah->ah_Meas3.sign[i] = 0; ah->meas3.sign[i] = 0;
} }
ah->ah_CalSamples = 0; ah->cal_samples = 0;
} }
static void ath9k_hw_per_calibration(struct ath_hw *ah, static void ath9k_hw_per_calibration(struct ath_hw *ah,
...@@ -251,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hw *ah, ...@@ -251,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hw *ah,
AR_PHY_TIMING_CTRL4_DO_CAL)) { AR_PHY_TIMING_CTRL4_DO_CAL)) {
currCal->calData->calCollect(ah); currCal->calData->calCollect(ah);
ah->ah_CalSamples++; ah->cal_samples++;
if (ah->ah_CalSamples >= currCal->calData->calNumSamples) { if (ah->cal_samples >= currCal->calData->calNumSamples) {
int i, numChains = 0; int i, numChains = 0;
for (i = 0; i < AR5416_MAX_CHAINS; i++) { for (i = 0; i < AR5416_MAX_CHAINS; i++) {
if (rxchainmask & (1 << i)) if (rxchainmask & (1 << i))
...@@ -279,7 +279,7 @@ static bool ath9k_hw_iscal_supported(struct ath_hw *ah, ...@@ -279,7 +279,7 @@ static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
{ {
struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
switch (calType & ah->ah_suppCals) { switch (calType & ah->supp_cals) {
case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
return true; return true;
case ADC_GAIN_CAL: case ADC_GAIN_CAL:
...@@ -297,17 +297,17 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah) ...@@ -297,17 +297,17 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
int i; int i;
for (i = 0; i < AR5416_MAX_CHAINS; i++) { for (i = 0; i < AR5416_MAX_CHAINS; i++) {
ah->ah_totalPowerMeasI[i] += ah->totalPowerMeasI[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
ah->ah_totalPowerMeasQ[i] += ah->totalPowerMeasQ[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
ah->ah_totalIqCorrMeas[i] += ah->totalIqCorrMeas[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i], ah->cal_samples, i, ah->totalPowerMeasI[i],
ah->ah_totalPowerMeasQ[i], ah->totalPowerMeasQ[i],
ah->ah_totalIqCorrMeas[i]); ah->totalIqCorrMeas[i]);
} }
} }
...@@ -316,23 +316,23 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) ...@@ -316,23 +316,23 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
int i; int i;
for (i = 0; i < AR5416_MAX_CHAINS; i++) { for (i = 0; i < AR5416_MAX_CHAINS; i++) {
ah->ah_totalAdcIOddPhase[i] += ah->totalAdcIOddPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
ah->ah_totalAdcIEvenPhase[i] += ah->totalAdcIEvenPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
ah->ah_totalAdcQOddPhase[i] += ah->totalAdcQOddPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
ah->ah_totalAdcQEvenPhase[i] += ah->totalAdcQEvenPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
"oddq=0x%08x; evenq=0x%08x;\n", "oddq=0x%08x; evenq=0x%08x;\n",
ah->ah_CalSamples, i, ah->cal_samples, i,
ah->ah_totalAdcIOddPhase[i], ah->totalAdcIOddPhase[i],
ah->ah_totalAdcIEvenPhase[i], ah->totalAdcIEvenPhase[i],
ah->ah_totalAdcQOddPhase[i], ah->totalAdcQOddPhase[i],
ah->ah_totalAdcQEvenPhase[i]); ah->totalAdcQEvenPhase[i]);
} }
} }
...@@ -341,23 +341,23 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) ...@@ -341,23 +341,23 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
int i; int i;
for (i = 0; i < AR5416_MAX_CHAINS; i++) { for (i = 0; i < AR5416_MAX_CHAINS; i++) {
ah->ah_totalAdcDcOffsetIOddPhase[i] += ah->totalAdcDcOffsetIOddPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
ah->ah_totalAdcDcOffsetIEvenPhase[i] += ah->totalAdcDcOffsetIEvenPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
ah->ah_totalAdcDcOffsetQOddPhase[i] += ah->totalAdcDcOffsetQOddPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
ah->ah_totalAdcDcOffsetQEvenPhase[i] += ah->totalAdcDcOffsetQEvenPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
"oddq=0x%08x; evenq=0x%08x;\n", "oddq=0x%08x; evenq=0x%08x;\n",
ah->ah_CalSamples, i, ah->cal_samples, i,
ah->ah_totalAdcDcOffsetIOddPhase[i], ah->totalAdcDcOffsetIOddPhase[i],
ah->ah_totalAdcDcOffsetIEvenPhase[i], ah->totalAdcDcOffsetIEvenPhase[i],
ah->ah_totalAdcDcOffsetQOddPhase[i], ah->totalAdcDcOffsetQOddPhase[i],
ah->ah_totalAdcDcOffsetQEvenPhase[i]); ah->totalAdcDcOffsetQEvenPhase[i]);
} }
} }
...@@ -369,9 +369,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) ...@@ -369,9 +369,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
int iqCorrNeg, i; int iqCorrNeg, i;
for (i = 0; i < numChains; i++) { for (i = 0; i < numChains; i++) {
powerMeasI = ah->ah_totalPowerMeasI[i]; powerMeasI = ah->totalPowerMeasI[i];
powerMeasQ = ah->ah_totalPowerMeasQ[i]; powerMeasQ = ah->totalPowerMeasQ[i];
iqCorrMeas = ah->ah_totalIqCorrMeas[i]; iqCorrMeas = ah->totalIqCorrMeas[i];
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"Starting IQ Cal and Correction for Chain %d\n", "Starting IQ Cal and Correction for Chain %d\n",
...@@ -379,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) ...@@ -379,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"Orignal: Chn %diq_corr_meas = 0x%08x\n", "Orignal: Chn %diq_corr_meas = 0x%08x\n",
i, ah->ah_totalIqCorrMeas[i]); i, ah->totalIqCorrMeas[i]);
iqCorrNeg = 0; iqCorrNeg = 0;
...@@ -443,10 +443,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -443,10 +443,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
u32 qGainMismatch, iGainMismatch, val, i; u32 qGainMismatch, iGainMismatch, val, i;
for (i = 0; i < numChains; i++) { for (i = 0; i < numChains; i++) {
iOddMeasOffset = ah->ah_totalAdcIOddPhase[i]; iOddMeasOffset = ah->totalAdcIOddPhase[i];
iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i]; iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
qOddMeasOffset = ah->ah_totalAdcQOddPhase[i]; qOddMeasOffset = ah->totalAdcQOddPhase[i];
qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i]; qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"Starting ADC Gain Cal for Chain %d\n", i); "Starting ADC Gain Cal for Chain %d\n", i);
...@@ -499,15 +499,15 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -499,15 +499,15 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
u32 iOddMeasOffset, iEvenMeasOffset, val, i; u32 iOddMeasOffset, iEvenMeasOffset, val, i;
int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
const struct hal_percal_data *calData = const struct hal_percal_data *calData =
ah->ah_cal_list_curr->calData; ah->cal_list_curr->calData;
u32 numSamples = u32 numSamples =
(1 << (calData->calCountMax + 5)) * calData->calNumSamples; (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
for (i = 0; i < numChains; i++) { for (i = 0; i < numChains; i++) {
iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i]; iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i]; iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i]; qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i]; qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"Starting ADC DC Offset Cal for Chain %d\n", i); "Starting ADC DC Offset Cal for Chain %d\n", i);
...@@ -555,9 +555,9 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -555,9 +555,9 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
bool ath9k_hw_reset_calvalid(struct ath_hw *ah) bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
{ {
struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
struct hal_cal_list *currCal = ah->ah_cal_list_curr; struct hal_cal_list *currCal = ah->cal_list_curr;
if (!ah->ah_curchan) if (!ah->curchan)
return true; return true;
if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah)) if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
...@@ -580,7 +580,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) ...@@ -580,7 +580,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
"Resetting Cal %d state for channel %u\n", "Resetting Cal %d state for channel %u\n",
currCal->calData->calType, conf->channel->center_freq); currCal->calData->calType, conf->channel->center_freq);
ah->ah_curchan->CalValid &= ~currCal->calData->calType; ah->curchan->CalValid &= ~currCal->calData->calType;
currCal->calState = CAL_WAITING; currCal->calState = CAL_WAITING;
return false; return false;
...@@ -722,7 +722,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -722,7 +722,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
u8 rxchainmask, bool longcal, u8 rxchainmask, bool longcal,
bool *isCalDone) bool *isCalDone)
{ {
struct hal_cal_list *currCal = ah->ah_cal_list_curr; struct hal_cal_list *currCal = ah->cal_list_curr;
*isCalDone = true; *isCalDone = true;
...@@ -732,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -732,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
isCalDone); isCalDone);
if (*isCalDone) { if (*isCalDone) {
ah->ah_cal_list_curr = currCal = currCal->calNext; ah->cal_list_curr = currCal = currCal->calNext;
if (currCal->calState == CAL_WAITING) { if (currCal->calState == CAL_WAITING) {
*isCalDone = false; *isCalDone = false;
...@@ -743,7 +743,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -743,7 +743,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
if (longcal) { if (longcal) {
ath9k_hw_getnf(ah, chan); ath9k_hw_getnf(ah, chan);
ath9k_hw_loadnf(ah, ah->ah_curchan); ath9k_hw_loadnf(ah, ah->curchan);
ath9k_hw_start_nfcal(ah); ath9k_hw_start_nfcal(ah);
if (chan->channelFlags & CHANNEL_CW_INT) if (chan->channelFlags & CHANNEL_CW_INT)
...@@ -869,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, ...@@ -869,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
REG_READ(ah, AR_PHY_AGC_CONTROL) | REG_READ(ah, AR_PHY_AGC_CONTROL) |
AR_PHY_AGC_CONTROL_NF); AR_PHY_AGC_CONTROL_NF);
ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL; ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
INIT_CAL(&ah->ah_adcGainCalData); INIT_CAL(&ah->adcgain_caldata);
INSERT_CAL(ah, &ah->ah_adcGainCalData); INSERT_CAL(ah, &ah->adcgain_caldata);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"enabling ADC Gain Calibration.\n"); "enabling ADC Gain Calibration.\n");
} }
if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
INIT_CAL(&ah->ah_adcDcCalData); INIT_CAL(&ah->adcdc_caldata);
INSERT_CAL(ah, &ah->ah_adcDcCalData); INSERT_CAL(ah, &ah->adcdc_caldata);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"enabling ADC DC Calibration.\n"); "enabling ADC DC Calibration.\n");
} }
if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
INIT_CAL(&ah->ah_iqCalData); INIT_CAL(&ah->iq_caldata);
INSERT_CAL(ah, &ah->ah_iqCalData); INSERT_CAL(ah, &ah->iq_caldata);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"enabling IQ Calibration.\n"); "enabling IQ Calibration.\n");
} }
ah->ah_cal_list_curr = ah->ah_cal_list; ah->cal_list_curr = ah->cal_list;
if (ah->ah_cal_list_curr) if (ah->cal_list_curr)
ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr); ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
} }
chan->CalValid = 0; chan->CalValid = 0;
......
drivers/net/wireless/ath9k/calib.h
View file @ 2660b81a
...@@ -56,14 +56,14 @@ struct ar5416IniArray { ...@@ -56,14 +56,14 @@ struct ar5416IniArray {
#define INSERT_CAL(_ahp, _perCal) \ #define INSERT_CAL(_ahp, _perCal) \
do { \ do { \
if ((_ahp)->ah_cal_list_last == NULL) { \ if ((_ahp)->cal_list_last == NULL) { \
(_ahp)->ah_cal_list = \ (_ahp)->cal_list = \
(_ahp)->ah_cal_list_last = (_perCal); \ (_ahp)->cal_list_last = (_perCal); \
((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ ((_ahp)->cal_list_last)->calNext = (_perCal); \
} else { \ } else { \
((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ ((_ahp)->cal_list_last)->calNext = (_perCal); \
(_ahp)->ah_cal_list_last = (_perCal); \ (_ahp)->cal_list_last = (_perCal); \
(_perCal)->calNext = (_ahp)->ah_cal_list; \ (_perCal)->calNext = (_ahp)->cal_list; \
} \ } \
} while (0) } while (0)
......
drivers/net/wireless/ath9k/eeprom.c
View file @ 2660b81a
This diff is collapsed.
drivers/net/wireless/ath9k/eeprom.h
View file @ 2660b81a
...@@ -441,7 +441,7 @@ struct ath9k_country_entry { ...@@ -441,7 +441,7 @@ struct ath9k_country_entry {
u8 iso[3]; u8 iso[3];
}; };
enum hal_eep_map { enum ath9k_eep_map {
EEP_MAP_DEFAULT = 0x0, EEP_MAP_DEFAULT = 0x0,
EEP_MAP_4KBITS, EEP_MAP_4KBITS,
EEP_MAP_MAX EEP_MAP_MAX
......
drivers/net/wireless/ath9k/hw.c
View file @ 2660b81a
This diff is collapsed.
drivers/net/wireless/ath9k/hw.h
View file @ 2660b81a
...@@ -420,152 +420,148 @@ struct ath9k_hw_version { ...@@ -420,152 +420,148 @@ struct ath9k_hw_version {
struct ath_hw { struct ath_hw {
struct ath_softc *ah_sc; struct ath_softc *ah_sc;
struct ath9k_hw_version hw_version; struct ath9k_hw_version hw_version;
struct ath9k_ops_config ah_config; struct ath9k_ops_config config;
struct ath9k_hw_capabilities ah_caps; struct ath9k_hw_capabilities caps;
struct ath9k_regulatory regulatory; struct ath9k_regulatory regulatory;
struct ath9k_channel ah_channels[38]; struct ath9k_channel channels[38];
struct ath9k_channel *ah_curchan; struct ath9k_channel *curchan;
union { union {
struct ar5416_eeprom_def def; struct ar5416_eeprom_def def;
struct ar5416_eeprom_4k map4k; struct ar5416_eeprom_4k map4k;
} ah_eeprom; } eeprom;
const struct eeprom_ops *eep_ops; const struct eeprom_ops *eep_ops;
enum ath9k_eep_map eep_map;
bool sw_mgmt_crypto; bool sw_mgmt_crypto;
bool ah_isPciExpress; bool is_pciexpress;
u8 macaddr[ETH_ALEN]; u8 macaddr[ETH_ALEN];
u16 ah_txTrigLevel; u16 tx_trig_level;
u16 ah_rfsilent; u16 rfsilent;
u32 ah_rfkill_gpio; u32 rfkill_gpio;
u32 ah_rfkill_polarity; u32 rfkill_polarity;
u32 ah_btactive_gpio; u32 btactive_gpio;
u32 ah_wlanactive_gpio; u32 wlanactive_gpio;
u32 ah_flags; u32 ah_flags;
enum nl80211_iftype ah_opmode;
enum ath9k_power_mode ah_power_mode; enum nl80211_iftype opmode;
enum ath9k_power_mode ah_restore_mode; enum ath9k_power_mode power_mode;
enum ath9k_power_mode restore_mode;
struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
struct ar5416Stats ah_stats; struct ar5416Stats stats;
struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
int16_t ah_curchanRadIndex; int16_t curchan_rad_index;
u32 ah_maskReg; u32 mask_reg;
u32 ah_txOkInterruptMask; u32 txok_interrupt_mask;
u32 ah_txErrInterruptMask; u32 txerr_interrupt_mask;
u32 ah_txDescInterruptMask; u32 txdesc_interrupt_mask;
u32 ah_txEolInterruptMask; u32 txeol_interrupt_mask;
u32 ah_txUrnInterruptMask; u32 txurn_interrupt_mask;
bool ah_chipFullSleep; bool chip_fullsleep;
u32 ah_atimWindow; u32 atim_window;
u16 ah_antennaSwitchSwap; u16 antenna_switch_swap;
enum ath9k_ant_setting ah_diversityControl; enum ath9k_ant_setting diversity_control;
/* Calibration */ /* Calibration */
enum hal_cal_types ah_suppCals; enum hal_cal_types supp_cals;
struct hal_cal_list ah_iqCalData; struct hal_cal_list iq_caldata;
struct hal_cal_list ah_adcGainCalData; struct hal_cal_list adcgain_caldata;
struct hal_cal_list ah_adcDcCalInitData; struct hal_cal_list adcdc_calinitdata;
struct hal_cal_list ah_adcDcCalData; struct hal_cal_list adcdc_caldata;
struct hal_cal_list *ah_cal_list; struct hal_cal_list *cal_list;
struct hal_cal_list *ah_cal_list_last; struct hal_cal_list *cal_list_last;
struct hal_cal_list *ah_cal_list_curr; struct hal_cal_list *cal_list_curr;
#define ah_totalPowerMeasI ah_Meas0.unsign #define totalPowerMeasI meas0.unsign
#define ah_totalPowerMeasQ ah_Meas1.unsign #define totalPowerMeasQ meas1.unsign
#define ah_totalIqCorrMeas ah_Meas2.sign #define totalIqCorrMeas meas2.sign
#define ah_totalAdcIOddPhase ah_Meas0.unsign #define totalAdcIOddPhase meas0.unsign
#define ah_totalAdcIEvenPhase ah_Meas1.unsign #define totalAdcIEvenPhase meas1.unsign
#define ah_totalAdcQOddPhase ah_Meas2.unsign #define totalAdcQOddPhase meas2.unsign
#define ah_totalAdcQEvenPhase ah_Meas3.unsign #define totalAdcQEvenPhase meas3.unsign
#define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign #define totalAdcDcOffsetIOddPhase meas0.sign
#define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign #define totalAdcDcOffsetIEvenPhase meas1.sign
#define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign #define totalAdcDcOffsetQOddPhase meas2.sign
#define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign #define totalAdcDcOffsetQEvenPhase meas3.sign
union { union {
u32 unsign[AR5416_MAX_CHAINS]; u32 unsign[AR5416_MAX_CHAINS];
int32_t sign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS];
} ah_Meas0; } meas0;
union { union {
u32 unsign[AR5416_MAX_CHAINS]; u32 unsign[AR5416_MAX_CHAINS];
int32_t sign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS];
} ah_Meas1; } meas1;
union { union {
u32 unsign[AR5416_MAX_CHAINS]; u32 unsign[AR5416_MAX_CHAINS];
int32_t sign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS];
} ah_Meas2; } meas2;
union { union {
u32 unsign[AR5416_MAX_CHAINS]; u32 unsign[AR5416_MAX_CHAINS];
int32_t sign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS];
} ah_Meas3; } meas3;
u16 ah_CalSamples; u16 cal_samples;
u32 ah_staId1Defaults; u32 sta_id1_defaults;
u32 ah_miscMode; u32 misc_mode;
enum { enum {
AUTO_32KHZ, AUTO_32KHZ,
USE_32KHZ, USE_32KHZ,
DONT_USE_32KHZ, DONT_USE_32KHZ,
} ah_enable32kHzClock; } enable_32kHz_clock;
/* RF */ /* RF */
u32 *ah_analogBank0Data; u32 *analogBank0Data;
u32 *ah_analogBank1Data; u32 *analogBank1Data;
u32 *ah_analogBank2Data; u32 *analogBank2Data;
u32 *ah_analogBank3Data; u32 *analogBank3Data;
u32 *ah_analogBank6Data; u32 *analogBank6Data;
u32 *ah_analogBank6TPCData; u32 *analogBank6TPCData;
u32 *ah_analogBank7Data; u32 *analogBank7Data;
u32 *ah_addac5416_21; u32 *addac5416_21;
u32 *ah_bank6Temp; u32 *bank6Temp;
int16_t ah_txPowerIndexOffset; int16_t txpower_indexoffset;
u32 ah_beaconInterval; u32 beacon_interval;
u32 ah_slottime; u32 slottime;
u32 ah_acktimeout; u32 acktimeout;
u32 ah_ctstimeout; u32 ctstimeout;
u32 ah_globaltxtimeout; u32 globaltxtimeout;
u8 ah_gBeaconRate; u8 gbeacon_rate;
u32 ah_gpioSelect;
u32 ah_polarity;
u32 ah_gpioBit;
/* ANI */ /* ANI */
u32 ah_procPhyErr; u32 proc_phyerr;
bool ah_hasHwPhyCounters; bool has_hw_phycounters;
u32 ah_aniPeriod; u32 aniperiod;
struct ar5416AniState *ah_curani; struct ar5416AniState *curani;
struct ar5416AniState ah_ani[255]; struct ar5416AniState ani[255];
int ah_totalSizeDesired[5]; int totalSizeDesired[5];
int ah_coarseHigh[5]; int coarse_high[5];
int ah_coarseLow[5]; int coarse_low[5];
int ah_firpwr[5]; int firpwr[5];
enum ath9k_ani_cmd ah_ani_function; enum ath9k_ani_cmd ani_function;
u32 ah_intrTxqs; u32 intr_txqs;
bool ah_intrMitigation; bool intr_mitigation;
enum ath9k_ht_extprotspacing ah_extprotspacing; enum ath9k_ht_extprotspacing extprotspacing;
u8 ah_txchainmask; u8 txchainmask;
u8 ah_rxchainmask; u8 rxchainmask;
struct ar5416IniArray ah_iniModes; struct ar5416IniArray iniModes;
struct ar5416IniArray ah_iniCommon; struct ar5416IniArray iniCommon;
struct ar5416IniArray ah_iniBank0; struct ar5416IniArray iniBank0;
struct ar5416IniArray ah_iniBB_RfGain; struct ar5416IniArray iniBB_RfGain;
struct ar5416IniArray ah_iniBank1; struct ar5416IniArray iniBank1;
struct ar5416IniArray ah_iniBank2; struct ar5416IniArray iniBank2;
struct ar5416IniArray ah_iniBank3; struct ar5416IniArray iniBank3;
struct ar5416IniArray ah_iniBank6; struct ar5416IniArray iniBank6;
struct ar5416IniArray ah_iniBank6TPC; struct ar5416IniArray iniBank6TPC;
struct ar5416IniArray ah_iniBank7; struct ar5416IniArray iniBank7;
struct ar5416IniArray ah_iniAddac; struct ar5416IniArray iniAddac;
struct ar5416IniArray ah_iniPcieSerdes; struct ar5416IniArray iniPcieSerdes;
struct ar5416IniArray ah_iniModesAdditional; struct ar5416IniArray iniModesAdditional;
struct ar5416IniArray ah_iniModesRxGain; struct ar5416IniArray iniModesRxGain;
struct ar5416IniArray ah_iniModesTxGain; struct ar5416IniArray iniModesTxGain;
/* To indicate EEPROM mapping used */
enum hal_eep_map ah_eep_map;
}; };
/* Attach, Detach, Reset */ /* Attach, Detach, Reset */
......
drivers/net/wireless/ath9k/mac.c
View file @ 2660b81a
...@@ -21,18 +21,18 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, ...@@ -21,18 +21,18 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
{ {
DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
"tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
ah->ah_txOkInterruptMask, ah->ah_txErrInterruptMask, ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
ah->ah_txDescInterruptMask, ah->ah_txEolInterruptMask, ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
ah->ah_txUrnInterruptMask); ah->txurn_interrupt_mask);
REG_WRITE(ah, AR_IMR_S0, REG_WRITE(ah, AR_IMR_S0,
SM(ah->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
| SM(ah->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
REG_WRITE(ah, AR_IMR_S1, REG_WRITE(ah, AR_IMR_S1,
SM(ah->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
| SM(ah->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
REG_RMW_FIELD(ah, AR_IMR_S2, REG_RMW_FIELD(ah, AR_IMR_S2,
AR_IMR_S2_QCU_TXURN, ah->ah_txUrnInterruptMask); AR_IMR_S2_QCU_TXURN, ah->txurn_interrupt_mask);
} }
u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
...@@ -75,10 +75,10 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) ...@@ -75,10 +75,10 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
u32 txcfg, curLevel, newLevel; u32 txcfg, curLevel, newLevel;
enum ath9k_int omask; enum ath9k_int omask;
if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) if (ah->tx_trig_level >= MAX_TX_FIFO_THRESHOLD)
return false; return false;
omask = ath9k_hw_set_interrupts(ah, ah->ah_maskReg & ~ATH9K_INT_GLOBAL); omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL);
txcfg = REG_READ(ah, AR_TXCFG); txcfg = REG_READ(ah, AR_TXCFG);
curLevel = MS(txcfg, AR_FTRIG); curLevel = MS(txcfg, AR_FTRIG);
...@@ -94,7 +94,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) ...@@ -94,7 +94,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
ath9k_hw_set_interrupts(ah, omask); ath9k_hw_set_interrupts(ah, omask);
ah->ah_txTrigLevel = newLevel; ah->tx_trig_level = newLevel;
return newLevel != curLevel; return newLevel != curLevel;
} }
...@@ -104,7 +104,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) ...@@ -104,7 +104,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
#define ATH9K_TIME_QUANTUM 100 /* usec */ #define ATH9K_TIME_QUANTUM 100 /* usec */
struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
u32 tsfLow, j, wait; u32 tsfLow, j, wait;
u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
...@@ -114,7 +114,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) ...@@ -114,7 +114,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
return false; return false;
} }
qi = &ah->ah_txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
return false; return false;
...@@ -296,7 +296,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, ...@@ -296,7 +296,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
{ {
struct ar5416_desc *ads = AR5416DESC(ds); struct ar5416_desc *ads = AR5416DESC(ds);
txPower += ah->ah_txPowerIndexOffset; txPower += ah->txpower_indexoffset;
if (txPower > 63) if (txPower > 63)
txPower = 63; txPower = 63;
...@@ -442,15 +442,15 @@ void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, ...@@ -442,15 +442,15 @@ void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs) void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
{ {
*txqs &= ah->ah_intrTxqs; *txqs &= ah->intr_txqs;
ah->ah_intrTxqs &= ~(*txqs); ah->intr_txqs &= ~(*txqs);
} }
bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
const struct ath9k_tx_queue_info *qinfo) const struct ath9k_tx_queue_info *qinfo)
{ {
u32 cw; u32 cw;
struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
...@@ -458,7 +458,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, ...@@ -458,7 +458,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
return false; return false;
} }
qi = &ah->ah_txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
return false; return false;
...@@ -517,7 +517,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, ...@@ -517,7 +517,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
struct ath9k_tx_queue_info *qinfo) struct ath9k_tx_queue_info *qinfo)
{ {
struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
...@@ -525,7 +525,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, ...@@ -525,7 +525,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
return false; return false;
} }
qi = &ah->ah_txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
return false; return false;
...@@ -553,7 +553,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, ...@@ -553,7 +553,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
const struct ath9k_tx_queue_info *qinfo) const struct ath9k_tx_queue_info *qinfo)
{ {
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
int q; int q;
switch (type) { switch (type) {
...@@ -571,7 +571,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, ...@@ -571,7 +571,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
break; break;
case ATH9K_TX_QUEUE_DATA: case ATH9K_TX_QUEUE_DATA:
for (q = 0; q < pCap->total_queues; q++) for (q = 0; q < pCap->total_queues; q++)
if (ah->ah_txq[q].tqi_type == if (ah->txq[q].tqi_type ==
ATH9K_TX_QUEUE_INACTIVE) ATH9K_TX_QUEUE_INACTIVE)
break; break;
if (q == pCap->total_queues) { if (q == pCap->total_queues) {
...@@ -587,7 +587,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, ...@@ -587,7 +587,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
qi = &ah->ah_txq[q]; qi = &ah->txq[q];
if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
"tx queue %u already active\n", q); "tx queue %u already active\n", q);
...@@ -616,14 +616,14 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, ...@@ -616,14 +616,14 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
{ {
struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
return false; return false;
} }
qi = &ah->ah_txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
return false; return false;
...@@ -632,11 +632,11 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) ...@@ -632,11 +632,11 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q);
qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
ah->ah_txOkInterruptMask &= ~(1 << q); ah->txok_interrupt_mask &= ~(1 << q);
ah->ah_txErrInterruptMask &= ~(1 << q); ah->txerr_interrupt_mask &= ~(1 << q);
ah->ah_txDescInterruptMask &= ~(1 << q); ah->txdesc_interrupt_mask &= ~(1 << q);
ah->ah_txEolInterruptMask &= ~(1 << q); ah->txeol_interrupt_mask &= ~(1 << q);
ah->ah_txUrnInterruptMask &= ~(1 << q); ah->txurn_interrupt_mask &= ~(1 << q);
ath9k_hw_set_txq_interrupts(ah, qi); ath9k_hw_set_txq_interrupts(ah, qi);
return true; return true;
...@@ -644,8 +644,8 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) ...@@ -644,8 +644,8 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
{ {
struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_channel *chan = ah->ah_curchan; struct ath9k_channel *chan = ah->curchan;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
u32 cwMin, chanCwMin, value; u32 cwMin, chanCwMin, value;
...@@ -654,7 +654,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) ...@@ -654,7 +654,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
return false; return false;
} }
qi = &ah->ah_txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
return true; return true;
...@@ -742,9 +742,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) ...@@ -742,9 +742,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
| AR_Q_MISC_CBR_INCR_DIS1 | AR_Q_MISC_CBR_INCR_DIS1
| AR_Q_MISC_CBR_INCR_DIS0); | AR_Q_MISC_CBR_INCR_DIS0);
value = (qi->tqi_readyTime - value = (qi->tqi_readyTime -
(ah->ah_config.sw_beacon_response_time - (ah->config.sw_beacon_response_time -
ah->ah_config.dma_beacon_response_time) - ah->config.dma_beacon_response_time) -
ah->ah_config.additional_swba_backoff) * 1024; ah->config.additional_swba_backoff) * 1024;
REG_WRITE(ah, AR_QRDYTIMECFG(q), REG_WRITE(ah, AR_QRDYTIMECFG(q),
value | AR_Q_RDYTIMECFG_EN); value | AR_Q_RDYTIMECFG_EN);
REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
...@@ -772,25 +772,25 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) ...@@ -772,25 +772,25 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
} }
if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
ah->ah_txOkInterruptMask |= 1 << q; ah->txok_interrupt_mask |= 1 << q;
else else
ah->ah_txOkInterruptMask &= ~(1 << q); ah->txok_interrupt_mask &= ~(1 << q);
if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
ah->ah_txErrInterruptMask |= 1 << q; ah->txerr_interrupt_mask |= 1 << q;
else else
ah->ah_txErrInterruptMask &= ~(1 << q); ah->txerr_interrupt_mask &= ~(1 << q);
if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
ah->ah_txDescInterruptMask |= 1 << q; ah->txdesc_interrupt_mask |= 1 << q;
else else
ah->ah_txDescInterruptMask &= ~(1 << q); ah->txdesc_interrupt_mask &= ~(1 << q);
if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
ah->ah_txEolInterruptMask |= 1 << q; ah->txeol_interrupt_mask |= 1 << q;
else else
ah->ah_txEolInterruptMask &= ~(1 << q); ah->txeol_interrupt_mask &= ~(1 << q);
if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
ah->ah_txUrnInterruptMask |= 1 << q; ah->txurn_interrupt_mask |= 1 << q;
else else
ah->ah_txUrnInterruptMask &= ~(1 << q); ah->txurn_interrupt_mask &= ~(1 << q);
ath9k_hw_set_txq_interrupts(ah, qi); ath9k_hw_set_txq_interrupts(ah, qi);
return true; return true;
...@@ -865,7 +865,7 @@ bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, ...@@ -865,7 +865,7 @@ bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
u32 size, u32 flags) u32 size, u32 flags)
{ {
struct ar5416_desc *ads = AR5416DESC(ds); struct ar5416_desc *ads = AR5416DESC(ds);
struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
ads->ds_ctl1 = size & AR_BufLen; ads->ds_ctl1 = size & AR_BufLen;
if (flags & ATH9K_RXDESC_INTREQ) if (flags & ATH9K_RXDESC_INTREQ)
......
drivers/net/wireless/ath9k/main.c
View file @ 2660b81a
This diff is collapsed.
drivers/net/wireless/ath9k/pci.c
View file @ 2660b81a
...@@ -228,7 +228,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) ...@@ -228,7 +228,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
#endif #endif
...@@ -269,7 +269,7 @@ static int ath_pci_resume(struct pci_dev *pdev) ...@@ -269,7 +269,7 @@ static int ath_pci_resume(struct pci_dev *pdev)
* check the h/w rfkill state on resume * check the h/w rfkill state on resume
* and start the rfkill poll timer * and start the rfkill poll timer
*/ */
if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
queue_delayed_work(sc->hw->workqueue, queue_delayed_work(sc->hw->workqueue,
&sc->rf_kill.rfkill_poll, 0); &sc->rf_kill.rfkill_poll, 0);
#endif #endif
......
drivers/net/wireless/ath9k/phy.c
View file @ 2660b81a
...@@ -20,7 +20,7 @@ void ...@@ -20,7 +20,7 @@ void
ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
int regWrites) int regWrites)
{ {
REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites); REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
} }
bool bool
...@@ -90,8 +90,8 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -90,8 +90,8 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
REG_WRITE(ah, AR_PHY(0x37), reg32); REG_WRITE(ah, AR_PHY(0x37), reg32);
ah->ah_curchan = chan; ah->curchan = chan;
ah->ah_curchanRadIndex = -1; ah->curchan_rad_index = -1;
return true; return true;
} }
...@@ -160,8 +160,8 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah, ...@@ -160,8 +160,8 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
ah->ah_curchan = chan; ah->curchan = chan;
ah->ah_curchanRadIndex = -1; ah->curchan_rad_index = -1;
return true; return true;
} }
...@@ -207,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -207,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1); RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1); RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3, RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
modesIndex); modesIndex);
{ {
int i; int i;
for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) { for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
ah->ah_analogBank6Data[i] = ah->analogBank6Data[i] =
INI_RA(&ah->ah_iniBank6TPC, i, modesIndex); INI_RA(&ah->iniBank6TPC, i, modesIndex);
} }
} }
...@@ -227,33 +227,33 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -227,33 +227,33 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
if (IS_CHAN_2GHZ(chan)) { if (IS_CHAN_2GHZ(chan)) {
ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
ob2GHz, 3, 197, 0); ob2GHz, 3, 197, 0);
ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
db2GHz, 3, 194, 0); db2GHz, 3, 194, 0);
} else { } else {
ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
ob5GHz, 3, 203, 0); ob5GHz, 3, 203, 0);
ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
db5GHz, 3, 200, 0); db5GHz, 3, 200, 0);
} }
} }
RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1); RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data, REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
regWrites); regWrites);
REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data, REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
regWrites); regWrites);
REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data, REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
regWrites); regWrites);
REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data, REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
regWrites); regWrites);
REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data, REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
regWrites); regWrites);
REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data, REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
regWrites); regWrites);
return true; return true;
...@@ -262,99 +262,99 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -262,99 +262,99 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
void void
ath9k_hw_rfdetach(struct ath_hw *ah) ath9k_hw_rfdetach(struct ath_hw *ah)
{ {
if (ah->ah_analogBank0Data != NULL) { if (ah->analogBank0Data != NULL) {
kfree(ah->ah_analogBank0Data); kfree(ah->analogBank0Data);
ah->ah_analogBank0Data = NULL; ah->analogBank0Data = NULL;
} }
if (ah->ah_analogBank1Data != NULL) { if (ah->analogBank1Data != NULL) {
kfree(ah->ah_analogBank1Data); kfree(ah->analogBank1Data);
ah->ah_analogBank1Data = NULL; ah->analogBank1Data = NULL;
} }
if (ah->ah_analogBank2Data != NULL) { if (ah->analogBank2Data != NULL) {
kfree(ah->ah_analogBank2Data); kfree(ah->analogBank2Data);
ah->ah_analogBank2Data = NULL; ah->analogBank2Data = NULL;
} }
if (ah->ah_analogBank3Data != NULL) { if (ah->analogBank3Data != NULL) {
kfree(ah->ah_analogBank3Data); kfree(ah->analogBank3Data);
ah->ah_analogBank3Data = NULL; ah->analogBank3Data = NULL;
} }
if (ah->ah_analogBank6Data != NULL) { if (ah->analogBank6Data != NULL) {
kfree(ah->ah_analogBank6Data); kfree(ah->analogBank6Data);
ah->ah_analogBank6Data = NULL; ah->analogBank6Data = NULL;
} }
if (ah->ah_analogBank6TPCData != NULL) { if (ah->analogBank6TPCData != NULL) {
kfree(ah->ah_analogBank6TPCData); kfree(ah->analogBank6TPCData);
ah->ah_analogBank6TPCData = NULL; ah->analogBank6TPCData = NULL;
} }
if (ah->ah_analogBank7Data != NULL) { if (ah->analogBank7Data != NULL) {
kfree(ah->ah_analogBank7Data); kfree(ah->analogBank7Data);
ah->ah_analogBank7Data = NULL; ah->analogBank7Data = NULL;
} }
if (ah->ah_addac5416_21 != NULL) { if (ah->addac5416_21 != NULL) {
kfree(ah->ah_addac5416_21); kfree(ah->addac5416_21);
ah->ah_addac5416_21 = NULL; ah->addac5416_21 = NULL;
} }
if (ah->ah_bank6Temp != NULL) { if (ah->bank6Temp != NULL) {
kfree(ah->ah_bank6Temp); kfree(ah->bank6Temp);
ah->ah_bank6Temp = NULL; ah->bank6Temp = NULL;
} }
} }
bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
{ {
if (!AR_SREV_9280_10_OR_LATER(ah)) { if (!AR_SREV_9280_10_OR_LATER(ah)) {
ah->ah_analogBank0Data = ah->analogBank0Data =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniBank0.ia_rows), GFP_KERNEL); ah->iniBank0.ia_rows), GFP_KERNEL);
ah->ah_analogBank1Data = ah->analogBank1Data =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniBank1.ia_rows), GFP_KERNEL); ah->iniBank1.ia_rows), GFP_KERNEL);
ah->ah_analogBank2Data = ah->analogBank2Data =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniBank2.ia_rows), GFP_KERNEL); ah->iniBank2.ia_rows), GFP_KERNEL);
ah->ah_analogBank3Data = ah->analogBank3Data =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniBank3.ia_rows), GFP_KERNEL); ah->iniBank3.ia_rows), GFP_KERNEL);
ah->ah_analogBank6Data = ah->analogBank6Data =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniBank6.ia_rows), GFP_KERNEL); ah->iniBank6.ia_rows), GFP_KERNEL);
ah->ah_analogBank6TPCData = ah->analogBank6TPCData =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL); ah->iniBank6TPC.ia_rows), GFP_KERNEL);
ah->ah_analogBank7Data = ah->analogBank7Data =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniBank7.ia_rows), GFP_KERNEL); ah->iniBank7.ia_rows), GFP_KERNEL);
if (ah->ah_analogBank0Data == NULL if (ah->analogBank0Data == NULL
|| ah->ah_analogBank1Data == NULL || ah->analogBank1Data == NULL
|| ah->ah_analogBank2Data == NULL || ah->analogBank2Data == NULL
|| ah->ah_analogBank3Data == NULL || ah->analogBank3Data == NULL
|| ah->ah_analogBank6Data == NULL || ah->analogBank6Data == NULL
|| ah->ah_analogBank6TPCData == NULL || ah->analogBank6TPCData == NULL
|| ah->ah_analogBank7Data == NULL) { || ah->analogBank7Data == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Cannot allocate RF banks\n"); "Cannot allocate RF banks\n");
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
} }
ah->ah_addac5416_21 = ah->addac5416_21 =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniAddac.ia_rows * ah->iniAddac.ia_rows *
ah->ah_iniAddac.ia_columns), GFP_KERNEL); ah->iniAddac.ia_columns), GFP_KERNEL);
if (ah->ah_addac5416_21 == NULL) { if (ah->addac5416_21 == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Cannot allocate ah_addac5416_21\n"); "Cannot allocate addac5416_21\n");
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
} }
ah->ah_bank6Temp = ah->bank6Temp =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->ah_iniBank6.ia_rows), GFP_KERNEL); ah->iniBank6.ia_rows), GFP_KERNEL);
if (ah->ah_bank6Temp == NULL) { if (ah->bank6Temp == NULL) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Cannot allocate ah_bank6Temp\n"); "Cannot allocate bank6Temp\n");
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
} }
...@@ -368,19 +368,19 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -368,19 +368,19 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
{ {
int i, regWrites = 0; int i, regWrites = 0;
u32 bank6SelMask; u32 bank6SelMask;
u32 *bank6Temp = ah->ah_bank6Temp; u32 *bank6Temp = ah->bank6Temp;
switch (ah->ah_diversityControl) { switch (ah->diversity_control) {
case ATH9K_ANT_FIXED_A: case ATH9K_ANT_FIXED_A:
bank6SelMask = bank6SelMask =
(ah-> (ah->
ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
REDUCE_CHAIN_1; REDUCE_CHAIN_1;
break; break;
case ATH9K_ANT_FIXED_B: case ATH9K_ANT_FIXED_B:
bank6SelMask = bank6SelMask =
(ah-> (ah->
ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
REDUCE_CHAIN_0; REDUCE_CHAIN_0;
break; break;
case ATH9K_ANT_VARIABLE: case ATH9K_ANT_VARIABLE:
...@@ -391,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -391,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
break; break;
} }
for (i = 0; i < ah->ah_iniBank6.ia_rows; i++) for (i = 0; i < ah->iniBank6.ia_rows; i++)
bank6Temp[i] = ah->ah_analogBank6Data[i]; bank6Temp[i] = ah->analogBank6Data[i];
REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
...@@ -406,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -406,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites); REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
#ifdef ALTER_SWITCH #ifdef ALTER_SWITCH
......
drivers/net/wireless/ath9k/phy.h
View file @ 2660b81a
...@@ -533,7 +533,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, ...@@ -533,7 +533,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
#define ATH9K_KEY_XOR 0xaa #define ATH9K_KEY_XOR 0xaa
#define ATH9K_IS_MIC_ENABLED(ah) \ #define ATH9K_IS_MIC_ENABLED(ah) \
((ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) ((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
#define ANTSWAP_AB 0x0001 #define ANTSWAP_AB 0x0001
#define REDUCE_CHAIN_0 0x00000050 #define REDUCE_CHAIN_0 0x00000050
......
drivers/net/wireless/ath9k/rc.c
View file @ 2660b81a
...@@ -1394,13 +1394,13 @@ static void ath_rc_init(struct ath_softc *sc, ...@@ -1394,13 +1394,13 @@ static void ath_rc_init(struct ath_softc *sc,
u8 i, j, k, hi = 0, hthi = 0; u8 i, j, k, hi = 0, hthi = 0;
/* FIXME: Adhoc */ /* FIXME: Adhoc */
if ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) || if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) ||
(sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)) { (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) {
bool is_cw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40; bool is_cw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
rate_table = ath_choose_rate_table(sc, sband->band, rate_table = ath_choose_rate_table(sc, sband->band,
sta->ht_cap.ht_supported, sta->ht_cap.ht_supported,
is_cw_40); is_cw_40);
} else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
/* cur_rate_table would be set on init through config() */ /* cur_rate_table would be set on init through config() */
rate_table = sc->cur_rate_table; rate_table = sc->cur_rate_table;
} }
...@@ -1412,7 +1412,7 @@ static void ath_rc_init(struct ath_softc *sc, ...@@ -1412,7 +1412,7 @@ static void ath_rc_init(struct ath_softc *sc,
if (sta->ht_cap.ht_supported) { if (sta->ht_cap.ht_supported) {
ath_rc_priv->ht_cap = WLAN_RC_HT_FLAG; ath_rc_priv->ht_cap = WLAN_RC_HT_FLAG;
if (sc->sc_ah->ah_caps.tx_chainmask != 1) if (sc->sc_ah->caps.tx_chainmask != 1)
ath_rc_priv->ht_cap |= WLAN_RC_DS_FLAG; ath_rc_priv->ht_cap |= WLAN_RC_DS_FLAG;
if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
ath_rc_priv->ht_cap |= WLAN_RC_40_FLAG; ath_rc_priv->ht_cap |= WLAN_RC_40_FLAG;
...@@ -1519,7 +1519,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband, ...@@ -1519,7 +1519,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
*/ */
if (tx_info_priv->tx.ts_flags & if (tx_info_priv->tx.ts_flags &
(ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) && (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) &&
((sc->sc_ah->ah_txTrigLevel) >= ath_rc_priv->tx_triglevel_max)) { ((sc->sc_ah->tx_trig_level) >= ath_rc_priv->tx_triglevel_max)) {
tx_status = 1; tx_status = 1;
is_underrun = 1; is_underrun = 1;
} }
...@@ -1628,7 +1628,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp ...@@ -1628,7 +1628,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
} }
rate_priv->rssi_down_time = jiffies_to_msecs(jiffies); rate_priv->rssi_down_time = jiffies_to_msecs(jiffies);
rate_priv->tx_triglevel_max = sc->sc_ah->ah_caps.tx_triglevel_max; rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max;
return rate_priv; return rate_priv;
} }
......
drivers/net/wireless/ath9k/recv.c
View file @ 2660b81a
...@@ -135,7 +135,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, ...@@ -135,7 +135,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
* discard the frame. Enable this if you want to see * discard the frame. Enable this if you want to see
* error frames in Monitor mode. * error frames in Monitor mode.
*/ */
if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_MONITOR) if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR)
goto rx_next; goto rx_next;
} else if (ds->ds_rxstat.rs_status != 0) { } else if (ds->ds_rxstat.rs_status != 0) {
if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
...@@ -161,7 +161,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, ...@@ -161,7 +161,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
* decryption and MIC failures. For monitor mode, * decryption and MIC failures. For monitor mode,
* we also ignore the CRC error. * we also ignore the CRC error.
*/ */
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR) { if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) {
if (ds->ds_rxstat.rs_status & if (ds->ds_rxstat.rs_status &
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
ATH9K_RXERR_CRC)) ATH9K_RXERR_CRC))
...@@ -241,7 +241,7 @@ static void ath_opmode_init(struct ath_softc *sc) ...@@ -241,7 +241,7 @@ static void ath_opmode_init(struct ath_softc *sc)
ath9k_hw_setrxfilter(ah, rfilt); ath9k_hw_setrxfilter(ah, rfilt);
/* configure bssid mask */ /* configure bssid mask */
if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ath9k_hw_setbssidmask(sc); ath9k_hw_setbssidmask(sc);
/* configure operational mode */ /* configure operational mode */
...@@ -360,13 +360,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc) ...@@ -360,13 +360,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
| ATH9K_RX_FILTER_MCAST; | ATH9K_RX_FILTER_MCAST;
/* If not a STA, enable processing of Probe Requests */ /* If not a STA, enable processing of Probe Requests */
if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_STATION) if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
rfilt |= ATH9K_RX_FILTER_PROBEREQ; rfilt |= ATH9K_RX_FILTER_PROBEREQ;
/* Can't set HOSTAP into promiscous mode */ /* Can't set HOSTAP into promiscous mode */
if (((sc->sc_ah->ah_opmode != NL80211_IFTYPE_AP) && if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
(sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
(sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR)) { (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) {
rfilt |= ATH9K_RX_FILTER_PROM; rfilt |= ATH9K_RX_FILTER_PROM;
/* ??? To prevent from sending ACK */ /* ??? To prevent from sending ACK */
rfilt &= ~ATH9K_RX_FILTER_UCAST; rfilt &= ~ATH9K_RX_FILTER_UCAST;
...@@ -375,13 +375,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc) ...@@ -375,13 +375,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
if (sc->rx.rxfilter & FIF_CONTROL) if (sc->rx.rxfilter & FIF_CONTROL)
rfilt |= ATH9K_RX_FILTER_CONTROL; rfilt |= ATH9K_RX_FILTER_CONTROL;
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION || if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION ||
sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
rfilt |= ATH9K_RX_FILTER_BEACON; rfilt |= ATH9K_RX_FILTER_BEACON;
/* If in HOSTAP mode, want to enable reception of PSPOLL frames /* If in HOSTAP mode, want to enable reception of PSPOLL frames
& beacon frames */ & beacon frames */
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) if (sc->sc_ah->opmode == NL80211_IFTYPE_AP)
rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL);
return rfilt; return rfilt;
......
drivers/net/wireless/ath9k/xmit.c
View file @ 2660b81a
...@@ -308,7 +308,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, ...@@ -308,7 +308,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
* when perform internal reset in this routine. * when perform internal reset in this routine.
* Only enable reset in STA mode for now. * Only enable reset in STA mode for now.
*/ */
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
needreset = 1; needreset = 1;
} }
} }
...@@ -1072,7 +1072,7 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) ...@@ -1072,7 +1072,7 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
spin_lock_bh(&sc->sc_resetlock); spin_lock_bh(&sc->sc_resetlock);
r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, true); r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
if (r) if (r)
DPRINTF(sc, ATH_DBG_FATAL, DPRINTF(sc, ATH_DBG_FATAL,
"Unable to reset hardware; reset status %u\n", "Unable to reset hardware; reset status %u\n",
...@@ -1477,7 +1477,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) ...@@ -1477,7 +1477,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
} }
/* For AR5416 - RTS cannot be followed by a frame larger than 8K */ /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->ah_caps.rts_aggr_limit)) if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
flags &= ~(ATH9K_TXDESC_RTSENA); flags &= ~(ATH9K_TXDESC_RTSENA);
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
......
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