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Commit 273b9465 authored by Paul Walmsley's avatar Paul Walmsley
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omap_hwmod: share identical omap_hwmod_class, omap_hwmod_class_sysconfig arrays 

To reduce kernel source file data duplication, share struct
omap_hwmod_class and omap_hwmod_class_sysconfig arrays across OMAP2xxx
and 3xxx hwmod data files.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent d826ebfa
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Showing with 364 additions and 643 deletions
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View file @ 273b9465
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arch/arm/mach-omap2/omap_hwmod_2430_data.c
View file @ 273b9465
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arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
View file @ 273b9465
......@@ -16,6 +16,164 @@
#include "omap_hwmod_common_data.h"
/* UART */
static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
.rev_offs = 0x50,
.sysc_offs = 0x54,
.syss_offs = 0x58,
.sysc_flags = (SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_uart_class = {
.name = "uart",
.sysc = &omap2_uart_sysc,
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2_dss_sysc,
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2_dispc_sysc,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2_rfbi_sysc,
};
/*
* 'venc' class
* video encoder
*/
struct omap_hwmod_class omap2_venc_hwmod_class = {
.name = "venc",
};
/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
{ .name = "rx", .dma_req = 18 },
{ .name = "tx", .dma_req = 17 },
{ .dma_req = -1 }
};
/* Other IP block data */
/*
* omap_hwmod class data
......@@ -162,73 +320,3 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
{ .irq = -1 }
};
/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
{ .name = "rx", .dma_req = 18 },
{ .name = "tx", .dma_req = 17 },
{ .dma_req = -1 }
};
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
View file @ 273b9465
......@@ -11,10 +11,13 @@
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <plat/dma.h>
#include <plat/dmtimer.h>
#include <plat/mcspi.h>
#include <mach/irqs.h>
#include "omap_hwmod_common_data.h"
#include "wd_timer.h"
struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
{ .irq = 48, },
......@@ -25,3 +28,123 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
{ .dma_req = -1 }
};
/* OMAP2xxx Timer Common */
static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
.name = "timer",
.sysc = &omap2xxx_timer_sysc,
.rev = OMAP_TIMER_IP_VERSION_1,
};
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap2xxx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable
};
/*
* 'gpio' class
* general purpose io module
*/
static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap2xxx_gpio_sysc,
.rev = 0,
};
/* system dma */
static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
.name = "dma",
.sysc = &omap2xxx_dma_sysc,
};
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors
* using a queued mailbox-interrupt mechanism.
*/
static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
.rev_offs = 0x000,
.sysc_offs = 0x010,
.syss_offs = 0x014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &omap2xxx_mailbox_sysc,
};
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_mcspi_class = {
.name = "mcspi",
.sysc = &omap2xxx_mcspi_sysc,
.rev = OMAP2_MCSPI_REV,
};
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View file @ 273b9465
......@@ -1190,24 +1190,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
.flags = HWMOD_SWSUP_SIDLE,
};
/* UART common */
static struct omap_hwmod_class_sysconfig uart_sysc = {
.rev_offs = 0x50,
.sysc_offs = 0x54,
.syss_offs = 0x58,
.sysc_flags = (SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class uart_class = {
.name = "uart",
.sysc = &uart_sysc,
};
/* UART1 */
static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
......@@ -1230,7 +1212,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
},
.slaves = omap3xxx_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
.class = &uart_class,
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
......@@ -1256,7 +1238,7 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
},
.slaves = omap3xxx_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
.class = &uart_class,
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
......@@ -1282,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
},
.slaves = omap3xxx_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
.class = &uart_class,
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
......@@ -1319,7 +1301,7 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
},
.slaves = omap3xxx_uart4_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
.class = &uart_class,
.class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
......@@ -1328,24 +1310,6 @@ static struct omap_hwmod_class i2c_class = {
.sysc = &i2c_sysc,
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
.name = "dss",
.sysc = &omap3xxx_dss_sysc,
};
static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
{ .name = "dsi1", .dma_req = 74 },
......@@ -1406,7 +1370,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
static struct omap_hwmod omap3430es1_dss_core_hwmod = {
.name = "dss_core",
.class = &omap3xxx_dss_hwmod_class,
.class = &omap2_dss_hwmod_class,
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.sdma_reqs = omap3xxx_dss_sdma_chs,
.prcm = {
......@@ -1430,7 +1394,7 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
static struct omap_hwmod omap3xxx_dss_core_hwmod = {
.name = "dss_core",
.class = &omap3xxx_dss_hwmod_class,
.class = &omap2_dss_hwmod_class,
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.sdma_reqs = omap3xxx_dss_sdma_chs,
.prcm = {
......@@ -1453,28 +1417,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap3xxx_dispc_sysc,
};
/* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
.master = &omap3xxx_l4_core_hwmod,
......@@ -1498,7 +1440,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap3xxx_dispc_hwmod_class,
.class = &omap2_dispc_hwmod_class,
.mpu_irqs = omap2_dispc_irqs,
.main_clk = "dss1_alwon_fck",
.prcm = {
......@@ -1580,26 +1522,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap3xxx_rfbi_sysc,
};
/* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
.master = &omap3xxx_l4_core_hwmod,
......@@ -1623,7 +1545,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap3xxx_rfbi_hwmod_class,
.class = &omap2_rfbi_hwmod_class,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
......@@ -1640,15 +1562,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
/*
* 'venc' class
* video encoder
*/
static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
.name = "venc",
};
/* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
.master = &omap3xxx_l4_core_hwmod,
......@@ -1673,7 +1586,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
.name = "dss_venc",
.class = &omap3xxx_venc_hwmod_class,
.class = &omap2_venc_hwmod_class,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
......
arch/arm/mach-omap2/omap_hwmod_common_data.h
View file @ 273b9465
......@@ -98,6 +98,17 @@ extern struct omap_hwmod_class l3_hwmod_class;
extern struct omap_hwmod_class l4_hwmod_class;
extern struct omap_hwmod_class mpu_hwmod_class;
extern struct omap_hwmod_class iva_hwmod_class;
extern struct omap_hwmod_class omap2_uart_class;
extern struct omap_hwmod_class omap2_dss_hwmod_class;
extern struct omap_hwmod_class omap2_dispc_hwmod_class;
extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
extern struct omap_hwmod_class omap2_venc_hwmod_class;
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mcspi_class;
#endif
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