Commit 2789c08f authored by Andreas Westin's avatar Andreas Westin Committed by Herbert Xu

crypto: ux500 - Add driver for CRYP hardware

This adds a driver for the ST-Ericsson ux500 crypto hardware
module. It supports AES, DES and 3DES, the driver implements
support for AES-ECB,CBC and CTR.
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarAndreas Westin <andreas.westin@stericsson.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 028fdd87
/*
* Copyright (C) ST-Ericsson SA 2011
*
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYPTO_UX500_H
#include <linux/dmaengine.h>
#include <plat/ste_dma40.h>
struct cryp_platform_data {
struct stedma40_chan_cfg mem_to_engine;
struct stedma40_chan_cfg engine_to_mem;
};
#endif
......@@ -295,4 +295,15 @@ config CRYPTO_DEV_TEGRA_AES
To compile this driver as a module, choose M here: the module
will be called tegra-aes.
config CRYPTO_DEV_UX500
tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
depends on ARCH_U8500
select CRYPTO_ALGAPI
help
Driver for ST-Ericsson UX500 crypto engine.
if CRYPTO_DEV_UX500
source "drivers/crypto/ux500/Kconfig"
endif # if CRYPTO_DEV_UX500
endif # CRYPTO_HW
......@@ -14,3 +14,4 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
\ No newline at end of file
#
# Copyright (C) ST-Ericsson SA 2010
# Author: Shujuan Chen (shujuan.chen@stericsson.com)
# License terms: GNU General Public License (GPL) version 2
#
config CRYPTO_DEV_UX500_CRYP
tristate "UX500 crypto driver for CRYP block"
depends on CRYPTO_DEV_UX500
select CRYPTO_DES
help
This selects the crypto driver for the UX500_CRYP hardware. It supports
AES-ECB, CBC and CTR with keys sizes of 128, 192 and 256 bit sizes.
config CRYPTO_DEV_UX500_DEBUG
bool "Activate ux500 platform debug-mode for crypto and hash block"
depends on CRYPTO_DEV_UX500_CRYP || CRYPTO_DEV_UX500_HASH
default n
help
Say Y if you want to add debug prints to ux500_hash and
ux500_cryp devices.
#
# Copyright (C) ST-Ericsson SA 2010
# Author: Shujuan Chen (shujuan.chen@stericsson.com)
# License terms: GNU General Public License (GPL) version 2
#
obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += cryp/
#/*
# * Copyright (C) ST-Ericsson SA 2010
# * Author: shujuan.chen@stericsson.com for ST-Ericsson.
# * License terms: GNU General Public License (GPL) version 2 */
ifdef CONFIG_CRYPTO_DEV_UX500_DEBUG
CFLAGS_cryp_core.o := -DDEBUG -O0
CFLAGS_cryp.o := -DDEBUG -O0
CFLAGS_cryp_irq.o := -DDEBUG -O0
endif
obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += ux500_cryp.o
ux500_cryp-objs := cryp.o cryp_irq.o cryp_core.o
This diff is collapsed.
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_H_
#define _CRYP_H_
#include <linux/completion.h>
#include <linux/dmaengine.h>
#include <linux/klist.h>
#include <linux/mutex.h>
#define DEV_DBG_NAME "crypX crypX:"
/* CRYP enable/disable */
enum cryp_crypen {
CRYP_CRYPEN_DISABLE = 0,
CRYP_CRYPEN_ENABLE = 1
};
/* CRYP Start Computation enable/disable */
enum cryp_start {
CRYP_START_DISABLE = 0,
CRYP_START_ENABLE = 1
};
/* CRYP Init Signal enable/disable */
enum cryp_init {
CRYP_INIT_DISABLE = 0,
CRYP_INIT_ENABLE = 1
};
/* Cryp State enable/disable */
enum cryp_state {
CRYP_STATE_DISABLE = 0,
CRYP_STATE_ENABLE = 1
};
/* Key preparation bit enable */
enum cryp_key_prep {
KSE_DISABLED = 0,
KSE_ENABLED = 1
};
/* Key size for AES */
#define CRYP_KEY_SIZE_128 (0)
#define CRYP_KEY_SIZE_192 (1)
#define CRYP_KEY_SIZE_256 (2)
/* AES modes */
enum cryp_algo_mode {
CRYP_ALGO_TDES_ECB,
CRYP_ALGO_TDES_CBC,
CRYP_ALGO_DES_ECB,
CRYP_ALGO_DES_CBC,
CRYP_ALGO_AES_ECB,
CRYP_ALGO_AES_CBC,
CRYP_ALGO_AES_CTR,
CRYP_ALGO_AES_XTS
};
/* Cryp Encryption or Decryption */
enum cryp_algorithm_dir {
CRYP_ALGORITHM_ENCRYPT,
CRYP_ALGORITHM_DECRYPT
};
/* Hardware access method */
enum cryp_mode {
CRYP_MODE_POLLING,
CRYP_MODE_INTERRUPT,
CRYP_MODE_DMA
};
/**
* struct cryp_config -
* @keysize: Key size for AES
* @algomode: AES modes
* @algodir: Cryp Encryption or Decryption
*
* CRYP configuration structure to be passed to set configuration
*/
struct cryp_config {
int keysize;
enum cryp_algo_mode algomode;
enum cryp_algorithm_dir algodir;
};
/**
* struct cryp_protection_config -
* @privilege_access: Privileged cryp state enable/disable
* @secure_access: Secure cryp state enable/disable
*
* Protection configuration structure for setting privilage access
*/
struct cryp_protection_config {
enum cryp_state privilege_access;
enum cryp_state secure_access;
};
/* Cryp status */
enum cryp_status_id {
CRYP_STATUS_BUSY = 0x10,
CRYP_STATUS_OUTPUT_FIFO_FULL = 0x08,
CRYP_STATUS_OUTPUT_FIFO_NOT_EMPTY = 0x04,
CRYP_STATUS_INPUT_FIFO_NOT_FULL = 0x02,
CRYP_STATUS_INPUT_FIFO_EMPTY = 0x01
};
/* Cryp DMA interface */
enum cryp_dma_req_type {
CRYP_DMA_DISABLE_BOTH,
CRYP_DMA_ENABLE_IN_DATA,
CRYP_DMA_ENABLE_OUT_DATA,
CRYP_DMA_ENABLE_BOTH_DIRECTIONS
};
enum cryp_dma_channel {
CRYP_DMA_RX = 0,
CRYP_DMA_TX
};
/* Key registers */
enum cryp_key_reg_index {
CRYP_KEY_REG_1,
CRYP_KEY_REG_2,
CRYP_KEY_REG_3,
CRYP_KEY_REG_4
};
/* Key register left and right */
struct cryp_key_value {
u32 key_value_left;
u32 key_value_right;
};
/* Cryp Initialization structure */
enum cryp_init_vector_index {
CRYP_INIT_VECTOR_INDEX_0,
CRYP_INIT_VECTOR_INDEX_1
};
/* struct cryp_init_vector_value -
* @init_value_left
* @init_value_right
* */
struct cryp_init_vector_value {
u32 init_value_left;
u32 init_value_right;
};
/**
* struct cryp_device_context - structure for a cryp context.
* @cr: control register
* @dmacr: DMA control register
* @imsc: Interrupt mask set/clear register
* @key_1_l: Key 1l register
* @key_1_r: Key 1r register
* @key_2_l: Key 2l register
* @key_2_r: Key 2r register
* @key_3_l: Key 3l register
* @key_3_r: Key 3r register
* @key_4_l: Key 4l register
* @key_4_r: Key 4r register
* @init_vect_0_l: Initialization vector 0l register
* @init_vect_0_r: Initialization vector 0r register
* @init_vect_1_l: Initialization vector 1l register
* @init_vect_1_r: Initialization vector 0r register
* @din: Data in register
* @dout: Data out register
*
* CRYP power management specifc structure.
*/
struct cryp_device_context {
u32 cr;
u32 dmacr;
u32 imsc;
u32 key_1_l;
u32 key_1_r;
u32 key_2_l;
u32 key_2_r;
u32 key_3_l;
u32 key_3_r;
u32 key_4_l;
u32 key_4_r;
u32 init_vect_0_l;
u32 init_vect_0_r;
u32 init_vect_1_l;
u32 init_vect_1_r;
u32 din;
u32 dout;
};
struct cryp_dma {
dma_cap_mask_t mask;
struct completion cryp_dma_complete;
struct dma_chan *chan_cryp2mem;
struct dma_chan *chan_mem2cryp;
struct stedma40_chan_cfg *cfg_cryp2mem;
struct stedma40_chan_cfg *cfg_mem2cryp;
int sg_src_len;
int sg_dst_len;
struct scatterlist *sg_src;
struct scatterlist *sg_dst;
int nents_src;
int nents_dst;
};
/**
* struct cryp_device_data - structure for a cryp device.
* @base: Pointer to the hardware base address.
* @dev: Pointer to the devices dev structure.
* @clk: Pointer to the device's clock control.
* @pwr_regulator: Pointer to the device's power control.
* @power_status: Current status of the power.
* @ctx_lock: Lock for current_ctx.
* @current_ctx: Pointer to the currently allocated context.
* @list_node: For inclusion into a klist.
* @dma: The dma structure holding channel configuration.
* @power_state: TRUE = power state on, FALSE = power state off.
* @power_state_spinlock: Spinlock for power_state.
* @restore_dev_ctx: TRUE = saved ctx, FALSE = no saved ctx.
*/
struct cryp_device_data {
struct cryp_register __iomem *base;
struct device *dev;
struct clk *clk;
struct regulator *pwr_regulator;
int power_status;
struct spinlock ctx_lock;
struct cryp_ctx *current_ctx;
struct klist_node list_node;
struct cryp_dma dma;
bool power_state;
struct spinlock power_state_spinlock;
bool restore_dev_ctx;
};
void cryp_wait_until_done(struct cryp_device_data *device_data);
/* Initialization functions */
int cryp_check(struct cryp_device_data *device_data);
void cryp_activity(struct cryp_device_data *device_data,
enum cryp_crypen cryp_crypen);
void cryp_flush_inoutfifo(struct cryp_device_data *device_data);
int cryp_set_configuration(struct cryp_device_data *device_data,
struct cryp_config *cryp_config,
u32 *control_register);
void cryp_configure_for_dma(struct cryp_device_data *device_data,
enum cryp_dma_req_type dma_req);
int cryp_configure_key_values(struct cryp_device_data *device_data,
enum cryp_key_reg_index key_reg_index,
struct cryp_key_value key_value);
int cryp_configure_init_vector(struct cryp_device_data *device_data,
enum cryp_init_vector_index
init_vector_index,
struct cryp_init_vector_value
init_vector_value);
int cryp_configure_protection(struct cryp_device_data *device_data,
struct cryp_protection_config *p_protect_config);
/* Power management funtions */
void cryp_save_device_context(struct cryp_device_data *device_data,
struct cryp_device_context *ctx,
int cryp_mode);
void cryp_restore_device_context(struct cryp_device_data *device_data,
struct cryp_device_context *ctx);
/* Data transfer and status bits. */
int cryp_is_logic_busy(struct cryp_device_data *device_data);
int cryp_get_status(struct cryp_device_data *device_data);
/**
* cryp_write_indata - This routine writes 32 bit data into the data input
* register of the cryptography IP.
* @device_data: Pointer to the device data struct for base address.
* @write_data: Data to write.
*/
int cryp_write_indata(struct cryp_device_data *device_data, u32 write_data);
/**
* cryp_read_outdata - This routine reads the data from the data output
* register of the CRYP logic
* @device_data: Pointer to the device data struct for base address.
* @read_data: Read the data from the output FIFO.
*/
int cryp_read_outdata(struct cryp_device_data *device_data, u32 *read_data);
#endif /* _CRYP_H_ */
This diff is collapsed.
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2.
*/
#include <linux/kernel.h>
#include <linux/bitmap.h>
#include <linux/device.h>
#include "cryp.h"
#include "cryp_p.h"
#include "cryp_irq.h"
#include "cryp_irqp.h"
void cryp_enable_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
u32 i;
dev_dbg(device_data->dev, "[%s]", __func__);
i = readl_relaxed(&device_data->base->imsc);
i = i | irq_src;
writel_relaxed(i, &device_data->base->imsc);
}
void cryp_disable_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
u32 i;
dev_dbg(device_data->dev, "[%s]", __func__);
i = readl_relaxed(&device_data->base->imsc);
i = i & ~irq_src;
writel_relaxed(i, &device_data->base->imsc);
}
bool cryp_pending_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
return (readl_relaxed(&device_data->base->mis) & irq_src) > 0;
}
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_IRQ_H_
#define _CRYP_IRQ_H_
#include "cryp.h"
enum cryp_irq_src_id {
CRYP_IRQ_SRC_INPUT_FIFO = 0x1,
CRYP_IRQ_SRC_OUTPUT_FIFO = 0x2,
CRYP_IRQ_SRC_ALL = 0x3
};
/**
* M0 Funtions
*/
void cryp_enable_irq_src(struct cryp_device_data *device_data, u32 irq_src);
void cryp_disable_irq_src(struct cryp_device_data *device_data, u32 irq_src);
bool cryp_pending_irq_src(struct cryp_device_data *device_data, u32 irq_src);
#endif /* _CRYP_IRQ_H_ */
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __CRYP_IRQP_H_
#define __CRYP_IRQP_H_
#include "cryp_irq.h"
/**
*
* CRYP Registers - Offset mapping
* +-----------------+
* 00h | CRYP_CR | Configuration register
* +-----------------+
* 04h | CRYP_SR | Status register
* +-----------------+
* 08h | CRYP_DIN | Data In register
* +-----------------+
* 0ch | CRYP_DOUT | Data out register
* +-----------------+
* 10h | CRYP_DMACR | DMA control register
* +-----------------+
* 14h | CRYP_IMSC | IMSC
* +-----------------+
* 18h | CRYP_RIS | Raw interrupt status
* +-----------------+
* 1ch | CRYP_MIS | Masked interrupt status.
* +-----------------+
* Key registers
* IVR registers
* Peripheral
* Cell IDs
*
* Refer data structure for other register map
*/
/**
* struct cryp_register
* @cr - Configuration register
* @status - Status register
* @din - Data input register
* @din_size - Data input size register
* @dout - Data output register
* @dout_size - Data output size register
* @dmacr - Dma control register
* @imsc - Interrupt mask set/clear register
* @ris - Raw interrupt status
* @mis - Masked interrupt statu register
* @key_1_l - Key register 1 L
* @key_1_r - Key register 1 R
* @key_2_l - Key register 2 L
* @key_2_r - Key register 2 R
* @key_3_l - Key register 3 L
* @key_3_r - Key register 3 R
* @key_4_l - Key register 4 L
* @key_4_r - Key register 4 R
* @init_vect_0_l - init vector 0 L
* @init_vect_0_r - init vector 0 R
* @init_vect_1_l - init vector 1 L
* @init_vect_1_r - init vector 1 R
* @cryp_unused1 - unused registers
* @itcr - Integration test control register
* @itip - Integration test input register
* @itop - Integration test output register
* @cryp_unused2 - unused registers
* @periphId0 - FE0 CRYP Peripheral Identication Register
* @periphId1 - FE4
* @periphId2 - FE8
* @periphId3 - FEC
* @pcellId0 - FF0 CRYP PCell Identication Register
* @pcellId1 - FF4
* @pcellId2 - FF8
* @pcellId3 - FFC
*/
struct cryp_register {
u32 cr; /* Configuration register */
u32 sr; /* Status register */
u32 din; /* Data input register */
u32 din_size; /* Data input size register */
u32 dout; /* Data output register */
u32 dout_size; /* Data output size register */
u32 dmacr; /* Dma control register */
u32 imsc; /* Interrupt mask set/clear register */
u32 ris; /* Raw interrupt status */
u32 mis; /* Masked interrupt statu register */
u32 key_1_l; /*Key register 1 L */
u32 key_1_r; /*Key register 1 R */
u32 key_2_l; /*Key register 2 L */
u32 key_2_r; /*Key register 2 R */
u32 key_3_l; /*Key register 3 L */
u32 key_3_r; /*Key register 3 R */
u32 key_4_l; /*Key register 4 L */
u32 key_4_r; /*Key register 4 R */
u32 init_vect_0_l; /*init vector 0 L */
u32 init_vect_0_r; /*init vector 0 R */
u32 init_vect_1_l; /*init vector 1 L */
u32 init_vect_1_r; /*init vector 1 R */
u32 cryp_unused1[(0x80 - 0x58) / sizeof(u32)]; /* unused registers */
u32 itcr; /*Integration test control register */
u32 itip; /*Integration test input register */
u32 itop; /*Integration test output register */
u32 cryp_unused2[(0xFE0 - 0x8C) / sizeof(u32)]; /* unused registers */
u32 periphId0; /* FE0 CRYP Peripheral Identication Register */
u32 periphId1; /* FE4 */
u32 periphId2; /* FE8 */
u32 periphId3; /* FEC */
u32 pcellId0; /* FF0 CRYP PCell Identication Register */
u32 pcellId1; /* FF4 */
u32 pcellId2; /* FF8 */
u32 pcellId3; /* FFC */
};
#endif
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_P_H_
#define _CRYP_P_H_
#include <linux/io.h>
#include <linux/bitops.h>
#include "cryp.h"
#include "cryp_irqp.h"
/**
* Generic Macros
*/
#define CRYP_SET_BITS(reg_name, mask) \
writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
#define CRYP_WRITE_BIT(reg_name, val, mask) \
writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
((val) & (mask))), reg_name)
#define CRYP_TEST_BITS(reg_name, val) \
(readl_relaxed(reg_name) & (val))
#define CRYP_PUT_BITS(reg, val, shift, mask) \
writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
(((u32)val << shift) & (mask))), reg)
/**
* CRYP specific Macros
*/
#define CRYP_PERIPHERAL_ID0 0xE3
#define CRYP_PERIPHERAL_ID1 0x05
#define CRYP_PERIPHERAL_ID2_DB8500 0x28
#define CRYP_PERIPHERAL_ID2_DB5500 0x29
#define CRYP_PERIPHERAL_ID3 0x00
#define CRYP_PCELL_ID0 0x0D
#define CRYP_PCELL_ID1 0xF0
#define CRYP_PCELL_ID2 0x05
#define CRYP_PCELL_ID3 0xB1
/**
* CRYP register default values
*/
#define MAX_DEVICE_SUPPORT 2
/* Priv set, keyrden set and datatype 8bits swapped set as default. */
#define CRYP_CR_DEFAULT 0x0482
#define CRYP_DMACR_DEFAULT 0x0
#define CRYP_IMSC_DEFAULT 0x0
#define CRYP_DIN_DEFAULT 0x0
#define CRYP_DOUT_DEFAULT 0x0
#define CRYP_KEY_DEFAULT 0x0
#define CRYP_INIT_VECT_DEFAULT 0x0
/**
* CRYP Control register specific mask
*/
#define CRYP_CR_SECURE_MASK BIT(0)
#define CRYP_CR_PRLG_MASK BIT(1)
#define CRYP_CR_ALGODIR_MASK BIT(2)
#define CRYP_CR_ALGOMODE_MASK (BIT(5) | BIT(4) | BIT(3))
#define CRYP_CR_DATATYPE_MASK (BIT(7) | BIT(6))
#define CRYP_CR_KEYSIZE_MASK (BIT(9) | BIT(8))
#define CRYP_CR_KEYRDEN_MASK BIT(10)
#define CRYP_CR_KSE_MASK BIT(11)
#define CRYP_CR_START_MASK BIT(12)
#define CRYP_CR_INIT_MASK BIT(13)
#define CRYP_CR_FFLUSH_MASK BIT(14)
#define CRYP_CR_CRYPEN_MASK BIT(15)
#define CRYP_CR_CONTEXT_SAVE_MASK (CRYP_CR_SECURE_MASK |\
CRYP_CR_PRLG_MASK |\
CRYP_CR_ALGODIR_MASK |\
CRYP_CR_ALGOMODE_MASK |\
CRYP_CR_DATATYPE_MASK |\
CRYP_CR_KEYSIZE_MASK |\
CRYP_CR_KEYRDEN_MASK |\
CRYP_CR_DATATYPE_MASK)
#define CRYP_SR_INFIFO_READY_MASK (BIT(0) | BIT(1))
#define CRYP_SR_IFEM_MASK BIT(0)
#define CRYP_SR_BUSY_MASK BIT(4)
/**
* Bit position used while setting bits in register
*/
#define CRYP_CR_PRLG_POS 1
#define CRYP_CR_ALGODIR_POS 2
#define CRYP_CR_ALGOMODE_POS 3
#define CRYP_CR_DATATYPE_POS 6
#define CRYP_CR_KEYSIZE_POS 8
#define CRYP_CR_KEYRDEN_POS 10
#define CRYP_CR_KSE_POS 11
#define CRYP_CR_START_POS 12
#define CRYP_CR_INIT_POS 13
#define CRYP_CR_CRYPEN_POS 15
#define CRYP_SR_BUSY_POS 4
/**
* CRYP PCRs------PC_NAND control register
* BIT_MASK
*/
#define CRYP_DMA_REQ_MASK (BIT(1) | BIT(0))
#define CRYP_DMA_REQ_MASK_POS 0
struct cryp_system_context {
/* CRYP Register structure */
struct cryp_register *p_cryp_reg[MAX_DEVICE_SUPPORT];
};
#endif
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment