Commit 27aab272 authored by Paul Burton's avatar Paul Burton

MIPS: bitops: ins start position is always an immediate

The start position for an ins instruction is always encoded as an
immediate, so allowing registers to be used by the inline asm makes no
sense. It should never happen anyway since a bit index should always be
small enough to be treated as an immediate, but remove the nonsensical
"r" for sanity.
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
parent 59361e99
...@@ -85,7 +85,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) ...@@ -85,7 +85,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
" " __INS "%0, %3, %2, 1 \n" " " __INS "%0, %3, %2, 1 \n"
" " __SC "%0, %1 \n" " " __SC "%0, %1 \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m) : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
: "ir" (bit), "r" (~0) : "i" (bit), "r" (~0)
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
} while (unlikely(!temp)); } while (unlikely(!temp));
return; return;
...@@ -150,7 +150,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) ...@@ -150,7 +150,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
" " __INS "%0, $0, %2, 1 \n" " " __INS "%0, $0, %2, 1 \n"
" " __SC "%0, %1 \n" " " __SC "%0, %1 \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m) : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
: "ir" (bit) : "i" (bit)
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
} while (unlikely(!temp)); } while (unlikely(!temp));
return; return;
...@@ -383,7 +383,7 @@ static inline int test_and_clear_bit(unsigned long nr, ...@@ -383,7 +383,7 @@ static inline int test_and_clear_bit(unsigned long nr,
" " __INS "%0, $0, %3, 1 \n" " " __INS "%0, $0, %3, 1 \n"
" " __SC "%0, %1 \n" " " __SC "%0, %1 \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "ir" (bit) : "i" (bit)
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
} while (unlikely(!temp)); } while (unlikely(!temp));
} else { } else {
......
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