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Commit 28681d62 authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Dave Jones
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[AGP] factor device capability collection

parent f458c23a
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Showing with 72 additions and 195 deletions
drivers/char/agp/amd-k8-agp.c
View file @ 28681d62
......@@ -370,62 +370,11 @@ static void agp_x86_64_agp_enable(u32 mode)
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+4, &command);
/*
* PASS2: go through all devices that claim to be
* AGP devices and collect their data.
*/
pci_for_each_dev(device) {
cap_ptr = pci_find_capability(device, PCI_CAP_ID_AGP);
if (cap_ptr != 0x00) {
/*
* Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum.
*/
pci_read_config_dword(device, cap_ptr + 4, &scratch);
/* adjust RQ depth */
command =
((command & ~0xff000000) |
min_t(u32, (mode & 0xff000000),
min_t(u32, (command & 0xff000000),
(scratch & 0xff000000))));
/* disable SBA if it's not supported */
if (!((command & 0x200) && (scratch & 0x200) && (mode & 0x200)))
command &= ~0x200;
/* disable FW if it's not supported */
if (!((command & 0x10) && (scratch & 0x10) && (mode & 0x10)))
command &= ~0x10;
if (!((command & 2) && (scratch & 2) && (mode & 2)))
command &= ~2; /* 8x */
if (!((command & 1) && (scratch & 1) && (mode & 1)))
command &= ~1; /* 4x */
}
}
/*
* PASS3: Figure out the 8X/4X setting and enable the
* target (our motherboard chipset).
*/
if (command & 2)
command &= ~5; /* 8X */
if (command & 1)
command &= ~6; /* 4X */
command = agp_collect_device_status(mode, command);
command |= 0x100;
pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+8, command);
/*
* PASS4: Go through all AGP devices and update the
* command registers.
*/
agp_device_command(command, 1);
}
......
drivers/char/agp/generic.c
View file @ 28681d62
......@@ -314,6 +314,69 @@ int agp_unbind_memory(agp_memory * curr)
/* Generic Agp routines - Start */
u32 agp_collect_device_status(u32 mode, u32 command)
{
struct pci_dev *device;
u8 agp;
u32 scratch;
pci_for_each_dev(device) {
agp = pci_find_capability(device, PCI_CAP_ID_AGP);
if (!agp)
continue;
/*
* Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum.
*/
pci_read_config_dword(device, agp + 4, &scratch);
/* adjust RQ depth */
command = ((command & ~0xff000000) |
min_t(u32, (mode & 0xff000000),
min_t(u32, (command & 0xff000000),
(scratch & 0xff000000))));
/* disable SBA if it's not supported */
if (!((command & 0x00000200) &&
(scratch & 0x00000200) &&
(mode & 0x00000200)))
command &= ~0x00000200;
/* disable FW if it's not supported */
if (!((command & 0x00000010) &&
(scratch & 0x00000010) &&
(mode & 0x00000010)))
command &= ~0x00000010;
if (!((command & 4) &&
(scratch & 4) &&
(mode & 4)))
command &= ~0x00000004;
if (!((command & 2) &&
(scratch & 2) &&
(mode & 2)))
command &= ~0x00000002;
if (!((command & 1) &&
(scratch & 1) &&
(mode & 1)))
command &= ~0x00000001;
}
if (command & 4)
command &= ~3; /* 4X */
if (command & 2)
command &= ~5; /* 2X (8X for AGP3.0) */
if (command & 1)
command &= ~6; /* 1X (4X for AGP3.0) */
return command;
}
void agp_device_command(u32 command, int agp_v3)
{
struct pci_dev *device;
......@@ -336,86 +399,17 @@ void agp_device_command(u32 command, int agp_v3)
void agp_generic_agp_enable(u32 mode)
{
struct pci_dev *device = NULL;
u32 command, scratch;
u8 cap_ptr;
u32 command;
pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 4, &command);
/*
* PASS1: go through all devices that claim to be
* AGP devices and collect their data.
*/
pci_for_each_dev(device) {
cap_ptr = pci_find_capability(device, PCI_CAP_ID_AGP);
if (cap_ptr != 0x00) {
/*
* Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum.
*/
pci_read_config_dword(device, cap_ptr + 4, &scratch);
/* adjust RQ depth */
command = ((command & ~0xff000000) |
min_t(u32, (mode & 0xff000000),
min_t(u32, (command & 0xff000000),
(scratch & 0xff000000))));
/* disable SBA if it's not supported */
if (!((command & 0x00000200) &&
(scratch & 0x00000200) &&
(mode & 0x00000200)))
command &= ~0x00000200;
/* disable FW if it's not supported */
if (!((command & 0x00000010) &&
(scratch & 0x00000010) &&
(mode & 0x00000010)))
command &= ~0x00000010;
if (!((command & 4) &&
(scratch & 4) &&
(mode & 4)))
command &= ~0x00000004;
if (!((command & 2) &&
(scratch & 2) &&
(mode & 2)))
command &= ~0x00000002;
if (!((command & 1) &&
(scratch & 1) &&
(mode & 1)))
command &= ~0x00000001;
}
}
/*
* PASS2: Figure out the 4X/2X/1X setting and enable the
* target (our motherboard chipset).
*/
if (command & 4)
command &= ~3; /* 4X */
if (command & 2)
command &= ~5; /* 2X */
if (command & 1)
command &= ~6; /* 1X */
command |= 0x00000100;
command = agp_collect_device_status(mode, command);
command |= 0x100;
pci_write_config_dword(agp_bridge.dev,
agp_bridge.capndx + 8,
command);
/*
* PASS3: Go throu all AGP devices and update the
* command registers.
*/
agp_device_command(command, 0);
}
......
drivers/char/agp/sworks-agp.c
View file @ 28681d62
......@@ -413,89 +413,23 @@ static struct aper_size_info_lvl2 serverworks_sizes[7] =
static void serverworks_agp_enable(u32 mode)
{
struct pci_dev *device = NULL;
u32 command, scratch, cap_id;
u8 cap_ptr;
u32 command;
pci_read_config_dword(serverworks_private.svrwrks_dev,
agp_bridge.capndx + 4,
&command);
/*
* PASS1: go throu all devices that claim to be
* AGP devices and collect their data.
*/
command = agp_collect_device_status(mode, command);
command &= ~0x10; /* disable FW */
command &= ~0x08;
pci_for_each_dev(device) {
cap_ptr = pci_find_capability(device, PCI_CAP_ID_AGP);
if (cap_ptr != 0x00) {
/*
* Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum.
*/
pci_read_config_dword(device, cap_ptr + 4, &scratch);
/* adjust RQ depth */
command =
((command & ~0xff000000) |
min_t(u32, (mode & 0xff000000),
min_t(u32, (command & 0xff000000),
(scratch & 0xff000000))));
/* disable SBA if it's not supported */
if (!((command & 0x00000200) &&
(scratch & 0x00000200) &&
(mode & 0x00000200)))
command &= ~0x00000200;
/* disable FW */
command &= ~0x00000010;
command &= ~0x00000008;
if (!((command & 4) &&
(scratch & 4) &&
(mode & 4)))
command &= ~0x00000004;
if (!((command & 2) &&
(scratch & 2) &&
(mode & 2)))
command &= ~0x00000002;
if (!((command & 1) &&
(scratch & 1) &&
(mode & 1)))
command &= ~0x00000001;
}
}
/*
* PASS2: Figure out the 4X/2X/1X setting and enable the
* target (our motherboard chipset).
*/
if (command & 4) {
command &= ~3; /* 4X */
}
if (command & 2) {
command &= ~5; /* 2X */
}
if (command & 1) {
command &= ~6; /* 1X */
}
command |= 0x00000100;
command |= 0x100;
pci_write_config_dword(serverworks_private.svrwrks_dev,
agp_bridge.capndx + 8,
command);
/*
* PASS3: Go throu all AGP devices and update the
* command registers.
*/
agp_device_command(command, 0);
}
......
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