Commit 28bbe4ea authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'i2c-for-6.11-rc1-second-batch' of...

Merge tag 'i2c-for-6.11-rc1-second-batch' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull more i2c updates from Wolfram Sang:
 "The I2C core has two header documentation updates as the dependecies
  are in now.

  The I2C host drivers add some patches which nearly fell through the
  cracks:

   - Added descriptions in the DTS for the Qualcomm SM8650 and SM8550
     Camera Control Interface (CCI).

   - Added support for the "settle-time-us" property, which allows the
     gpio-mux device to switch from one bus to another with a
     configurable delay. The time can be set in the DTS. The latest
     change also includes file sorting.

   - Fixed slot numbering in the SMBus framework to prevent failures
     when more than 8 slots are occupied. It now enforces a a maximum of
     8 slots to be used. This ensures that the Intel PIIX4 device can
     register the SPDs correctly without failure, even if other slots
     are populated but not used"

* tag 'i2c-for-6.11-rc1-second-batch' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  i2c: header: improve kdoc for i2c_algorithm
  i2c: header: remove unneeded stuff regarding i2c_algorithm
  i2c: piix4: Register SPDs
  i2c: smbus: remove i801 assumptions from SPD probing
  i2c: mux: gpio: Add support for the 'settle-time-us' property
  i2c: mux: gpio: Re-order #include to match alphabetic order
  dt-bindings: i2c: mux-gpio: Add 'settle-time-us' property
  dt-bindings: i2c: qcom-cci: Document sm8650 compatible
  dt-bindings: i2c: qcom-cci: Document sm8550 compatible
parents d51f8f63 385ac870
......@@ -57,6 +57,9 @@ properties:
last value used.
$ref: /schemas/types.yaml#/definitions/uint32
settle-time-us:
description: Delay to wait before doing any transfer when a new bus gets selected.
allOf:
- $ref: i2c-mux.yaml
......
......@@ -31,6 +31,8 @@ properties:
- qcom,sm6350-cci
- qcom,sm8250-cci
- qcom,sm8450-cci
- qcom,sm8550-cci
- qcom,sm8650-cci
- const: qcom,msm8996-cci # CCI v2
"#address-cells":
......@@ -195,6 +197,24 @@ allOf:
- const: cpas_ahb
- const: cci
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-cci
- qcom,sm8650-cci
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: camnoc_axi
- const: cpas_ahb
- const: cci
additionalProperties: false
examples:
......
......@@ -196,6 +196,7 @@ config I2C_ISMT
config I2C_PIIX4
tristate "Intel PIIX4 and compatible (ATI/AMD/Serverworks/Broadcom/SMSC)"
depends on PCI && HAS_IOPORT
select I2C_SMBUS
help
If you say yes to this option, support will be included for the Intel
PIIX4 family of mainboard I2C interfaces. Specifically, the following
......
......@@ -29,6 +29,7 @@
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/i2c.h>
#include <linux/i2c-smbus.h>
#include <linux/slab.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
......@@ -982,6 +983,14 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
return retval;
}
/*
* The AUX bus can not be probed as on some platforms it reports all
* devices present and all reads return "0".
* This would allow the ee1004 to be probed incorrectly.
*/
if (port == 0)
i2c_register_spd(adap);
*padap = adap;
return 0;
}
......
......@@ -352,18 +352,11 @@ void i2c_register_spd(struct i2c_adapter *adap)
return;
/*
* If we're a child adapter on a muxed segment, then limit slots to 8,
* as this is the max number of SPD EEPROMs that can be addressed per bus.
* The max number of SPD EEPROMs that can be addressed per bus is 8.
* If more slots are present either muxed or multiple busses are
* necessary or the additional slots are ignored.
*/
if (i2c_parent_is_i2c_adapter(adap)) {
slot_count = 8;
} else {
if (slot_count > 8) {
dev_warn(&adap->dev,
"More than 8 memory slots on a single bus, contact i801 maintainer to add missing mux config\n");
return;
}
}
slot_count = min(slot_count, 8);
/*
* Memory types could be found at section 7.18.2 (Memory Device — Type), table 78
......
......@@ -5,16 +5,17 @@
* Peter Korsgaard <peter.korsgaard@barco.com>
*/
#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/i2c.h>
#include <linux/i2c-mux.h>
#include <linux/module.h>
#include <linux/overflow.h>
#include <linux/platform_data/i2c-mux-gpio.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/bits.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
struct gpiomux {
struct i2c_mux_gpio_platform_data data;
......@@ -37,6 +38,9 @@ static int i2c_mux_gpio_select(struct i2c_mux_core *muxc, u32 chan)
i2c_mux_gpio_set(mux, chan);
if (mux->data.settle_time)
fsleep(mux->data.settle_time);
return 0;
}
......@@ -116,6 +120,8 @@ static int i2c_mux_gpio_probe_fw(struct gpiomux *mux,
if (device_property_read_u32(dev, "idle-state", &mux->data.idle))
mux->data.idle = I2C_MUX_GPIO_NO_IDLE;
device_property_read_u32(dev, "settle-time-us", &mux->data.settle_time);
return 0;
}
......
......@@ -30,7 +30,6 @@ extern const struct device_type i2c_client_type;
/* --- General options ------------------------------------------------ */
struct i2c_msg;
struct i2c_algorithm;
struct i2c_adapter;
struct i2c_client;
struct i2c_driver;
......@@ -512,16 +511,15 @@ i2c_register_board_info(int busnum, struct i2c_board_info const *info,
#endif /* I2C_BOARDINFO */
/**
* struct i2c_algorithm - represent I2C transfer method
* @xfer: Issue a set of i2c transactions to the given I2C adapter
* defined by the msgs array, with num messages available to transfer via
* the adapter specified by adap.
* @xfer_atomic: same as @xfer. Yet, only using atomic context
* so e.g. PMICs can be accessed very late before shutdown. Optional.
* @smbus_xfer: Issue smbus transactions to the given I2C adapter. If this
* struct i2c_algorithm - represent I2C transfer methods
* @xfer: Transfer a given number of messages defined by the msgs array via
* the specified adapter.
* @xfer_atomic: Same as @xfer. Yet, only using atomic context so e.g. PMICs
* can be accessed very late before shutdown. Optional.
* @smbus_xfer: Issue SMBus transactions to the given I2C adapter. If this
* is not present, then the bus layer will try and convert the SMBus calls
* into I2C transfers instead.
* @smbus_xfer_atomic: same as @smbus_xfer. Yet, only using atomic context
* @smbus_xfer_atomic: Same as @smbus_xfer. Yet, only using atomic context
* so e.g. PMICs can be accessed very late before shutdown. Optional.
* @functionality: Return the flags that this algorithm/adapter pair supports
* from the ``I2C_FUNC_*`` flags.
......@@ -533,8 +531,6 @@ i2c_register_board_info(int busnum, struct i2c_board_info const *info,
* @reg_slave: deprecated, use @reg_target
* @unreg_slave: deprecated, use @unreg_target
*
*
* The following structs are for those who like to implement new bus drivers:
* i2c_algorithm is the interface to a class of hardware solutions which can
* be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
* to name two of the most common.
......@@ -550,9 +546,6 @@ struct i2c_algorithm {
* to NULL. If an adapter algorithm can do SMBus access, set
* smbus_xfer. If set to NULL, the SMBus protocol is simulated
* using common I2C messages.
*
* xfer should return the number of messages successfully
* processed, or a negative value on error
*/
union {
int (*xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs,
......
......@@ -19,6 +19,7 @@
* position
* @n_values: Number of multiplexer positions (busses to instantiate)
* @idle: Bitmask to write to MUX when idle or GPIO_I2CMUX_NO_IDLE if not used
* @settle_time: Delay to wait when a new bus is selected
*/
struct i2c_mux_gpio_platform_data {
int parent;
......@@ -26,6 +27,7 @@ struct i2c_mux_gpio_platform_data {
const unsigned *values;
int n_values;
unsigned idle;
u32 settle_time;
};
#endif /* _LINUX_I2C_MUX_GPIO_H */
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