Commit 28e8e29c authored by Marc Zyngier's avatar Marc Zyngier Committed by Arnd Bergmann

ARM: consolidate pen_release instead of having per platform definitions

Almost each SMP platform defines pen_release to manage booting secondary
CPUs. This of course clashes with the single zImage effort.

Add the pen_release definition to the ARM SMP code, and remove all others.
This should only be used by platforms which lack any kind of CPU power
management...
Reported-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent ac6c7998
...@@ -70,6 +70,7 @@ struct secondary_data { ...@@ -70,6 +70,7 @@ struct secondary_data {
void *stack; void *stack;
}; };
extern struct secondary_data secondary_data; extern struct secondary_data secondary_data;
extern volatile int pen_release;
extern int __cpu_disable(void); extern int __cpu_disable(void);
......
...@@ -51,6 +51,12 @@ ...@@ -51,6 +51,12 @@
*/ */
struct secondary_data secondary_data; struct secondary_data secondary_data;
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
enum ipi_msg_type { enum ipi_msg_type {
IPI_TIMER = 2, IPI_TIMER = 2,
IPI_RESCHEDULE, IPI_RESCHEDULE,
......
...@@ -23,8 +23,6 @@ ...@@ -23,8 +23,6 @@
#include "common.h" #include "common.h"
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void) static inline void cpu_enter_lowpower(void)
{ {
unsigned int v; unsigned int v;
......
...@@ -39,13 +39,6 @@ extern void exynos4_secondary_startup(void); ...@@ -39,13 +39,6 @@ extern void exynos4_secondary_startup(void);
#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM5 : S5P_VA_SYSRAM) S5P_INFORM5 : S5P_VA_SYSRAM)
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
/* /*
* Write pen_release in a way that is guaranteed to be visible to all * Write pen_release in a way that is guaranteed to be visible to all
* observers, irrespective of whether they're taking part in coherency * observers, irrespective of whether they're taking part in coherency
......
...@@ -15,8 +15,6 @@ ...@@ -15,8 +15,6 @@
#include "core.h" #include "core.h"
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void) static inline void cpu_enter_lowpower(void)
{ {
/* Just flush the cache. Changing the coherency is not yet /* Just flush the cache. Changing the coherency is not yet
......
...@@ -35,11 +35,6 @@ ...@@ -35,11 +35,6 @@
#define GIC_PPI_EDGE_MASK 0xFFFFD7FF #define GIC_PPI_EDGE_MASK 0xFFFFD7FF
extern void msm_secondary_startup(void); extern void msm_secondary_startup(void);
/*
* control for which core is the next to come out of the secondary
* boot "holding pen".
*/
volatile int pen_release = -1;
static DEFINE_SPINLOCK(boot_lock); static DEFINE_SPINLOCK(boot_lock);
......
...@@ -16,8 +16,6 @@ ...@@ -16,8 +16,6 @@
#include <asm/cp15.h> #include <asm/cp15.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void) static inline void cpu_enter_lowpower(void)
{ {
unsigned int v; unsigned int v;
......
...@@ -17,8 +17,6 @@ ...@@ -17,8 +17,6 @@
#include <asm/cp15.h> #include <asm/cp15.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void) static inline void cpu_enter_lowpower(void)
{ {
unsigned int v; unsigned int v;
......
...@@ -21,11 +21,6 @@ ...@@ -21,11 +21,6 @@
#include <mach/spear.h> #include <mach/spear.h>
#include <mach/generic.h> #include <mach/generic.h>
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
static DEFINE_SPINLOCK(boot_lock); static DEFINE_SPINLOCK(boot_lock);
static void __iomem *scu_base = IOMEM(VA_SCU_BASE); static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
......
...@@ -17,8 +17,6 @@ ...@@ -17,8 +17,6 @@
#include <mach/setup.h> #include <mach/setup.h>
extern volatile int pen_release;
/* /*
* platform-specific code to shutdown a CPU * platform-specific code to shutdown a CPU
* *
......
...@@ -27,12 +27,6 @@ ...@@ -27,12 +27,6 @@
/* This is called from headsmp.S to wakeup the secondary core */ /* This is called from headsmp.S to wakeup the secondary core */
extern void u8500_secondary_startup(void); extern void u8500_secondary_startup(void);
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int pen_release = -1;
/* /*
* Write pen_release in a way that is guaranteed to be visible to all * Write pen_release in a way that is guaranteed to be visible to all
* observers, irrespective of whether they're taking part in coherency * observers, irrespective of whether they're taking part in coherency
......
...@@ -16,8 +16,6 @@ ...@@ -16,8 +16,6 @@
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
#include <asm/cp15.h> #include <asm/cp15.h>
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void) static inline void cpu_enter_lowpower(void)
{ {
unsigned int v; unsigned int v;
......
...@@ -19,12 +19,6 @@ ...@@ -19,12 +19,6 @@
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
/* /*
* Write pen_release in a way that is guaranteed to be visible to all * Write pen_release in a way that is guaranteed to be visible to all
* observers, irrespective of whether they're taking part in coherency * observers, irrespective of whether they're taking part in coherency
......
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