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Commit 293d2e97 authored by Georgi Djakov's avatar Georgi Djakov Committed by Stephen Boyd
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clk: qcom: Introduce parent_map tables 

In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.

This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
 - Define a parent_map struct to map the relations between PLL source index
 and register configuration value.
 - Add a qcom_find_src_index() function for finding the index of a clock
 matching the specific PLL configuration.
 - Update the {set,get}_parent RCG functions use the newly introduced
 parent_map struct.
 - Convert all existing drivers to the new parent_map tables.
Signed-off-by: default avatarGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent fae507af
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Showing with 338 additions and 286 deletions
drivers/clk/qcom/clk-rcg.c
View file @ 293d2e97
......@@ -54,7 +54,7 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
goto err;
ns = ns_to_src(&rcg->s, ns);
for (i = 0; i < num_parents; i++)
if (ns == rcg->s.parent_map[i])
if (ns == rcg->s.parent_map[i].cfg)
return i;
err:
......@@ -90,7 +90,7 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
ns = ns_to_src(s, ns);
for (i = 0; i < num_parents; i++)
if (ns == s->parent_map[i])
if (ns == s->parent_map[i].cfg)
return i;
err:
......@@ -105,7 +105,7 @@ static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
u32 ns;
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns);
ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
return 0;
......@@ -206,7 +206,7 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
{
u32 ns, md, reg;
int bank, new_bank, ret;
int bank, new_bank, ret, index;
struct mn *mn;
struct pre_div *p;
struct src_sel *s;
......@@ -276,7 +276,10 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
}
s = &rcg->s[new_bank];
ns = src_to_ns(s, s->parent_map[f->src], ns);
index = qcom_find_src_index(hw, s->parent_map, f->src);
if (index < 0)
return index;
ns = src_to_ns(s, s->parent_map[index].cfg, ns);
ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
if (ret)
return ret;
......
drivers/clk/qcom/clk-rcg.h
View file @ 293d2e97
......@@ -25,6 +25,16 @@ struct freq_tbl {
u16 n;
};
/**
* struct parent_map - map table for PLL source select configuration values
* @src: source PLL
* @cfg: configuration value
*/
struct parent_map {
u8 src;
u8 cfg;
};
/**
* struct mn - M/N:D counter
* @mnctr_en_bit: bit to enable mn counter
......@@ -65,7 +75,7 @@ struct pre_div {
struct src_sel {
u8 src_sel_shift;
#define SRC_SEL_MASK 0x7
const u8 *parent_map;
const struct parent_map *parent_map;
};
/**
......@@ -151,7 +161,7 @@ struct clk_rcg2 {
u32 cmd_rcgr;
u8 mnd_width;
u8 hid_width;
const u8 *parent_map;
const struct parent_map *parent_map;
const struct freq_tbl *freq_tbl;
struct clk_regmap clkr;
};
......
drivers/clk/qcom/clk-rcg2.c
View file @ 293d2e97
......@@ -75,7 +75,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
cfg >>= CFG_SRC_SEL_SHIFT;
for (i = 0; i < num_parents; i++)
if (cfg == rcg->parent_map[i])
if (cfg == rcg->parent_map[i].cfg)
return i;
err:
......@@ -114,10 +114,10 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int ret;
u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
CFG_SRC_SEL_MASK,
rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
CFG_SRC_SEL_MASK, cfg);
if (ret)
return ret;
......@@ -222,7 +222,11 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
{
u32 cfg, mask;
int ret;
struct clk_hw *hw = &rcg->clkr.hw;
int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
if (index < 0)
return index;
if (rcg->mnd_width && f->n) {
mask = BIT(rcg->mnd_width) - 1;
......@@ -245,7 +249,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
mask = BIT(rcg->hid_width) - 1;
mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
if (rcg->mnd_width && f->n && (f->m != f->n))
cfg |= CFG_MODE_DUAL_EDGE;
ret = regmap_update_bits(rcg->clkr.regmap,
......
drivers/clk/qcom/common.c
View file @ 293d2e97
......@@ -43,6 +43,18 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
}
EXPORT_SYMBOL_GPL(qcom_find_freq);
int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
{
int i, num_parents = __clk_get_num_parents(hw->clk);
for (i = 0; i < num_parents; i++)
if (src == map[i].src)
return i;
return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_src_index);
struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
......
drivers/clk/qcom/common.h
View file @ 293d2e97
......@@ -19,6 +19,8 @@ struct clk_regmap;
struct qcom_reset_map;
struct regmap;
struct freq_tbl;
struct clk_hw;
struct parent_map;
struct qcom_cc_desc {
const struct regmap_config *config;
......@@ -30,6 +32,8 @@ struct qcom_cc_desc {
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
unsigned long rate);
extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
u8 src);
extern struct regmap *qcom_cc_map(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
......
drivers/clk/qcom/gcc-apq8084.c
View file @ 293d2e97
......@@ -32,18 +32,20 @@
#include "clk-branch.h"
#include "reset.h"
#define P_XO 0
#define P_GPLL0 1
#define P_GPLL1 1
#define P_GPLL4 2
#define P_PCIE_0_1_PIPE_CLK 1
#define P_SATA_ASIC0_CLK 1
#define P_SATA_RX_CLK 1
#define P_SLEEP_CLK 1
enum {
P_XO,
P_GPLL0,
P_GPLL1,
P_GPLL4,
P_PCIE_0_1_PIPE_CLK,
P_SATA_ASIC0_CLK,
P_SATA_RX_CLK,
P_SLEEP_CLK,
};
static const u8 gcc_xo_gpll0_map[] = {
[P_XO] = 0,
[P_GPLL0] = 1,
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 }
};
static const char *gcc_xo_gpll0[] = {
......@@ -51,10 +53,10 @@ static const char *gcc_xo_gpll0[] = {
"gpll0_vote",
};
static const u8 gcc_xo_gpll0_gpll4_map[] = {
[P_XO] = 0,
[P_GPLL0] = 1,
[P_GPLL4] = 5,
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 5 }
};
static const char *gcc_xo_gpll0_gpll4[] = {
......@@ -63,9 +65,9 @@ static const char *gcc_xo_gpll0_gpll4[] = {
"gpll4_vote",
};
static const u8 gcc_xo_sata_asic0_map[] = {
[P_XO] = 0,
[P_SATA_ASIC0_CLK] = 2,
static const struct parent_map gcc_xo_sata_asic0_map[] = {
{ P_XO, 0 },
{ P_SATA_ASIC0_CLK, 2 }
};
static const char *gcc_xo_sata_asic0[] = {
......@@ -73,9 +75,9 @@ static const char *gcc_xo_sata_asic0[] = {
"sata_asic0_clk",
};
static const u8 gcc_xo_sata_rx_map[] = {
[P_XO] = 0,
[P_SATA_RX_CLK] = 2,
static const struct parent_map gcc_xo_sata_rx_map[] = {
{ P_XO, 0 },
{ P_SATA_RX_CLK, 2}
};
static const char *gcc_xo_sata_rx[] = {
......@@ -83,9 +85,9 @@ static const char *gcc_xo_sata_rx[] = {
"sata_rx_clk",
};
static const u8 gcc_xo_pcie_map[] = {
[P_XO] = 0,
[P_PCIE_0_1_PIPE_CLK] = 2,
static const struct parent_map gcc_xo_pcie_map[] = {
{ P_XO, 0 },
{ P_PCIE_0_1_PIPE_CLK, 2 }
};
static const char *gcc_xo_pcie[] = {
......@@ -93,9 +95,9 @@ static const char *gcc_xo_pcie[] = {
"pcie_pipe",
};
static const u8 gcc_xo_pcie_sleep_map[] = {
[P_XO] = 0,
[P_SLEEP_CLK] = 6,
static const struct parent_map gcc_xo_pcie_sleep_map[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 6 }
};
static const char *gcc_xo_pcie_sleep[] = {
......@@ -1263,9 +1265,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
{ }
};
static u8 usb_hsic_clk_src_map[] = {
[P_XO] = 0,
[P_GPLL1] = 4,
static const struct parent_map usb_hsic_clk_src_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 4 }
};
static struct clk_rcg2 usb_hsic_clk_src = {
......
drivers/clk/qcom/gcc-ipq806x.c
View file @ 293d2e97
......@@ -140,15 +140,17 @@ static struct clk_regmap pll14_vote = {
},
};
#define P_PXO 0
#define P_PLL8 1
#define P_PLL3 1
#define P_PLL0 2
#define P_CXO 2
enum {
P_PXO,
P_PLL8,
P_PLL3,
P_PLL0,
P_CXO,
};
static const u8 gcc_pxo_pll8_map[] = {
[P_PXO] = 0,
[P_PLL8] = 3,
static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 }
};
static const char *gcc_pxo_pll8[] = {
......@@ -156,10 +158,10 @@ static const char *gcc_pxo_pll8[] = {
"pll8_vote",
};
static const u8 gcc_pxo_pll8_cxo_map[] = {
[P_PXO] = 0,
[P_PLL8] = 3,
[P_CXO] = 5,
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_CXO, 5 }
};
static const char *gcc_pxo_pll8_cxo[] = {
......@@ -168,14 +170,14 @@ static const char *gcc_pxo_pll8_cxo[] = {
"cxo",
};
static const u8 gcc_pxo_pll3_map[] = {
[P_PXO] = 0,
[P_PLL3] = 1,
static const struct parent_map gcc_pxo_pll3_map[] = {
{ P_PXO, 0 },
{ P_PLL3, 1 }
};
static const u8 gcc_pxo_pll3_sata_map[] = {
[P_PXO] = 0,
[P_PLL3] = 6,
static const struct parent_map gcc_pxo_pll3_sata_map[] = {
{ P_PXO, 0 },
{ P_PLL3, 6 }
};
static const char *gcc_pxo_pll3[] = {
......@@ -183,10 +185,10 @@ static const char *gcc_pxo_pll3[] = {
"pll3",
};
static const u8 gcc_pxo_pll8_pll0[] = {
[P_PXO] = 0,
[P_PLL8] = 3,
[P_PLL0] = 2,
static const struct parent_map gcc_pxo_pll8_pll0[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_PLL0, 2 }
};
static const char *gcc_pxo_pll8_pll0_map[] = {
......
drivers/clk/qcom/gcc-msm8660.c
View file @ 293d2e97
......@@ -59,13 +59,15 @@ static struct clk_regmap pll8_vote = {
},
};
#define P_PXO 0
#define P_PLL8 1
#define P_CXO 2
enum {
P_PXO,
P_PLL8,
P_CXO,
};
static const u8 gcc_pxo_pll8_map[] = {
[P_PXO] = 0,
[P_PLL8] = 3,
static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 }
};
static const char *gcc_pxo_pll8[] = {
......@@ -73,10 +75,10 @@ static const char *gcc_pxo_pll8[] = {
"pll8_vote",
};
static const u8 gcc_pxo_pll8_cxo_map[] = {
[P_PXO] = 0,
[P_PLL8] = 3,
[P_CXO] = 5,
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_CXO, 5 }
};
static const char *gcc_pxo_pll8_cxo[] = {
......
drivers/clk/qcom/gcc-msm8960.c
View file @ 293d2e97
......@@ -113,14 +113,16 @@ static struct clk_regmap pll14_vote = {
},
};
#define P_PXO 0
#define P_PLL8 1
#define P_PLL3 2
#define P_CXO 2
enum {
P_PXO,
P_PLL8,
P_PLL3,
P_CXO,
};
static const u8 gcc_pxo_pll8_map[] = {
[P_PXO] = 0,
[P_PLL8] = 3,
static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 }
};
static const char *gcc_pxo_pll8[] = {
......@@ -128,10 +130,10 @@ static const char *gcc_pxo_pll8[] = {
"pll8_vote",
};
static const u8 gcc_pxo_pll8_cxo_map[] = {
[P_PXO] = 0,
[P_PLL8] = 3,
[P_CXO] = 5,
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_CXO, 5 }
};
static const char *gcc_pxo_pll8_cxo[] = {
......@@ -140,10 +142,10 @@ static const char *gcc_pxo_pll8_cxo[] = {
"cxo",
};
static const u8 gcc_pxo_pll8_pll3_map[] = {
[P_PXO] = 0,
[P_PLL8] = 3,
[P_PLL3] = 6,
static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_PLL3, 6 }
};
static const char *gcc_pxo_pll8_pll3[] = {
......
drivers/clk/qcom/gcc-msm8974.c
View file @ 293d2e97
......@@ -32,14 +32,16 @@
#include "clk-branch.h"
#include "reset.h"
#define P_XO 0
#define P_GPLL0 1
#define P_GPLL1 1
#define P_GPLL4 2
enum {
P_XO,
P_GPLL0,
P_GPLL1,
P_GPLL4,
};
static const u8 gcc_xo_gpll0_map[] = {
[P_XO] = 0,
[P_GPLL0] = 1,
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 }
};
static const char *gcc_xo_gpll0[] = {
......@@ -47,10 +49,10 @@ static const char *gcc_xo_gpll0[] = {
"gpll0_vote",
};
static const u8 gcc_xo_gpll0_gpll4_map[] = {
[P_XO] = 0,
[P_GPLL0] = 1,
[P_GPLL4] = 5,
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 5 }
};
static const char *gcc_xo_gpll0_gpll4[] = {
......@@ -984,9 +986,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
{ }
};
static u8 usb_hsic_clk_src_map[] = {
[P_XO] = 0,
[P_GPLL1] = 4,
static const struct parent_map usb_hsic_clk_src_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 4 }
};
static struct clk_rcg2 usb_hsic_clk_src = {
......
drivers/clk/qcom/lcc-ipq806x.c
View file @ 293d2e97
......@@ -61,12 +61,14 @@ static const struct pll_config pll4_config = {
.main_output_mask = BIT(23),
};
#define P_PXO 0
#define P_PLL4 1
enum {
P_PXO,
P_PLL4,
};
static const u8 lcc_pxo_pll4_map[] = {
[P_PXO] = 0,
[P_PLL4] = 2,
static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PXO, 0 },
{ P_PLL4, 2 }
};
static const char *lcc_pxo_pll4[] = {
......
drivers/clk/qcom/lcc-msm8960.c
View file @ 293d2e97
......@@ -47,12 +47,14 @@ static struct clk_pll pll4 = {
},
};
#define P_PXO 0
#define P_PLL4 1
enum {
P_PXO,
P_PLL4,
};
static const u8 lcc_pxo_pll4_map[] = {
[P_PXO] = 0,
[P_PLL4] = 2,
static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PXO, 0 },
{ P_PLL4, 2 }
};
static const char *lcc_pxo_pll4[] = {
......
drivers/clk/qcom/mmcc-apq8084.c
View file @ 293d2e97
......@@ -27,28 +27,30 @@
#include "clk-branch.h"
#include "reset.h"
#define P_XO 0
#define P_MMPLL0 1
#define P_EDPLINK 1
#define P_MMPLL1 2
#define P_HDMIPLL 2
#define P_GPLL0 3
#define P_EDPVCO 3
#define P_MMPLL4 4
#define P_DSI0PLL 4
#define P_DSI0PLL_BYTE 4
#define P_MMPLL2 4
#define P_MMPLL3 4
#define P_GPLL1 5
#define P_DSI1PLL 5
#define P_DSI1PLL_BYTE 5
#define P_MMSLEEP 6
static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_GPLL0] = 5,
enum {
P_XO,
P_MMPLL0,
P_EDPLINK,
P_MMPLL1,
P_HDMIPLL,
P_GPLL0,
P_EDPVCO,
P_MMPLL4,
P_DSI0PLL,
P_DSI0PLL_BYTE,
P_MMPLL2,
P_MMPLL3,
P_GPLL1,
P_DSI1PLL,
P_DSI1PLL_BYTE,
P_MMSLEEP,
};
static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 }
};
static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
......@@ -58,13 +60,13 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
"mmss_gpll0_vote",
};
static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_HDMIPLL] = 4,
[P_GPLL0] = 5,
[P_DSI0PLL] = 2,
[P_DSI1PLL] = 3,
static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_HDMIPLL, 4 },
{ P_GPLL0, 5 },
{ P_DSI0PLL, 2 },
{ P_DSI1PLL, 3 }
};
static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
......@@ -76,12 +78,12 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
"dsi1pll",
};
static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_GPLL0] = 5,
[P_MMPLL2] = 3,
static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL2, 3 }
};
static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
......@@ -92,12 +94,12 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
"mmpll2",
};
static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_GPLL0] = 5,
[P_MMPLL3] = 3,
static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL3, 3 }
};
static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
......@@ -108,13 +110,13 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
"mmpll3",
};
static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
[P_XO] = 0,
[P_EDPLINK] = 4,
[P_HDMIPLL] = 3,
[P_EDPVCO] = 5,
[P_DSI0PLL] = 1,
[P_DSI1PLL] = 2,
static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_EDPVCO, 5 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const char *mmcc_xo_dsi_hdmi_edp[] = {
......@@ -126,13 +128,13 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
"dsi1pll",
};
static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
[P_XO] = 0,
[P_EDPLINK] = 4,
[P_HDMIPLL] = 3,
[P_GPLL0] = 5,
[P_DSI0PLL] = 1,
[P_DSI1PLL] = 2,
static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_GPLL0, 5 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
......@@ -144,13 +146,13 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
"dsi1pll",
};
static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
[P_XO] = 0,
[P_EDPLINK] = 4,
[P_HDMIPLL] = 3,
[P_GPLL0] = 5,
[P_DSI0PLL_BYTE] = 1,
[P_DSI1PLL_BYTE] = 2,
static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_GPLL0, 5 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 2 }
};
static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
......@@ -162,12 +164,12 @@ static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
"dsi1pllbyte",
};
static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_GPLL0] = 5,
[P_MMPLL4] = 3,
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL4, 3 }
};
static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
......@@ -178,13 +180,13 @@ static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
"gpll0",
};
static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_MMPLL4] = 3,
[P_GPLL0] = 5,
[P_GPLL1] = 4,
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_MMPLL4, 3 },
{ P_GPLL0, 5 },
{ P_GPLL1, 4 }
};
static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
......@@ -196,14 +198,14 @@ static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
"gpll0",
};
static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_MMPLL4] = 3,
[P_GPLL0] = 5,
[P_GPLL1] = 4,
[P_MMSLEEP] = 6,
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_MMPLL4, 3 },
{ P_GPLL0, 5 },
{ P_GPLL1, 4 },
{ P_MMSLEEP, 6 }
};
static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
......
drivers/clk/qcom/mmcc-msm8960.c
View file @ 293d2e97
......@@ -33,18 +33,21 @@
#include "clk-branch.h"
#include "reset.h"
#define P_PXO 0
#define P_PLL8 1
#define P_PLL2 2
#define P_PLL3 3
#define P_PLL15 3
enum {
P_PXO,
P_PLL8,
P_PLL2,
P_PLL3,
P_PLL15,
P_HDMI_PLL,
};
#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
static u8 mmcc_pxo_pll8_pll2_map[] = {
[P_PXO] = 0,
[P_PLL8] = 2,
[P_PLL2] = 1,
static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 }
};
static const char *mmcc_pxo_pll8_pll2[] = {
......@@ -53,11 +56,11 @@ static const char *mmcc_pxo_pll8_pll2[] = {
"pll2",
};
static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
[P_PXO] = 0,
[P_PLL8] = 2,
[P_PLL2] = 1,
[P_PLL3] = 3,
static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 },
{ P_PLL3, 3 }
};
static const char *mmcc_pxo_pll8_pll2_pll15[] = {
......@@ -67,11 +70,11 @@ static const char *mmcc_pxo_pll8_pll2_pll15[] = {
"pll15",
};
static u8 mmcc_pxo_pll8_pll2_pll15_map[] = {
[P_PXO] = 0,
[P_PLL8] = 2,
[P_PLL2] = 1,
[P_PLL15] = 3,
static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 2 },
{ P_PLL2, 1 },
{ P_PLL15, 3 }
};
static const char *mmcc_pxo_pll8_pll2_pll3[] = {
......@@ -1377,11 +1380,9 @@ static struct clk_branch rot_clk = {
},
};
#define P_HDMI_PLL 1
static u8 mmcc_pxo_hdmi_map[] = {
[P_PXO] = 0,
[P_HDMI_PLL] = 3,
static const struct parent_map mmcc_pxo_hdmi_map[] = {
{ P_PXO, 0 },
{ P_HDMI_PLL, 3 }
};
static const char *mmcc_pxo_hdmi[] = {
......
drivers/clk/qcom/mmcc-msm8974.c
View file @ 293d2e97
......@@ -32,26 +32,28 @@
#include "clk-branch.h"
#include "reset.h"
#define P_XO 0
#define P_MMPLL0 1
#define P_EDPLINK 1
#define P_MMPLL1 2
#define P_HDMIPLL 2
#define P_GPLL0 3
#define P_EDPVCO 3
#define P_GPLL1 4
#define P_DSI0PLL 4
#define P_DSI0PLL_BYTE 4
#define P_MMPLL2 4
#define P_MMPLL3 4
#define P_DSI1PLL 5
#define P_DSI1PLL_BYTE 5
static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_GPLL0] = 5,
enum {
P_XO,
P_MMPLL0,
P_EDPLINK,
P_MMPLL1,
P_HDMIPLL,
P_GPLL0,
P_EDPVCO,
P_GPLL1,
P_DSI0PLL,
P_DSI0PLL_BYTE,
P_MMPLL2,
P_MMPLL3,
P_DSI1PLL,
P_DSI1PLL_BYTE,
};
static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 }
};
static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
......@@ -61,13 +63,13 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
"mmss_gpll0_vote",
};
static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_HDMIPLL] = 4,
[P_GPLL0] = 5,
[P_DSI0PLL] = 2,
[P_DSI1PLL] = 3,
static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_HDMIPLL, 4 },
{ P_GPLL0, 5 },
{ P_DSI0PLL, 2 },
{ P_DSI1PLL, 3 }
};
static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
......@@ -79,12 +81,12 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
"dsi1pll",
};
static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_GPLL0] = 5,
[P_MMPLL2] = 3,
static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL2, 3 }
};
static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
......@@ -95,12 +97,12 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
"mmpll2",
};
static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_GPLL0] = 5,
[P_MMPLL3] = 3,
static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL3, 3 }
};
static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
......@@ -111,12 +113,12 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
"mmpll3",
};
static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = {
[P_XO] = 0,
[P_MMPLL0] = 1,
[P_MMPLL1] = 2,
[P_GPLL0] = 5,
[P_GPLL1] = 4,
static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_GPLL1, 4 }
};
static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
......@@ -127,13 +129,13 @@ static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
"gpll1_vote",
};
static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
[P_XO] = 0,
[P_EDPLINK] = 4,
[P_HDMIPLL] = 3,
[P_EDPVCO] = 5,
[P_DSI0PLL] = 1,
[P_DSI1PLL] = 2,
static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_EDPVCO, 5 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const char *mmcc_xo_dsi_hdmi_edp[] = {
......@@ -145,13 +147,13 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
"dsi1pll",
};
static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
[P_XO] = 0,
[P_EDPLINK] = 4,
[P_HDMIPLL] = 3,
[P_GPLL0] = 5,
[P_DSI0PLL] = 1,
[P_DSI1PLL] = 2,
static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_GPLL0, 5 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
......@@ -163,13 +165,13 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
"dsi1pll",
};
static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
[P_XO] = 0,
[P_EDPLINK] = 4,
[P_HDMIPLL] = 3,
[P_GPLL0] = 5,
[P_DSI0PLL_BYTE] = 1,
[P_DSI1PLL_BYTE] = 2,
static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_GPLL0, 5 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 2 }
};
static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
......
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