Commit 29dc7ef3 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Handle 320 vs. 333 MHz cdclk on vlv

Depending on the HPLL frequency one of the supported cdclk frquencies is
either 320MHz or 333MHz. Figure out which one it is to accurately pick
the minimal required cdclk. This would also avoid a warning from the
cdclk code where it compares the actual cdclk read out from the hardware
with a value that was calculated using valleyview_calc_cdclk().
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d197b7d3
...@@ -4545,19 +4545,22 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) ...@@ -4545,19 +4545,22 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
int max_pixclk) int max_pixclk)
{ {
int vco = valleyview_get_vco(dev_priv);
int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
/* /*
* Really only a few cases to deal with, as only 4 CDclks are supported: * Really only a few cases to deal with, as only 4 CDclks are supported:
* 200MHz * 200MHz
* 267MHz * 267MHz
* 320MHz * 320/333MHz (depends on HPLL freq)
* 400MHz * 400MHz
* So we check to see whether we're above 90% of the lower bin and * So we check to see whether we're above 90% of the lower bin and
* adjust if needed. * adjust if needed.
*/ */
if (max_pixclk > 320000*9/10) if (max_pixclk > freq_320*9/10)
return 400000; return 400000;
else if (max_pixclk > 266667*9/10) else if (max_pixclk > 266667*9/10)
return 320000; return freq_320;
else else
return 266667; return 266667;
/* Looks like the 200MHz CDclk freq doesn't work on some configs */ /* Looks like the 200MHz CDclk freq doesn't work on some configs */
......
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