Commit 2a2bf85f authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM soc device tree updates from Olof Johansson:
 "Device tree conversion and enablement branch.  Mostly a bunch of new
  bindings and setup for various platforms, but the Via/Winchip VT8500
  platform is also converted over from being 100% legacy to now use
  device tree for probing.  More of that will come for 3.8."

Trivial conflicts due to removal of vt8500 files, and one documentation
file that was added with slightly different contents both here and in
the USb tree.

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (212 commits)
  arm: vt8500: Fixup for missing gpio.h
  ARM: LPC32xx: LED fix in PHY3250 DTS file
  ARM: dt: mmp-dma: add binding file
  arm: vt8500: Update arch-vt8500 to devicetree support.
  arm: vt8500: gpio: Devicetree support for arch-vt8500
  arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
  arm: vt8500: clk: Add Common Clock Framework support
  video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
  serial: vt8500: Add devicetree support for vt8500-serial
  rtc: vt8500: Add devicetree support for vt8500-rtc
  arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
  ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support
  ARM: tegra: Add Avionic Design Medcom-Wide support
  ARM: tegra: Add Avionic Design Plutux support
  ARM: tegra: Add Avionic Design Tamonten support
  ARM: tegra: dts: Add pwm label
  ARM: ux500: Fix SSP register address format
  ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT
  ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT
  ARM: ux500: Add all encompassing sound node to the HREF Device Tree
  ...
parents 11801e9d 99261fba
* Marvell Tauros2 Cache
Required properties:
- compatible : Should be "marvell,tauros2-cache".
- marvell,tauros2-cache-features : Specify the features supported for the
tauros2 cache.
The features including
CACHE_TAUROS2_PREFETCH_ON (1 << 0)
CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
The definition can be found at
arch/arm/include/asm/hardware/cache-tauros2.h
Example:
L2: l2-cache {
compatible = "marvell,tauros2-cache";
marvell,tauros2-cache-features = <0x3>;
};
* MSM Timer
Properties:
- compatible : Should at least contain "qcom,msm-timer". More specific
properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
purpose timer and a debug timer respectively.
- interrupts : Interrupt indicating a match event.
- reg : Specifies the base address of the timer registers. The second region
specifies an optional register used to configure the clock divider.
- clock-frequency : The frequency of the timer in Hz.
Optional:
- cpu-offset : per-cpu offset used when the timer is accessed without the
CPU remapping facilities. The offset is cpu-offset * cpu-nr.
Example:
timer@200a004 {
compatible = "qcom,msm-gpt", "qcom,msm-timer";
interrupts = <1 2 0x301>;
reg = <0x0200a004 0x10>;
clock-frequency = <32768>;
cpu-offset = <0x40000>;
};
timer@200a024 {
compatible = "qcom,msm-dgt", "qcom,msm-timer";
interrupts = <1 3 0x301>;
reg = <0x0200a024 0x10>,
<0x0200a034 0x4>;
clock-frequency = <6750000>;
cpu-offset = <0x40000>;
};
......@@ -36,6 +36,9 @@ Boards:
- OMAP3 BeagleBoard : Low cost community board
compatible = "ti,omap3-beagle", "ti,omap3"
- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
- OMAP4 SDP : Software Developement Board
compatible = "ti,omap4-sdp", "ti,omap4430"
......
VIA/Wondermedia VT8500 Platforms Device Tree Bindings
---------------------------------------
Boards with the VIA VT8500 SoC shall have the following properties:
Required root node property:
compatible = "via,vt8500";
Boards with the Wondermedia WM8505 SoC shall have the following properties:
Required root node property:
compatible = "wm,wm8505";
Boards with the Wondermedia WM8650 SoC shall have the following properties:
Required root node property:
compatible = "wm,wm8650";
VIA/Wondermedia VT8500 Interrupt Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-intc"
- reg : Should contain 1 register ranges(address and length)
- #interrupt-cells : should be <1>
Example:
intc: interrupt-controller@d8140000 {
compatible = "via,vt8500-intc";
interrupt-controller;
reg = <0xd8140000 0x10000>;
#interrupt-cells = <1>;
};
VIA/Wondermedia VT8500 Power Management Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-pmc"
- reg : Should contain 1 register ranges(address and length)
Example:
pmc@d8130000 {
compatible = "via,vt8500-pmc";
reg = <0xd8130000 0x1000>;
};
VIA/Wondermedia VT8500 Timer
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-timer"
- reg : Should contain 1 register ranges(address and length)
- interrupts : interrupt for the timer
Example:
timer@d8130100 {
compatible = "via,vt8500-timer";
reg = <0xd8130100 0x28>;
interrupts = <36>;
};
* Clock bindings for Freescale i.MX23
Required properties:
- compatible: Should be "fsl,imx23-clkctrl"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX23
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll 1
ref_cpu 2
ref_emi 3
ref_pix 4
ref_io 5
saif_sel 6
lcdif_sel 7
gpmi_sel 8
ssp_sel 9
emi_sel 10
cpu 11
etm_sel 12
cpu_pll 13
cpu_xtal 14
hbus 15
xbus 16
lcdif_div 17
ssp_div 18
gpmi_div 19
emi_pll 20
emi_xtal 21
etm_div 22
saif_div 23
clk32k_div 24
rtc 25
adc 26
spdif_div 27
clk32k 28
dri 29
pwm 30
filt 31
uart 32
ssp 33
gpmi 34
spdif 35
emi 36
saif 37
lcdif 38
etm 39
usb 40
usb_pwr 41
Examples:
clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
clock-output-names =
...
"uart", /* 32 */
...
"end_of_list";
};
auart0: serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
status = "disabled";
};
* Clock bindings for Freescale i.MX28
Required properties:
- compatible: Should be "fsl,imx28-clkctrl"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX28
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll0 1
pll1 2
pll2 3
ref_cpu 4
ref_emi 5
ref_io0 6
ref_io1 7
ref_pix 8
ref_hsadc 9
ref_gpmi 10
saif0_sel 11
saif1_sel 12
gpmi_sel 13
ssp0_sel 14
ssp1_sel 15
ssp2_sel 16
ssp3_sel 17
emi_sel 18
etm_sel 19
lcdif_sel 20
cpu 21
ptp_sel 22
cpu_pll 23
cpu_xtal 24
hbus 25
xbus 26
ssp0_div 27
ssp1_div 28
ssp2_div 29
ssp3_div 30
gpmi_div 31
emi_pll 32
emi_xtal 33
lcdif_div 34
etm_div 35
ptp 36
saif0_div 37
saif1_div 38
clk32k_div 39
rtc 40
lradc 41
spdif_div 42
clk32k 43
pwm 44
uart 45
ssp0 46
ssp1 47
ssp2 48
ssp3 49
gpmi 50
spdif 51
emi 52
saif0 53
saif1 54
lcdif 55
etm 56
fec 57
can0 58
can1 59
usb0 60
usb1 61
usb0_pwr 62
usb1_pwr 63
enet_out 64
Examples:
clks: clkctrl@80040000 {
compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
clock-output-names =
...
"uart", /* 45 */
...
"end_of_list";
};
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
clocks = <&clks 45>;
status = "disabled";
};
* Clock bindings for Freescale i.MX6 Quad
Required properties:
- compatible: Should be "fsl,imx6q-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
clocks and IDs.
Clock ID
---------------------------
dummy 0
ckil 1
ckih 2
osc 3
pll2_pfd0_352m 4
pll2_pfd1_594m 5
pll2_pfd2_396m 6
pll3_pfd0_720m 7
pll3_pfd1_540m 8
pll3_pfd2_508m 9
pll3_pfd3_454m 10
pll2_198m 11
pll3_120m 12
pll3_80m 13
pll3_60m 14
twd 15
step 16
pll1_sw 17
periph_pre 18
periph2_pre 19
periph_clk2_sel 20
periph2_clk2_sel 21
axi_sel 22
esai_sel 23
asrc_sel 24
spdif_sel 25
gpu2d_axi 26
gpu3d_axi 27
gpu2d_core_sel 28
gpu3d_core_sel 29
gpu3d_shader_sel 30
ipu1_sel 31
ipu2_sel 32
ldb_di0_sel 33
ldb_di1_sel 34
ipu1_di0_pre_sel 35
ipu1_di1_pre_sel 36
ipu2_di0_pre_sel 37
ipu2_di1_pre_sel 38
ipu1_di0_sel 39
ipu1_di1_sel 40
ipu2_di0_sel 41
ipu2_di1_sel 42
hsi_tx_sel 43
pcie_axi_sel 44
ssi1_sel 45
ssi2_sel 46
ssi3_sel 47
usdhc1_sel 48
usdhc2_sel 49
usdhc3_sel 50
usdhc4_sel 51
enfc_sel 52
emi_sel 53
emi_slow_sel 54
vdo_axi_sel 55
vpu_axi_sel 56
cko1_sel 57
periph 58
periph2 59
periph_clk2 60
periph2_clk2 61
ipg 62
ipg_per 63
esai_pred 64
esai_podf 65
asrc_pred 66
asrc_podf 67
spdif_pred 68
spdif_podf 69
can_root 70
ecspi_root 71
gpu2d_core_podf 72
gpu3d_core_podf 73
gpu3d_shader 74
ipu1_podf 75
ipu2_podf 76
ldb_di0_podf 77
ldb_di1_podf 78
ipu1_di0_pre 79
ipu1_di1_pre 80
ipu2_di0_pre 81
ipu2_di1_pre 82
hsi_tx_podf 83
ssi1_pred 84
ssi1_podf 85
ssi2_pred 86
ssi2_podf 87
ssi3_pred 88
ssi3_podf 89
uart_serial_podf 90
usdhc1_podf 91
usdhc2_podf 92
usdhc3_podf 93
usdhc4_podf 94
enfc_pred 95
enfc_podf 96
emi_podf 97
emi_slow_podf 98
vpu_axi_podf 99
cko1_podf 100
axi 101
mmdc_ch0_axi_podf 102
mmdc_ch1_axi_podf 103
arm 104
ahb 105
apbh_dma 106
asrc 107
can1_ipg 108
can1_serial 109
can2_ipg 110
can2_serial 111
ecspi1 112
ecspi2 113
ecspi3 114
ecspi4 115
ecspi5 116
enet 117
esai 118
gpt_ipg 119
gpt_ipg_per 120
gpu2d_core 121
gpu3d_core 122
hdmi_iahb 123
hdmi_isfr 124
i2c1 125
i2c2 126
i2c3 127
iim 128
enfc 129
ipu1 130
ipu1_di0 131
ipu1_di1 132
ipu2 133
ipu2_di0 134
ldb_di0 135
ldb_di1 136
ipu2_di1 137
hsi_tx 138
mlb 139
mmdc_ch0_axi 140
mmdc_ch1_axi 141
ocram 142
openvg_axi 143
pcie_axi 144
pwm1 145
pwm2 146
pwm3 147
pwm4 148
per1_bch 149
gpmi_bch_apb 150
gpmi_bch 151
gpmi_io 152
gpmi_apb 153
sata 154
sdma 155
spba 156
ssi1 157
ssi2 158
ssi3 159
uart_ipg 160
uart_serial 161
usboh3 162
usdhc1 163
usdhc2 164
usdhc3 165
usdhc4 166
vdo_axi 167
vpu_axi 168
cko1 169
pll1_sys 170
pll2_bus 171
pll3_usb_otg 172
pll4_audio 173
pll5_video 174
pll6_mlb 175
pll7_usb_host 176
pll8_enet 177
ssi1_ipg 178
ssi2_ipg 179
ssi3_ipg 180
rom 181
usbphy1 182
usbphy2 183
ldb_di0_div_3_5 184
ldb_di1_div_3_5 185
Examples:
clks: ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
clock-output-names = ...
"uart_ipg",
"uart_serial",
...;
};
uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks 160>, <&clks 161>;
clock-names = "ipg", "per";
status = "disabled";
};
Device Tree Clock bindings for arch-vt8500
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
"wm,wm8650-pll-clock" - for a WM8650 PLL clock
"via,vt8500-device-clock" - for a VT/WM device clock
Required properties for PLL clocks:
- reg : shall be the control register offset from PMC base for the pll clock.
- clocks : shall be the input parent clock phandle for the clock. This should
be the reference clock.
- #clock-cells : from common clock binding; shall be set to 0.
Required properties for device clocks:
- clocks : shall be the input parent clock phandle for the clock. This should
be a pll output.
- #clock-cells : from common clock binding; shall be set to 0.
Device Clocks
Device clocks are required to have one or both of the following sets of
properties:
Gated device clocks:
Required properties:
- enable-reg : shall be the register offset from PMC base for the enable
register.
- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
Divisor device clocks:
Required property:
- divisor-reg : shall be the register offset from PMC base for the divisor
register.
Optional property:
- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
if not specified.
For example:
ref25: ref25M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
plla: plla {
#clock-cells = <0>;
compatible = "wm,wm8650-pll-clock";
clocks = <&ref25>;
reg = <0x200>;
};
sdhc: sdhc {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x328>;
divisor-mask = <0x3f>;
enable-reg = <0x254>;
enable-bit = <18>;
};
* MARVELL MMP DMA controller
Marvell Peripheral DMA Controller
Used platfroms: pxa688, pxa910, pxa3xx, etc
Required properties:
- compatible: Should be "marvell,pdma-1.0"
- reg: Should contain DMA registers location and length.
- interrupts: Either contain all of the per-channel DMA interrupts
or one irq for pdma device
- #dma-channels: Number of DMA channels supported by the controller.
"marvell,pdma-1.0"
Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
Examples:
/*
* Each channel has specific irq
* ICU parse out irq channel from ICU register,
* while DMA controller may not able to distinguish the irq channel
* Using this method, interrupt-parent is required as demuxer
* For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
* 18~21 is ADMA irq
*/
pdma: dma-controller@d4000000 {
compatible = "marvell,pdma-1.0";
reg = <0xd4000000 0x10000>;
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
interrupt-parent = <&intcmux32>;
#dma-channels = <16>;
};
/*
* One irq for all channels
* Dmaengine driver (DMA controller) distinguish irq channel via
* parsing internal register
*/
pdma: dma-controller@d4000000 {
compatible = "marvell,pdma-1.0";
reg = <0xd4000000 0x10000>;
interrupts = <47>;
#dma-channels = <16>;
};
Marvell Two Channel DMA Controller used specifically for audio
Used platfroms: pxa688, pxa910
Required properties:
- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
- reg: Should contain DMA registers location and length.
- interrupts: Either contain all of the per-channel DMA interrupts
or one irq for dma device
"marvell,adma-1.0" used on pxa688
"marvell,pxa910-squ" used on pxa910
Examples:
/* each channel has specific irq */
adma0: dma-controller@d42a0800 {
compatible = "marvell,adma-1.0";
reg = <0xd42a0800 0x100>;
interrupts = <18 19>;
interrupt-parent = <&intcmux32>;
};
/* One irq for all channels */
squ: dma-controller@d42a0800 {
compatible = "marvell,pxa910-squ";
reg = <0xd42a0800 0x100>;
interrupts = <46>;
};
......@@ -39,3 +39,46 @@ Example:
#gpio-cells = <4>;
gpio-controller;
};
Samsung S3C24XX GPIO Controller
Required properties:
- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
- reg: Physical base address of the controller and length of memory mapped
region.
- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
should be the following with values derived from the SoC user manual.
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[mux function]
[flags and pull up/down]
Values for gpio specifier:
- Pin number: depending on the controller a number from 0 up to 15.
- Mux function: Depending on the SoC and the gpio bank the gpio can be set
as input, output or a special function
- Flags and Pull Up/Down: the values to use differ for the individual SoCs
example S3C2416/S3C2450:
0 - Pull Up/Down Disabled.
1 - Pull Down Enabled.
2 - Pull Up Enabled.
Bit 16 (0x00010000) - Input is active low.
Consult the user manual for the correct values of Mux and Pull Up/Down.
- gpio-controller: Specifies that the node is a gpio controller.
- #address-cells: should be 1.
- #size-cells: should be 1.
Example:
gpa: gpio-controller@56000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "samsung,s3c24xx-gpio";
reg = <0x56000000 0x10>;
#gpio-cells = <3>;
gpio-controller;
};
......@@ -11,6 +11,11 @@ Required properties:
- interrupt-controller: Mark the device node as an interrupt controller
The first cell is the GPIO number.
The second cell is not used.
- ti,use-leds : Enables LEDA and LEDB outputs if set
- ti,debounce : if n-th bit is set, debounces GPIO-n
- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
Example:
......@@ -20,4 +25,5 @@ twl_gpio: gpio {
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
ti,use-leds;
};
VIA/Wondermedia VT8500 GPIO Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
or "wm,wm8650-gpio" depending on your SoC
- reg : Should contain 1 register range (address and length)
- #gpio-cells : should be <3>.
1) bank
2) pin number
3) flags - should be 0
Example:
gpio: gpio-controller@d8110000 {
compatible = "via,vt8500-gpio";
gpio-controller;
reg = <0xd8110000 0x10000>;
#gpio-cells = <3>;
};
vibrate {
gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
};
......@@ -56,3 +56,4 @@ stm,m41t00 Serial Access TIMEKEEPER
stm,m41t62 Serial real-time clock (RTC) with alarm
stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
ti,tsc2003 I2C Touch-Screen Controller
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
Required properties:
- compatible : Should be "jedec,lpddr2-timings"
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
Optional properties:
The following properties represent AC timing parameters from the memory
data-sheet of the device for a given speed-bin. All these properties are
of type <u32> and the default unit is ps (pico seconds). Parameters with
a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
- tRCD
- tWR
- tRAS-min
- tRRD
- tWTR
- tXP
- tRTP
- tDQSCK-max
- tFAW
- tZQCS
- tZQinit
- tRPab
- tZQCL
- tCKESR
- tRAS-max-ns
- tDQSCK-max-derated
Example:
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
Required properties:
- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
"jedec,lpddr2-s4"
"ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
"ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
"ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
- density : <u32> representing density in Mb (Mega bits)
- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
Optional properties:
The following optional properties represent the minimum value of some AC
timing parameters of the DDR device in terms of number of clock cycles.
These values shall be obtained from the device data-sheet.
- tRRD-min-tck
- tWTR-min-tck
- tXP-min-tck
- tRTP-min-tck
- tCKE-min-tck
- tRPab-min-tck
- tRCD-min-tck
- tWR-min-tck
- tRASmin-min-tck
- tCKESR-min-tck
- tFAW-min-tck
Child nodes:
- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
speed-bins as is required. Please see Documentation/devicetree/
bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
Example:
elpida_ECB240ABACN : lpddr2 {
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
tWR-min-tck = <3>;
tRASmin-min-tck = <3>;
tRRD-min-tck = <2>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tRTP-min-tck = <2>;
tCKE-min-tck = <3>;
tCKESR-min-tck = <3>;
tFAW-min-tck = <8>;
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <200000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <10000>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
}
* EMIF family of TI SDRAM controllers
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
is the IP revision of the specific EMIF instance.
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
<1> : Attila PHY
<2> : Intelli PHY
- device-handle : phandle to a "lpddr2" node representing the memory part
- ti,hwmods : For TI hwmods processing and omap device creation
the value shall be "emif<n>" where <n> is the number of the EMIF
instance with base 1.
Optional properties:
- cs1-used : Have this property if CS1 of this EMIF
instance has a memory part attached to it. If there is a memory
part attached to CS1, it should be the same type as the one on CS0,
so there is no need to give the details of this memory part.
- cal-resistor-per-cs : Have this property if the board has one
calibration resistor per chip-select.
- hw-caps-read-idle-ctrl: Have this property if the controller
supports read idle window programming
- hw-caps-dll-calib-ctrl: Have this property if the controller
supports dll calibration control
- hw-caps-ll-interface : Have this property if the controller
has a low latency interface and corresponding interrupt events
- hw-caps-temp-alert : Have this property if the controller
has capability for generating SDRAM temperature alerts
Example:
emif1: emif@0x4c000000 {
compatible = "ti,emif-4d";
ti,hwmods = "emif2";
phy-type = <1>;
device-handle = <&elpida_ECB240ABACN>;
cs1-used;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
......@@ -23,6 +23,7 @@ Device IRQ Names Supply Names Description
ab8500-bm : : : Battery Manager
ab8500-btemp : : : Battery Temperature
ab8500-charger : : : Battery Charger
ab8500-codec : : : Audio Codec
ab8500-fg : : : Fuel Gauge
ab8500-gpadc : HW_CONV_END : vddadc : Analogue to Digital Converter
SW_CONV_END : :
......@@ -52,6 +53,14 @@ Optional child device properties:
supplied in the interrupts property
- <supply_name>-supply : contains a phandle to the regulator supply node in Device Tree
Non-standard child device properties:
- Audio CODEC:
- stericsson,amic[1|2]-type-single-ended : Single-ended Analoge Mic (default: differential)
- stericsson,amic1a-bias-vamic2 : Analoge Mic wishes to use a non-standard Vamic
- stericsson,amic1b-bias-vamic2 : Analoge Mic wishes to use a non-standard Vamic
- stericsson,amic2-bias-vamic1 : Analoge Mic wishes to use a non-standard Vamic
- stericsson,earpeice-cmv : Earpeice voltage (only: 950 | 1100 | 1270 | 1580)
ab8500@5 {
compatible = "stericsson,ab8500";
reg = <5>; /* mailbox 5 is i2c */
......@@ -110,6 +119,12 @@ ab8500@5 {
compatible = "stericsson,ab8500-pwm";
};
codec: ab8500-codec {
compatible = "stericsson,ab8500-codec";
stericsson,earpeice-cmv = <950>; /* Units in mV. */
};
ab8500-regulators {
compatible = "stericsson,ab8500-regulator";
......
PXA3xx NAND DT bindings
Required properties:
- compatible: Should be "marvell,pxa3xx-nand"
- reg: The register base for the controller
- interrupts: The interrupt to map
- #address-cells: Set to <1> if the node includes partitions
Optional properties:
- marvell,nand-enable-arbiter: Set to enable the bus arbiter
- marvell,nand-keep-config: Set to keep the NAND controller config as set
by the bootloader
- num-cs: Number of chipselect lines to usw
Example:
nand0: nand@43100000 {
compatible = "marvell,pxa3xx-nand";
reg = <0x43100000 90>;
interrupts = <45>;
#address-cells = <1>;
marvell,nand-enable-arbiter;
marvell,nand-keep-config;
num-cs = <1>;
/* partitions (optional) */
};
* PXA RTC
PXA specific RTC driver.
Required properties:
- compatible : Should be "marvell,pxa-rtc"
Examples:
rtc@40900000 {
compatible = "marvell,pxa-rtc";
reg = <0x40900000 0x3c>;
interrupts = <30 31>;
};
VIA/Wondermedia VT8500 Realtime Clock Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-rtc"
- reg : Should contain 1 register ranges(address and length)
- interrupts : alarm interrupt
Example:
rtc@d8100000 {
compatible = "via,vt8500-rtc";
reg = <0xd8100000 0x10000>;
interrupts = <48>;
};
* MOP500 Audio Machine Driver
This node is responsible for linking together all ux500 Audio Driver components.
Required properties:
- compatible : "stericsson,snd-soc-mop500"
Non-standard properties:
- stericsson,cpu-dai : Phandle to the CPU-side DAI
- stericsson,audio-codec : Phandle to the Audio CODEC
- stericsson,card-name : Over-ride default card name
Example:
sound {
compatible = "stericsson,snd-soc-mop500";
stericsson,cpu-dai = <&msp1 &msp3>;
stericsson,audio-codec = <&codec>;
};
msp1: msp@80124000 {
compatible = "stericsson,ux500-msp-i2s";
reg = <0x80124000 0x1000>;
interrupts = <0 62 0x4>;
v-ape-supply = <&db8500_vape_reg>;
};
msp3: msp@80125000 {
compatible = "stericsson,ux500-msp-i2s";
reg = <0x80125000 0x1000>;
interrupts = <0 62 0x4>;
v-ape-supply = <&db8500_vape_reg>;
};
codec: ab8500-codec {
compatible = "stericsson,ab8500-codec";
stericsson,earpeice-cmv = <950>; /* Units in mV. */
};
* ux500 MSP (CPU-side Digital Audio Interface)
Required properties:
- compatible :"stericsson,ux500-msp-i2s"
- reg : Physical base address and length of the device's registers.
Optional properties:
- interrupts : The interrupt output from the device.
- interrupt-parent : The parent interrupt controller.
- <name>-supply : Phandle to the regulator <name> supply
Example:
sound {
compatible = "stericsson,snd-soc-mop500";
stericsson,platform-pcm-dma = <&pcm>;
stericsson,cpu-dai = <&msp1 &msp3>;
stericsson,audio-codec = <&codec>;
};
pcm: ux500-pcm {
compatible = "stericsson,ux500-pcm";
};
msp1: msp@80124000 {
compatible = "stericsson,ux500-msp-i2s";
reg = <0x80124000 0x1000>;
interrupts = <0 62 0x4>;
v-ape-supply = <&db8500_vape_reg>;
};
msp3: msp@80125000 {
compatible = "stericsson,ux500-msp-i2s";
reg = <0x80125000 0x1000>;
interrupts = <0 62 0x4>;
v-ape-supply = <&db8500_vape_reg>;
};
codec: ab8500-codec {
compatible = "stericsson,ab8500-codec";
stericsson,earpeice-cmv = <950>; /* Units in mV. */
};
VIA/Wondermedia VT8500 UART Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-uart"
- reg : Should contain 1 register ranges(address and length)
- interrupts : UART interrupt
- clocks : phandle to the uart source clock (usually a 24Mhz fixed clock)
Example:
uart@d8210000 {
compatible = "via,vt8500-uart";
reg = <0xd8210000 0x1040>;
interrupts = <47>;
clocks = <&ref24>;
};
Generic Platform UHCI controllers.
Generic Platform UHCI Controller
-----------------------------------------------------
Required properties:
- compatible: Should be "platform-uhci".
- reg: Address range of the uhci registers
- interrupts: Should contain the uhci interrupt.
- compatible : "platform-uhci"
- reg : Should contain 1 register ranges(address and length)
- interrupts : UHCI controller interrupt
usb: uhci@D8007301 {
compatible = "platform-uhci", "usb-uhci";
reg = <0xD8007301 0x200>;
interrupts = <0>;
};
Example:
uhci@d8007b00 {
compatible = "platform-uhci";
reg = <0xd8007b00 0x200>;
interrupts = <43>;
};
VIA/Wondermedia VT8500 EHCI Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-ehci"
- reg : Should contain 1 register ranges(address and length)
- interrupts : ehci controller interrupt
Example:
ehci@d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
interrupts = <43>;
};
......@@ -48,5 +48,7 @@ sirf SiRF Technology, Inc.
st STMicroelectronics
stericsson ST-Ericsson
ti Texas Instruments
via VIA Technologies, Inc.
wlf Wolfson Microelectronics
wm Wondermedia Technologies, Inc.
xlnx Xilinx
VIA VT8500 Framebuffer
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-fb"
- reg : Should contain 1 register ranges(address and length)
- interrupts : framebuffer controller interrupt
- display: a phandle pointing to the display node
Required nodes:
- display: a display node is required to initialize the lcd panel
This should be in the board dts.
- default-mode: a videomode within the display with timing parameters
as specified below.
Example:
fb@d800e400 {
compatible = "via,vt8500-fb";
reg = <0xd800e400 0x400>;
interrupts = <12>;
display = <&display>;
default-mode = <&mode0>;
};
VIA VT8500 Display
-----------------------------------------------------
Required properties (as per of_videomode_helper):
- hactive, vactive: Display resolution
- hfront-porch, hback-porch, hsync-len: Horizontal Display timing parameters
in pixels
vfront-porch, vback-porch, vsync-len: Vertical display timing parameters in
lines
- clock: displayclock in Hz
- bpp: lcd panel bit-depth.
<16> for RGB565, <32> for RGB888
Optional properties (as per of_videomode_helper):
- width-mm, height-mm: Display dimensions in mm
- hsync-active-high (bool): Hsync pulse is active high
- vsync-active-high (bool): Vsync pulse is active high
- interlaced (bool): This is an interlaced mode
- doublescan (bool): This is a doublescan mode
Example:
display: display@0 {
modes {
mode0: mode@0 {
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hfront-porch = <40>;
hsync-len = <0>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <1>;
clock = <0>; /* unused but required */
bpp = <16>; /* non-standard but required */
};
};
};
VIA/Wondermedia Graphics Engine Controller
-----------------------------------------------------
Required properties:
- compatible : "wm,prizm-ge-rops"
- reg : Should contain 1 register ranges(address and length)
Example:
ge_rops@d8050400 {
compatible = "wm,prizm-ge-rops";
reg = <0xd8050400 0x100>;
};
Wondermedia WM8505 Framebuffer
-----------------------------------------------------
Required properties:
- compatible : "wm,wm8505-fb"
- reg : Should contain 1 register ranges(address and length)
- via,display: a phandle pointing to the display node
Required nodes:
- display: a display node is required to initialize the lcd panel
This should be in the board dts. See definition in
Documentation/devicetree/bindings/video/via,vt8500-fb.txt
- default-mode: a videomode node as specified in
Documentation/devicetree/bindings/video/via,vt8500-fb.txt
Example:
fb@d8050800 {
compatible = "wm,wm8505-fb";
reg = <0xd8050800 0x200>;
display = <&display>;
default-mode = <&mode0>;
};
......@@ -1003,6 +1003,10 @@ config ARCH_VT8500
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select USE_OF
select COMMON_CLK
select HAVE_CLK
select CLKDEV_LOOKUP
help
Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
......@@ -1129,8 +1133,6 @@ source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/plat-versatile/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-w90x900/Kconfig"
# Definitions to make life easier
......@@ -1617,6 +1619,7 @@ config ARCH_NR_GPIO
default 355 if ARCH_U8500
default 264 if MACH_H4700
default 512 if SOC_OMAP5
default 288 if ARCH_VT8500
default 0
help
Maximum number of GPIOs in the system.
......
......@@ -17,4 +17,64 @@ memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
ocp {
uart1: serial@44e09000 {
status = "okay";
};
i2c1: i2c@44e0b000 {
status = "okay";
clock-frequency = <400000>;
tps: tps@24 {
reg = <0x24>;
};
};
};
};
/include/ "tps65217.dtsi"
&tps {
regulators {
dcdc1_reg: regulator@0 {
regulator-always-on;
};
dcdc2_reg: regulator@1 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1325000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3_reg: regulator@2 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
regulator-always-on;
};
ldo2_reg: regulator@4 {
regulator-always-on;
};
ldo3_reg: regulator@5 {
regulator-always-on;
};
ldo4_reg: regulator@6 {
regulator-always-on;
};
};
};
......@@ -17,4 +17,104 @@ memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
ocp {
uart1: serial@44e09000 {
status = "okay";
};
i2c1: i2c@44e0b000 {
status = "okay";
clock-frequency = <400000>;
tps: tps@2d {
reg = <0x2d>;
};
};
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
};
/include/ "tps65910.dtsi"
&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;
regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};
vio_reg: regulator@1 {
regulator-always-on;
};
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1312500>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: regulator@3 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
vdd3_reg: regulator@4 {
regulator-always-on;
};
vdig1_reg: regulator@5 {
regulator-always-on;
};
vdig2_reg: regulator@6 {
regulator-always-on;
};
vpll_reg: regulator@7 {
regulator-always-on;
};
vdac_reg: regulator@8 {
regulator-always-on;
};
vaux1_reg: regulator@9 {
regulator-always-on;
};
vaux2_reg: regulator@10 {
regulator-always-on;
};
vaux33_reg: regulator@11 {
regulator-always-on;
};
vmmc_reg: regulator@12 {
regulator-always-on;
};
};
};
......@@ -69,95 +69,146 @@ gpio1: gpio@44e07000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x44e07000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <96>;
};
gpio2: gpio@4804C000 {
gpio2: gpio@4804c000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x4804c000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <98>;
};
gpio3: gpio@481AC000 {
gpio3: gpio@481ac000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x481ac000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <32>;
};
gpio4: gpio@481AE000 {
gpio4: gpio@481ae000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x481ae000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <62>;
};
uart1: serial@44E09000 {
uart1: serial@44e09000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
reg = <0x44e09000 0x2000>;
interrupt-parent = <&intc>;
interrupts = <72>;
status = "disabled";
};
uart2: serial@48022000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
reg = <0x48022000 0x2000>;
interrupt-parent = <&intc>;
interrupts = <73>;
status = "disabled";
};
uart3: serial@48024000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
reg = <0x48024000 0x2000>;
interrupt-parent = <&intc>;
interrupts = <74>;
status = "disabled";
};
uart4: serial@481A6000 {
uart4: serial@481a6000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
reg = <0x481a6000 0x2000>;
interrupt-parent = <&intc>;
interrupts = <44>;
status = "disabled";
};
uart5: serial@481A8000 {
uart5: serial@481a8000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart5";
clock-frequency = <48000000>;
reg = <0x481a8000 0x2000>;
interrupt-parent = <&intc>;
interrupts = <45>;
status = "disabled";
};
uart6: serial@481AA000 {
uart6: serial@481aa000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart6";
clock-frequency = <48000000>;
reg = <0x481aa000 0x2000>;
interrupt-parent = <&intc>;
interrupts = <46>;
status = "disabled";
};
i2c1: i2c@44E0B000 {
i2c1: i2c@44e0b000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
reg = <0x44e0b000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <70>;
status = "disabled";
};
i2c2: i2c@4802A000 {
i2c2: i2c@4802a000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
reg = <0x4802a000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <71>;
status = "disabled";
};
i2c3: i2c@4819C000 {
i2c3: i2c@4819c000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
reg = <0x4819c000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <30>;
status = "disabled";
};
wdt2: wdt@44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
reg = <0x44e35000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <91>;
};
};
};
......@@ -194,6 +194,8 @@ prcmu@80157000 {
interrupts = <0 47 0x4>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
prcmu-timer-4@80157450 {
......@@ -330,6 +332,7 @@ db8500_esram34_ret_reg: db8500_esram34_ret {
ab8500@5 {
compatible = "stericsson,ab8500";
reg = <5>; /* mailbox 5 is i2c */
interrupt-parent = <&intc>;
interrupts = <0 40 0x4>;
interrupt-controller;
#interrupt-cells = <2>;
......@@ -371,7 +374,7 @@ ab8500-usb {
};
ab8500-ponkey {
compatible = "stericsson,ab8500-ponkey";
compatible = "stericsson,ab8500-poweron-key";
interrupts = <6 0x4
7 0x4>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
......@@ -389,6 +392,12 @@ ab8500-debugfs {
compatible = "stericsson,ab8500-debug";
};
codec: ab8500-codec {
compatible = "stericsson,ab8500-codec";
stericsson,earpeice-cmv = <950>; /* Units in mV. */
};
ab8500-regulators {
compatible = "stericsson,ab8500-regulator";
......@@ -471,48 +480,63 @@ ab8500_ldo_ana_reg: ab8500_ldo_ana {
};
i2c@80004000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80004000 0x1000>;
interrupts = <0 21 0x4>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
};
i2c@80122000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80122000 0x1000>;
interrupts = <0 22 0x4>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
};
i2c@80128000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80128000 0x1000>;
interrupts = <0 55 0x4>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
};
i2c@80110000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80110000 0x1000>;
interrupts = <0 12 0x4>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
};
i2c@8012a000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x8012a000 0x1000>;
interrupts = <0 51 0x4>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
clock-frequency = <400000>;
};
ssp@80002000 {
compatible = "arm,pl022", "arm,primecell";
reg = <80002000 0x1000>;
reg = <0x80002000 0x1000>;
interrupts = <0 14 0x4>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -580,6 +604,39 @@ sdi@80008000 {
status = "disabled";
};
msp0: msp@80123000 {
compatible = "stericsson,ux500-msp-i2s";
reg = <0x80123000 0x1000>;
interrupts = <0 31 0x4>;
v-ape-supply = <&db8500_vape_reg>;
status = "disabled";
};
msp1: msp@80124000 {
compatible = "stericsson,ux500-msp-i2s";
reg = <0x80124000 0x1000>;
interrupts = <0 62 0x4>;
v-ape-supply = <&db8500_vape_reg>;
status = "disabled";
};
// HDMI sound
msp2: msp@80117000 {
compatible = "stericsson,ux500-msp-i2s";
reg = <0x80117000 0x1000>;
interrupts = <0 98 0x4>;
v-ape-supply = <&db8500_vape_reg>;
status = "disabled";
};
msp3: msp@80125000 {
compatible = "stericsson,ux500-msp-i2s";
reg = <0x80125000 0x1000>;
interrupts = <0 62 0x4>;
v-ape-supply = <&db8500_vape_reg>;
status = "disabled";
};
external-bus@50000000 {
compatible = "simple-bus";
reg = <0x50000000 0x4000000>;
......
......@@ -166,9 +166,116 @@ gpio_keys {
#size-cells = <0>;
autorepeat;
button@21 {
label = "GPIO Key UP";
label = "Interrupt Key";
linux,code = <103>;
gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
};
key1 {
label = "KEY1";
linux,code = <1>;
gpios = <&pca9532 0 0>;
};
key2 {
label = "KEY2";
linux,code = <2>;
gpios = <&pca9532 1 0>;
};
key3 {
label = "KEY3";
linux,code = <3>;
gpios = <&pca9532 2 0>;
};
key4 {
label = "KEY4";
linux,code = <4>;
gpios = <&pca9532 3 0>;
};
joy0 {
label = "Joystick Key 0";
linux,code = <10>;
gpios = <&gpio 2 0 0>; /* P2.0 */
};
joy1 {
label = "Joystick Key 1";
linux,code = <11>;
gpios = <&gpio 2 1 0>; /* P2.1 */
};
joy2 {
label = "Joystick Key 2";
linux,code = <12>;
gpios = <&gpio 2 2 0>; /* P2.2 */
};
joy3 {
label = "Joystick Key 3";
linux,code = <13>;
gpios = <&gpio 2 3 0>; /* P2.3 */
};
joy4 {
label = "Joystick Key 4";
linux,code = <14>;
gpios = <&gpio 2 4 0>; /* P2.4 */
};
};
leds {
compatible = "gpio-leds";
/* LEDs on OEM Board */
led1 {
gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
linux,default-trigger = "timer";
default-state = "off";
};
led2 {
gpios = <&gpio 2 10 1>; /* P2.10, active low */
default-state = "off";
};
led3 {
gpios = <&gpio 2 11 1>; /* P2.11, active low */
default-state = "off";
};
led4 {
gpios = <&gpio 2 12 1>; /* P2.12, active low */
default-state = "off";
};
/* LEDs on Base Board */
lede1 {
gpios = <&pca9532 8 0>;
default-state = "off";
};
lede2 {
gpios = <&pca9532 9 0>;
default-state = "off";
};
lede3 {
gpios = <&pca9532 10 0>;
default-state = "off";
};
lede4 {
gpios = <&pca9532 11 0>;
default-state = "off";
};
lede5 {
gpios = <&pca9532 12 0>;
default-state = "off";
};
lede6 {
gpios = <&pca9532 13 0>;
default-state = "off";
};
lede7 {
gpios = <&pca9532 14 0>;
default-state = "off";
};
lede8 {
gpios = <&pca9532 15 0>;
default-state = "off";
};
};
};
/*
* Common devices used in different OMAP boards
*/
/ {
elpida_ECB240ABACN: lpddr2 {
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
tWR-min-tck = <3>;
tRASmin-min-tck = <3>;
tRRD-min-tck = <2>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tRTP-min-tck = <2>;
tCKE-min-tck = <3>;
tCKESR-min-tck = <3>;
tFAW-min-tck = <8>;
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
tDQSCK-max-derated = <6000>;
};
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <200000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <10000>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
tDQSCK-max-derated = <6000>;
};
};
};
/*
* Copyright 2012 ST-Ericsson AB
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "dbx5x0.dtsi"
/ {
model = "ST-Ericsson HREF platform with Device Tree";
compatible = "st-ericsson,hrefv60+";
memory {
reg = <0x00000000 0x20000000>;
};
soc-u9500 {
uart@80120000 {
status = "okay";
};
uart@80121000 {
status = "okay";
};
uart@80007000 {
status = "okay";
};
i2c@80004000 {
tc3589x@42 {
compatible = "tc3589x";
reg = <0x42>;
interrupt-parent = <&gpio6>;
interrupts = <25 0x1>;
interrupt-controller;
#interrupt-cells = <2>;
tc3589x_gpio: tc3589x_gpio {
compatible = "tc3589x-gpio";
interrupts = <0 0x1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
};
tps61052@33 {
compatible = "tps61052";
reg = <0x33>;
};
};
i2c@80128000 {
lp5521@0x33 {
compatible = "lp5521";
reg = <0x33>;
};
lp5521@0x34 {
compatible = "lp5521";
reg = <0x34>;
};
bh1780@0x29 {
compatible = "rohm,bh1780gli";
reg = <0x33>;
};
};
sound {
compatible = "stericsson,snd-soc-mop500";
stericsson,cpu-dai = <&msp1 &msp3>;
stericsson,audio-codec = <&codec>;
};
msp1: msp@80124000 {
status = "okay";
};
msp3: msp@80125000 {
status = "okay";
};
};
};
......@@ -42,12 +42,13 @@ pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog-gpios@0 {
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
......
......@@ -31,6 +31,22 @@ ssp0: ssp@80010000 {
bus-width = <4>;
status = "okay";
};
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
};
};
apbx@80040000 {
......@@ -39,6 +55,47 @@ duart: serial@80070000 {
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
auart0: serial@8006c000 {
pinctrl-names = "default";
pinctrl-0 = <&auart0_2pins_a>;
status = "okay";
};
usbphy0: usbphy@8007c000 {
status = "okay";
};
};
};
ahb@80080000 {
usb0: usb@80080000 {
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
};
regulators {
compatible = "simple-bus";
reg_usb0_vbus: usb0_vbus {
compatible = "regulator-fixed";
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
gpio = <&gpio0 17 0>;
};
};
leds {
compatible = "gpio-leds";
user {
label = "green";
gpios = <&gpio2 1 0>;
linux,default-trigger = "default-on";
};
};
};
......@@ -36,7 +36,7 @@ pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog-gpios@0 {
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
......
......@@ -52,6 +52,7 @@ icoll: interrupt-controller@80000000 {
dma-apbh@80004000 {
compatible = "fsl,imx23-dma-apbh";
reg = <0x80004000 0x2000>;
clocks = <&clks 15>;
};
ecc@80008000 {
......@@ -67,6 +68,7 @@ gpmi-nand@8000c000 {
reg-names = "gpmi-nand", "bch";
interrupts = <13>, <56>;
interrupt-names = "gpmi-dma", "bch";
clocks = <&clks 34>;
fsl,gpmi-dma-channel = <4>;
status = "disabled";
};
......@@ -74,6 +76,7 @@ gpmi-nand@8000c000 {
ssp0: ssp@80010000 {
reg = <0x80010000 0x2000>;
interrupts = <15 14>;
clocks = <&clks 33>;
fsl,ssp-dma-channel = <1>;
status = "disabled";
};
......@@ -140,6 +143,17 @@ auart0_pins_a: auart0@0 {
fsl,pull-up = <0>;
};
auart0_2pins_a: auart0-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
gpmi_pins_a: gpmi-nand@0 {
reg = <0>;
fsl,pinmux-ids = <
......@@ -183,7 +197,6 @@ mmc0_4bit_pins_a: mmc0-4bit@0 {
0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
>;
fsl,drive-strength = <1>;
......@@ -280,6 +293,7 @@ emi@80020000 {
dma-apbx@80024000 {
compatible = "fsl,imx23-dma-apbx";
reg = <0x80024000 0x2000>;
clocks = <&clks 16>;
};
dcp@80028000 {
......@@ -306,12 +320,14 @@ lcdif@80030000 {
compatible = "fsl,imx23-lcdif";
reg = <0x80030000 2000>;
interrupts = <46 45>;
clocks = <&clks 38>;
status = "disabled";
};
ssp1: ssp@80034000 {
reg = <0x80034000 0x2000>;
interrupts = <2 20>;
clocks = <&clks 33>;
fsl,ssp-dma-channel = <2>;
status = "disabled";
};
......@@ -329,9 +345,10 @@ apbx@80040000 {
reg = <0x80040000 0x40000>;
ranges;
clkctl@80040000 {
clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
status = "disabled";
#clock-cells = <1>;
};
saif0: saif@80042000 {
......@@ -383,6 +400,7 @@ rtc@8005c000 {
pwm: pwm@80064000 {
compatible = "fsl,imx23-pwm";
reg = <0x80064000 0x2000>;
clocks = <&clks 30>;
#pwm-cells = <2>;
fsl,pwm-number = <5>;
status = "disabled";
......@@ -397,6 +415,7 @@ auart0: serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
status = "disabled";
};
......@@ -404,6 +423,7 @@ auart1: serial@8006e000 {
compatible = "fsl,imx23-auart";
reg = <0x8006e000 0x2000>;
interrupts = <59 60 58>;
clocks = <&clks 32>;
status = "disabled";
};
......@@ -411,11 +431,15 @@ duart: serial@80070000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80070000 0x2000>;
interrupts = <0>;
clocks = <&clks 32>, <&clks 16>;
clock-names = "uart", "apb_pclk";
status = "disabled";
};
usbphy@8007c000 {
usbphy0: usbphy@8007c000 {
compatible = "fsl,imx23-usbphy";
reg = <0x8007c000 0x2000>;
clocks = <&clks 41>;
status = "disabled";
};
};
......@@ -428,8 +452,12 @@ ahb@80080000 {
reg = <0x80080000 0x80000>;
ranges;
usbctrl@80080000 {
usb0: usb@80080000 {
compatible = "fsl,imx23-usb", "fsl,imx27-usb";
reg = <0x80080000 0x40000>;
interrupts = <11>;
fsl,usbphy = <&usbphy0>;
clocks = <&clks 40>;
status = "disabled";
};
};
......
......@@ -23,10 +23,6 @@ memory {
soc {
aipi@10000000 { /* aipi */
wdog@10002000 {
status = "okay";
};
serial@1000a000 {
fsl,uart-has-rtscts;
status = "okay";
......
......@@ -62,7 +62,6 @@ wdog@10002000 {
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
reg = <0x10002000 0x4000>;
interrupts = <27>;
status = "disabled";
};
uart1: serial@1000a000 {
......
......@@ -37,7 +37,7 @@ pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog-gpios@0 {
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
......
/*
* Copyright 2012 Free Electrons
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*
* The CFA-10049 is an expansion board for the CFA-10036 module, thus we
* need to include the CFA-10036 DTS.
*/
/include/ "imx28-cfa10036.dts"
/ {
model = "Crystalfontz CFA-10049 Board";
compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
apb@80000000 {
apbh@80000000 {
pinctrl@80018000 {
spi3_pins_cfa10049: spi3-cfa10049@0 {
reg = <0>;
fsl,pinmux-ids = <
0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
};
ssp3: ssp@80016000 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins_cfa10049>;
status = "okay";
gpio5: gpio5@0 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
registers-number = <2>;
spi-max-frequency = <100000>;
};
gpio6: gpio6@1 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <1>;
registers-number = <4>;
spi-max-frequency = <100000>;
};
};
};
apbx@80040000 {
i2c1: i2c@8005a000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
usbphy1: usbphy@8007e000 {
status = "okay";
};
};
};
ahb@80080000 {
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-0 = <&usbphy1_pins_a>;
pinctrl-names = "default";
status = "okay";
};
};
regulators {
compatible = "simple-bus";
reg_usb1_vbus: usb1_vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 7 1>;
};
};
};
......@@ -46,11 +46,28 @@ ssp1: ssp@80012000 {
wp-gpios = <&gpio0 28 0>;
};
ssp2: ssp@80014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf016b";
spi-max-frequency = <40000000>;
reg = <0>;
};
};
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog-gpios@0 {
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
......@@ -128,6 +145,10 @@ saif1: saif@80046000 {
status = "okay";
};
lradc@80050000 {
status = "okay";
};
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
......@@ -140,6 +161,12 @@ sgtl5000: codec@0a {
VDDIO-supply = <&reg_3p3v>;
};
at24@51 {
compatible = "at24,24c32";
pagesize = <32>;
reg = <0x51>;
};
};
pwm: pwm@80064000 {
......
......@@ -23,6 +23,8 @@ memory {
apb@80000000 {
apbh@80000000 {
gpmi-nand@8000c000 {
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
status = "okay";
......@@ -61,19 +63,40 @@ ssp0: ssp@80010000 {
&mmc0_cd_cfg
&mmc0_sck_cfg>;
bus-width = <8>;
wp-gpios = <&gpio3 10 1>;
wp-gpios = <&gpio3 10 0>;
vmmc-supply = <&reg_vddio_sd0>;
status = "okay";
};
ssp2: ssp@80014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
spi-max-frequency = <40000000>;
reg = <0>;
};
};
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog-gpios@0 {
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
......@@ -129,6 +152,7 @@ saif1: saif@80046000 {
i2c0: i2c@80058000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
clock-frequency = <400000>;
status = "okay";
sgtl5000: codec@0a {
......@@ -151,32 +175,51 @@ rtc: rtc@68 {
};
};
lradc@80050000 {
status = "okay";
};
duart: serial@80074000 {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
auart0: serial@8006a000 {
pinctrl-names = "default";
pinctrl-0 = <&auart0_2pins_a>;
usbphy0: usbphy@8007c000 {
status = "okay";
};
auart3: serial@80070000 {
usbphy1: usbphy@8007e000 {
status = "okay";
};
auart0: serial@8006a000 {
pinctrl-names = "default";
pinctrl-0 = <&auart3_pins_a>;
pinctrl-0 = <&auart0_2pins_a>;
status = "okay";
};
};
};
ahb@80080000 {
usb0: usb@80080000 {
vbus-supply = <&reg_usb0_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&usbphy0_pins_a>;
status = "okay";
};
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&usbphy1_pins_a>;
status = "okay";
};
mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-reset-gpios = <&gpio3 11 0>;
status = "okay";
};
......@@ -198,6 +241,30 @@ reg_3p3v: 3p3v {
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vddio_sd0: vddio-sd0 {
compatible = "regulator-fixed";
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 28 0>;
};
reg_usb0_vbus: usb0_vbus {
compatible = "regulator-fixed";
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 12 0>;
};
reg_usb1_vbus: usb1_vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 13 0>;
};
};
sound {
......
......@@ -25,7 +25,7 @@ pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog-gpios@0 {
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
......@@ -34,6 +34,24 @@ hog_pins_a: hog-gpios@0 {
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
mac0_pins_gpio: mac0-gpio-mode@0 {
reg = <0>;
fsl,pinmux-ids = <
0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
};
};
......@@ -72,8 +90,9 @@ auart1: serial@8006c000 {
ahb@80080000 {
mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-names = "default", "gpio_mode";
pinctrl-0 = <&mac0_pins_a>;
pinctrl-1 = <&mac0_pins_gpio>;
status = "okay";
};
};
......
......@@ -27,6 +27,8 @@ aliases {
serial2 = &auart2;
serial3 = &auart3;
serial4 = &auart4;
ethernet0 = &mac0;
ethernet1 = &mac1;
};
cpus {
......@@ -65,6 +67,7 @@ hsadc@80002000 {
dma-apbh@80004000 {
compatible = "fsl,imx28-dma-apbh";
reg = <0x80004000 0x2000>;
clocks = <&clks 25>;
};
perfmon@80006000 {
......@@ -81,34 +84,47 @@ gpmi-nand@8000c000 {
reg-names = "gpmi-nand", "bch";
interrupts = <88>, <41>;
interrupt-names = "gpmi-dma", "bch";
clocks = <&clks 50>;
fsl,gpmi-dma-channel = <4>;
status = "disabled";
};
ssp0: ssp@80010000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80010000 0x2000>;
interrupts = <96 82>;
clocks = <&clks 46>;
fsl,ssp-dma-channel = <0>;
status = "disabled";
};
ssp1: ssp@80012000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80012000 0x2000>;
interrupts = <97 83>;
clocks = <&clks 47>;
fsl,ssp-dma-channel = <1>;
status = "disabled";
};
ssp2: ssp@80014000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80014000 0x2000>;
interrupts = <98 84>;
clocks = <&clks 48>;
fsl,ssp-dma-channel = <2>;
status = "disabled";
};
ssp3: ssp@80016000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80016000 0x2000>;
interrupts = <99 85>;
clocks = <&clks 49>;
fsl,ssp-dma-channel = <3>;
status = "disabled";
};
......@@ -410,6 +426,28 @@ i2c0_pins_a: i2c0@0 {
fsl,pull-up = <1>;
};
i2c0_pins_b: i2c0@1 {
reg = <1>;
fsl,pinmux-ids = <
0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
i2c1_pins_a: i2c1@0 {
reg = <0>;
fsl,pinmux-ids = <
0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
saif0_pins_a: saif0@0 {
reg = <0>;
fsl,pinmux-ids = <
......@@ -453,6 +491,16 @@ pwm2_pins_a: pwm2@0 {
fsl,pull-up = <0>;
};
pwm4_pins_a: pwm4@0 {
reg = <0>;
fsl,pinmux-ids = <
0x31d0 /* MX28_PAD_PWM4__PWM_4 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
lcdif_24bit_pins_a: lcdif-24bit@0 {
reg = <0>;
fsl,pinmux-ids = <
......@@ -507,6 +555,49 @@ can1_pins_a: can1@0 {
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
spi2_pins_a: spi2@0 {
reg = <0>;
fsl,pinmux-ids = <
0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
usbphy0_pins_a: usbphy0@0 {
reg = <0>;
fsl,pinmux-ids = <
0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
>;
fsl,drive-strength = <2>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
usbphy0_pins_b: usbphy0@1 {
reg = <1>;
fsl,pinmux-ids = <
0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
>;
fsl,drive-strength = <2>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
usbphy1_pins_a: usbphy1@0 {
reg = <0>;
fsl,pinmux-ids = <
0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
>;
fsl,drive-strength = <2>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
};
digctl@8001c000 {
......@@ -523,6 +614,7 @@ etm@80022000 {
dma-apbx@80024000 {
compatible = "fsl,imx28-dma-apbx";
reg = <0x80024000 0x2000>;
clocks = <&clks 26>;
};
dcp@80028000 {
......@@ -551,6 +643,7 @@ lcdif@80030000 {
compatible = "fsl,imx28-lcdif";
reg = <0x80030000 0x2000>;
interrupts = <38 86>;
clocks = <&clks 55>;
status = "disabled";
};
......@@ -558,6 +651,8 @@ can0: can@80032000 {
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
reg = <0x80032000 0x2000>;
interrupts = <8>;
clocks = <&clks 58>, <&clks 58>;
clock-names = "ipg", "per";
status = "disabled";
};
......@@ -565,6 +660,8 @@ can1: can@80034000 {
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
reg = <0x80034000 0x2000>;
interrupts = <9>;
clocks = <&clks 59>, <&clks 59>;
clock-names = "ipg", "per";
status = "disabled";
};
......@@ -611,15 +708,17 @@ apbx@80040000 {
reg = <0x80040000 0x40000>;
ranges;
clkctl@80040000 {
clks: clkctrl@80040000 {
compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
status = "disabled";
#clock-cells = <1>;
};
saif0: saif@80042000 {
compatible = "fsl,imx28-saif";
reg = <0x80042000 0x2000>;
interrupts = <59 80>;
clocks = <&clks 53>;
fsl,saif-dma-channel = <4>;
status = "disabled";
};
......@@ -633,12 +732,16 @@ saif1: saif@80046000 {
compatible = "fsl,imx28-saif";
reg = <0x80046000 0x2000>;
interrupts = <58 81>;
clocks = <&clks 54>;
fsl,saif-dma-channel = <5>;
status = "disabled";
};
lradc@80050000 {
compatible = "fsl,imx28-lradc";
reg = <0x80050000 0x2000>;
interrupts = <10 14 15 16 17 18 19
20 21 22 23 24 25>;
status = "disabled";
};
......@@ -677,6 +780,7 @@ i2c1: i2c@8005a000 {
pwm: pwm@80064000 {
compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
reg = <0x80064000 0x2000>;
clocks = <&clks 44>;
#pwm-cells = <2>;
fsl,pwm-number = <8>;
status = "disabled";
......@@ -691,6 +795,7 @@ auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
clocks = <&clks 45>;
status = "disabled";
};
......@@ -698,6 +803,7 @@ auart1: serial@8006c000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <113 72 73>;
clocks = <&clks 45>;
status = "disabled";
};
......@@ -705,6 +811,7 @@ auart2: serial@8006e000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006e000 0x2000>;
interrupts = <114 74 75>;
clocks = <&clks 45>;
status = "disabled";
};
......@@ -712,6 +819,7 @@ auart3: serial@80070000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x80070000 0x2000>;
interrupts = <115 76 77>;
clocks = <&clks 45>;
status = "disabled";
};
......@@ -719,6 +827,7 @@ auart4: serial@80072000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x80072000 0x2000>;
interrupts = <116 78 79>;
clocks = <&clks 45>;
status = "disabled";
};
......@@ -726,18 +835,22 @@ duart: serial@80074000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80074000 0x1000>;
interrupts = <47>;
clocks = <&clks 45>, <&clks 26>;
clock-names = "uart", "apb_pclk";
status = "disabled";
};
usbphy0: usbphy@8007c000 {
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
reg = <0x8007c000 0x2000>;
clocks = <&clks 62>;
status = "disabled";
};
usbphy1: usbphy@8007e000 {
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
reg = <0x8007e000 0x2000>;
clocks = <&clks 63>;
status = "disabled";
};
};
......@@ -754,6 +867,7 @@ usb0: usb@80080000 {
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
reg = <0x80080000 0x10000>;
interrupts = <93>;
clocks = <&clks 60>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
};
......@@ -762,6 +876,7 @@ usb1: usb@80090000 {
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
reg = <0x80090000 0x10000>;
interrupts = <92>;
clocks = <&clks 61>;
fsl,usbphy = <&usbphy1>;
status = "disabled";
};
......@@ -775,6 +890,8 @@ mac0: ethernet@800f0000 {
compatible = "fsl,imx28-fec";
reg = <0x800f0000 0x4000>;
interrupts = <101>;
clocks = <&clks 57>, <&clks 57>;
clock-names = "ipg", "ahb";
status = "disabled";
};
......@@ -782,6 +899,8 @@ mac1: ethernet@800f4000 {
compatible = "fsl,imx28-fec";
reg = <0x800f4000 0x4000>;
interrupts = <102>;
clocks = <&clks 57>, <&clks 57>;
clock-names = "ipg", "ahb";
status = "disabled";
};
......
......@@ -25,23 +25,31 @@ soc {
aips@70000000 { /* aips-1 */
spba@70000000 {
esdhc@70004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
fsl,cd-controller;
fsl,wp-controller;
status = "okay";
};
esdhc@70008000 { /* ESDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio1 6 0>;
wp-gpios = <&gpio1 5 0>;
status = "okay";
};
uart3: serial@7000c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@70010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
status = "okay";
......@@ -169,31 +177,43 @@ ssi2: ssi@70014000 {
};
};
wdog@73f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@73fa8000 {
compatible = "fsl,imx51-iomuxc-babbage";
reg = <0x73fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
>;
};
};
};
uart1: serial@73fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
fsl,uart-has-rtscts;
status = "okay";
};
uart2: serial@73fc0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
};
aips@80000000 { /* aips-2 */
sdma@83fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
i2c@83fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
......@@ -206,10 +226,14 @@ sgtl5000: codec@0a {
};
audmux@83fd0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
ethernet@83fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "mii";
status = "okay";
};
......
......@@ -130,6 +130,34 @@ esdhc@70024000 { /* ESDHC4 */
};
};
usb@73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
usb@73f80200 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
usb@73f80400 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
usb@73f80600 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
status = "disabled";
};
gpio1: gpio@73f84000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f84000 0x4000>;
......@@ -174,7 +202,6 @@ wdog@73f98000 { /* WDOG1 */
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
status = "disabled";
};
wdog@73f9c000 { /* WDOG2 */
......@@ -184,6 +211,122 @@ wdog@73f9c000 { /* WDOG2 */
status = "disabled";
};
iomuxc@73fa8000 {
compatible = "fsl,imx51-iomuxc";
reg = <0x73fa8000 0x4000>;
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
>;
};
};
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
>;
};
};
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
>;
};
};
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
>;
};
};
};
uart1: serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
......@@ -219,6 +362,7 @@ sdma@83fb0000 {
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
cspi@83fc0000 {
......
......@@ -25,31 +25,66 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_2>;
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-ard";
reg = <0x53fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
};
};
eim-cs1@f4000000 {
......
......@@ -25,12 +25,16 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio3 14 0>;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
......@@ -56,32 +60,45 @@ partition@40000 {
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-evk";
reg = <0x53fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
pmic: mc13892@08 {
......@@ -96,6 +113,8 @@ codec: sgtl5000@0a {
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......
......@@ -25,6 +25,8 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
status = "okay";
};
......@@ -35,32 +37,46 @@ ssi2: ssi@50014000 {
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-qsb";
reg = <0x53fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
......@@ -72,6 +88,8 @@ sgtl5000: codec@0a {
};
i2c@63fc8000 { /* I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
......@@ -158,10 +176,14 @@ ldo13 {
};
audmux@63fd0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......
......@@ -25,22 +25,30 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio4 11 0>;
status = "okay";
};
esdhc@50008000 { /* ESDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
non-removable;
status = "okay";
};
uart3: serial@5000c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
......@@ -72,35 +80,49 @@ partition@40000 {
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
non-removable;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-smd";
reg = <0x53fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
uart2: serial@53fc0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
codec: sgtl5000@0a {
......@@ -120,6 +142,8 @@ touchkey: mpr121@5a {
};
i2c@63fc8000 { /* I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
......@@ -139,6 +163,8 @@ pmic: dialog@48 {
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......
......@@ -135,6 +135,34 @@ esdhc@50024000 { /* ESDHC4 */
};
};
usb@53f80000 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
usb@53f80200 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
usb@53f80400 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
usb@53f80600 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80600 0x0200>;
interrupts = <17>;
status = "disabled";
};
gpio1: gpio@53f84000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53f84000 0x4000>;
......@@ -179,7 +207,6 @@ wdog@53f98000 { /* WDOG1 */
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
status = "disabled";
};
wdog@53f9c000 { /* WDOG2 */
......@@ -189,6 +216,161 @@ wdog@53f9c000 { /* WDOG2 */
status = "disabled";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
>;
};
};
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
>;
};
pinctrl_esdhc1_2: esdhc1grp-2 {
fsl,pins = <
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
>;
};
};
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
>;
};
};
esdhc3 {
pinctrl_esdhc3_1: esdhc3grp-1 {
fsl,pins = <
943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
>;
};
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
>;
};
};
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
>;
};
};
};
uart1: serial@53fbc000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
......@@ -203,6 +385,20 @@ uart2: serial@53fc0000 {
status = "disabled";
};
can1: can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
status = "disabled";
};
can2: can@53fcc000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fcc000 0x4000>;
interrupts = <83>;
status = "disabled";
};
gpio5: gpio@53fdc000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53fdc000 0x4000>;
......@@ -277,6 +473,7 @@ sdma@63fb0000 {
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
cspi@63fc0000 {
......
......@@ -28,8 +28,27 @@ gpmi-nand@00112000 {
status = "disabled"; /* gpmi nand conflicts with SD */
};
aips-bus@02000000 { /* AIPS1 */
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_2>;
phy-mode = "rgmii";
status = "okay";
};
......@@ -52,6 +71,8 @@ usdhc@0219c000 { /* uSDHC4 */
};
uart4: serial@021f0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
status = "okay";
};
};
......
......@@ -46,15 +46,20 @@ ssi1: ssi@02028000 {
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_hog>;
pinctrl-0 = <&pinctrl_hog>;
gpios {
pinctrl_gpio_hog: gpiohog {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
>;
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
>;
};
};
};
......@@ -63,6 +68,9 @@ pinctrl_gpio_hog: gpiohog {
aips-bus@02100000 { /* AIPS2 */
usb@02184000 { /* USB OTG */
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_1>;
disable-over-current;
status = "okay";
};
......@@ -71,12 +79,16 @@ usb@02184200 { /* USB1 */
};
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
......@@ -84,6 +96,8 @@ usdhc@02198000 { /* uSDHC3 */
};
usdhc@0219c000 { /* uSDHC4 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_2>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <&reg_3p3v>;
......@@ -99,7 +113,7 @@ audmux@021d8000 {
uart2: serial@021e8000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2_1>;
pinctrl-0 = <&pinctrl_uart2_1>;
};
i2c@021a0000 { /* I2C1 */
......@@ -111,6 +125,7 @@ i2c@021a0000 { /* I2C1 */
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 169>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
......
......@@ -22,28 +22,51 @@ memory {
};
soc {
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
uart1: serial@02020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
status = "okay";
};
usdhc@02194000 { /* uSDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
......
This diff is collapsed.
......@@ -26,6 +26,11 @@ soc {
interrupt-parent = <&intc>;
ranges;
L2: l2-cache {
compatible = "marvell,tauros2-cache";
marvell,tauros2-cache-features = <0x3>;
};
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
......
......@@ -7,7 +7,7 @@ / {
compatible = "qcom,msm8660-surf", "qcom,msm8660";
interrupt-parent = <&intc>;
intc: interrupt-controller@02080000 {
intc: interrupt-controller@2080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
#interrupt-cells = <3>;
......@@ -15,6 +15,23 @@ intc: interrupt-controller@02080000 {
< 0x02081000 0x1000 >;
};
timer@2000004 {
compatible = "qcom,msm-gpt", "qcom,msm-timer";
interrupts = <1 1 0x301>;
reg = <0x02000004 0x10>;
clock-frequency = <32768>;
cpu-offset = <0x40000>;
};
timer@2000024 {
compatible = "qcom,msm-dgt", "qcom,msm-timer";
interrupts = <1 0 0x301>;
reg = <0x02000024 0x10>,
<0x02000034 0x4>;
clock-frequency = <6750000>;
cpu-offset = <0x40000>;
};
serial@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
......
/dts-v1/;
/include/ "skeleton.dtsi"
/ {
model = "Qualcomm MSM8960 CDP";
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
interrupt-parent = <&intc>;
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = < 0x02000000 0x1000 >,
< 0x02002000 0x1000 >;
};
timer@200a004 {
compatible = "qcom,msm-gpt", "qcom,msm-timer";
interrupts = <1 2 0x301>;
reg = <0x0200a004 0x10>;
clock-frequency = <32768>;
cpu-offset = <0x80000>;
};
timer@200a024 {
compatible = "qcom,msm-dgt", "qcom,msm-timer";
interrupts = <1 1 0x301>;
reg = <0x0200a024 0x10>,
<0x0200a034 0x4>;
clock-frequency = <6750000>;
cpu-offset = <0x80000>;
};
serial@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x16440000 0x1000>,
<0x16400000 0x1000>;
interrupts = <0 154 0x0>;
};
};
......@@ -7,7 +7,7 @@
*/
/dts-v1/;
/include/ "omap2.dtsi"
/include/ "omap2420.dtsi"
/ {
model = "TI OMAP2420 H4 board";
......
/*
* Device Tree Source for OMAP2420 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "omap2.dtsi"
/ {
compatible = "ti,omap2420", "ti,omap2";
ocp {
omap2420_pmx: pinmux@48000030 {
compatible = "ti,omap2420-padconf", "pinctrl-single";
reg = <0x48000030 0x0113>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
mcbsp1: mcbsp@48074000 {
compatible = "ti,omap2420-mcbsp";
reg = <0x48074000 0xff>;
reg-names = "mpu";
interrupts = <59>, /* TX interrupt */
<60>; /* RX interrupt */
interrupt-names = "tx", "rx";
interrupt-parent = <&intc>;
ti,hwmods = "mcbsp1";
};
mcbsp2: mcbsp@48076000 {
compatible = "ti,omap2420-mcbsp";
reg = <0x48076000 0xff>;
reg-names = "mpu";
interrupts = <62>, /* TX interrupt */
<63>; /* RX interrupt */
interrupt-names = "tx", "rx";
interrupt-parent = <&intc>;
ti,hwmods = "mcbsp2";
};
};
};
/*
* Device Tree Source for OMAP243x SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "omap2.dtsi"
/ {
compatible = "ti,omap2430", "ti,omap2";
ocp {
omap2430_pmx: pinmux@49002030 {
compatible = "ti,omap2430-padconf", "pinctrl-single";
reg = <0x49002030 0x0154>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
mcbsp1: mcbsp@48074000 {
compatible = "ti,omap2430-mcbsp";
reg = <0x48074000 0xff>;
reg-names = "mpu";
interrupts = <64>, /* OCP compliant interrupt */
<59>, /* TX interrupt */
<60>, /* RX interrupt */
<61>; /* RX overflow interrupt */
interrupt-names = "common", "tx", "rx", "rx_overflow";
interrupt-parent = <&intc>;
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
};
mcbsp2: mcbsp@48076000 {
compatible = "ti,omap2430-mcbsp";
reg = <0x48076000 0xff>;
reg-names = "mpu";
interrupts = <16>, /* OCP compliant interrupt */
<62>, /* TX interrupt */
<63>; /* RX interrupt */
interrupt-names = "common", "tx", "rx";
interrupt-parent = <&intc>;
ti,buffer-size = <128>;
ti,hwmods = "mcbsp2";
};
mcbsp3: mcbsp@4808c000 {
compatible = "ti,omap2430-mcbsp";
reg = <0x4808c000 0xff>;
reg-names = "mpu";
interrupts = <17>, /* OCP compliant interrupt */
<89>, /* TX interrupt */
<90>; /* RX interrupt */
interrupt-names = "common", "tx", "rx";
interrupt-parent = <&intc>;
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3";
};
mcbsp4: mcbsp@4808e000 {
compatible = "ti,omap2430-mcbsp";
reg = <0x4808e000 0xff>;
reg-names = "mpu";
interrupts = <18>, /* OCP compliant interrupt */
<54>, /* TX interrupt */
<55>; /* RX interrupt */
interrupt-names = "common", "tx", "rx";
interrupt-parent = <&intc>;
ti,buffer-size = <128>;
ti,hwmods = "mcbsp4";
};
mcbsp5: mcbsp@48096000 {
compatible = "ti,omap2430-mcbsp";
reg = <0x48096000 0xff>;
reg-names = "mpu";
interrupts = <19>, /* OCP compliant interrupt */
<81>, /* TX interrupt */
<82>; /* RX interrupt */
interrupt-names = "common", "tx", "rx";
interrupt-parent = <&intc>;
ti,buffer-size = <128>;
ti,hwmods = "mcbsp5";
};
};
};
......@@ -7,16 +7,44 @@
*/
/dts-v1/;
/include/ "omap3.dtsi"
/include/ "omap36xx.dtsi"
/ {
model = "TI OMAP3 BeagleBoard";
compatible = "ti,omap3-beagle", "ti,omap3";
model = "TI OMAP3 BeagleBoard xM";
compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
leds {
compatible = "gpio-leds";
pmu_stat {
label = "beagleboard::pmu_stat";
gpios = <&twl_gpio 19 0>; /* LEDB */
};
heartbeat {
label = "beagleboard::usr0";
gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
linux,default-trigger = "heartbeat";
};
mmc {
label = "beagleboard::usr1";
gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
linux,default-trigger = "mmc0";
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "omap3beagle";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
};
&i2c1 {
......@@ -27,11 +55,17 @@ twl: twl@48 {
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
vsim: regulator@10 {
vsim: regulator-vsim {
compatible = "ti,twl4030-vsim";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
......@@ -67,3 +101,15 @@ &mmc2 {
&mmc3 {
status = "disabled";
};
&twl_gpio {
ti,use-leds;
/* pullups: BIT(1) */
ti,pullups = <0x000002>;
/*
* pulldowns:
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
* BIT(15), BIT(16), BIT(17)
*/
ti,pulldowns = <0x03a1c4>;
};
......@@ -17,6 +17,15 @@ memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
leds {
compatible = "gpio-leds";
ledb {
label = "omap3evm::ledb";
gpios = <&twl_gpio 19 0>; /* LEDB */
linux,default-trigger = "default-on";
};
};
};
&i2c1 {
......@@ -46,3 +55,7 @@ tvp5146@5c {
reg = <0x5c>;
};
};
&twl_gpio {
ti,use-leds;
};
/*
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* The Gumstix Overo must be combined with an expansion board.
*/
/dts-v1/;
/include/ "omap3.dtsi"
/ {
leds {
compatible = "gpio-leds";
overo {
label = "overo:blue:COM";
gpios = <&twl_gpio 19 0>;
linux,default-trigger = "mmc0";
};
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
};
};
/include/ "twl4030.dtsi"
/* i2c2 pins are used for gpio */
&i2c2 {
status = "disabled";
};
/* on board microSD slot */
&mmc1 {
vmmc-supply = <&vmmc1>;
bus-width = <4>;
};
/* optional on board WiFi */
&mmc2 {
bus-width = <4>;
};
&twl_gpio {
ti,use-leds;
};
/*
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Tobi expansion board is manufactured by Gumstix Inc.
*/
/include/ "omap3-overo.dtsi"
/ {
model = "TI OMAP3 Gumstix Overo on Tobi";
compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
leds {
compatible = "gpio-leds";
heartbeat {
label = "overo:red:gpio21";
gpios = <&gpio1 21 0>;
linux,default-trigger = "heartbeat";
};
};
};
&i2c3 {
clock-frequency = <100000>;
};
&mmc3 {
status = "disabled";
};
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/*
* Device Tree Source for OMAP3 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "omap3.dtsi"
/ {
aliases {
serial3 = &uart4;
};
ocp {
uart4: serial@49042000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};
};
};
......@@ -8,6 +8,7 @@
/dts-v1/;
/include/ "omap4.dtsi"
/include/ "elpida_ecb240abacn.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
......@@ -126,3 +127,13 @@ &mmc5 {
ti,non-removable;
bus-width = <4>;
};
&emif1 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&emif2 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
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......@@ -25,6 +25,11 @@ soc {
interrupt-parent = <&intc>;
ranges;
L2: l2-cache {
compatible = "marvell,tauros2-cache";
marvell,tauros2-cache-features = <0x3>;
};
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
......
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