Commit 2b35050a authored by Ryder Lee's avatar Ryder Lee Committed by Felix Fietkau

mt76: mt7915: fix mib stats counter reporting to mac80211

In order to properly report MIB counters to mac80211, resets stats in
mt7915_get_stats routine() and hold mt76 mutex accessing MIB counters.
Sum up MIB counters in mt7915_mac_update_mib_stats routine.

Fixes: e57b7901 ("mt76: add mac80211 driver for MT7915 PCIe-based chipsets")
Signed-off-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 2eb6f6c4
...@@ -1678,39 +1678,30 @@ mt7915_mac_update_mib_stats(struct mt7915_phy *phy) ...@@ -1678,39 +1678,30 @@ mt7915_mac_update_mib_stats(struct mt7915_phy *phy)
bool ext_phy = phy != &dev->phy; bool ext_phy = phy != &dev->phy;
int i, aggr0, aggr1; int i, aggr0, aggr1;
memset(mib, 0, sizeof(*mib)); mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
MT_MIB_SDR3_FCS_ERR_MASK);
mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
MT_MIB_SDR3_FCS_ERR_MASK);
aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) { for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) {
u32 val, val2; u32 val;
val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); mib->ack_fail_cnt +=
if (val2 > mib->ack_fail_cnt) FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
mib->ack_fail_cnt = val2;
val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
if (val2 > mib->ba_miss_cnt)
mib->ba_miss_cnt = val2;
val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
if (val2 > mib->rts_retries_cnt) { mib->rts_retries_cnt +=
mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
mib->rts_retries_cnt = val2;
}
val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
val2 = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
dev->mt76.aggr_stats[aggr0++] += val & 0xffff; dev->mt76.aggr_stats[aggr0++] += val & 0xffff;
dev->mt76.aggr_stats[aggr0++] += val >> 16; dev->mt76.aggr_stats[aggr0++] += val >> 16;
dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff;
dev->mt76.aggr_stats[aggr1++] += val2 >> 16; val = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
dev->mt76.aggr_stats[aggr1++] += val & 0xffff;
dev->mt76.aggr_stats[aggr1++] += val >> 16;
} }
} }
......
...@@ -717,13 +717,19 @@ mt7915_get_stats(struct ieee80211_hw *hw, ...@@ -717,13 +717,19 @@ mt7915_get_stats(struct ieee80211_hw *hw,
struct ieee80211_low_level_stats *stats) struct ieee80211_low_level_stats *stats)
{ {
struct mt7915_phy *phy = mt7915_hw_phy(hw); struct mt7915_phy *phy = mt7915_hw_phy(hw);
struct mt7915_dev *dev = mt7915_hw_dev(hw);
struct mib_stats *mib = &phy->mib; struct mib_stats *mib = &phy->mib;
mutex_lock(&dev->mt76.mutex);
stats->dot11RTSSuccessCount = mib->rts_cnt; stats->dot11RTSSuccessCount = mib->rts_cnt;
stats->dot11RTSFailureCount = mib->rts_retries_cnt; stats->dot11RTSFailureCount = mib->rts_retries_cnt;
stats->dot11FCSErrorCount = mib->fcs_err_cnt; stats->dot11FCSErrorCount = mib->fcs_err_cnt;
stats->dot11ACKFailureCount = mib->ack_fail_cnt; stats->dot11ACKFailureCount = mib->ack_fail_cnt;
memset(mib, 0, sizeof(*mib));
mutex_unlock(&dev->mt76.mutex);
return 0; return 0;
} }
......
...@@ -108,11 +108,11 @@ struct mt7915_vif { ...@@ -108,11 +108,11 @@ struct mt7915_vif {
}; };
struct mib_stats { struct mib_stats {
u16 ack_fail_cnt; u32 ack_fail_cnt;
u16 fcs_err_cnt; u32 fcs_err_cnt;
u16 rts_cnt; u32 rts_cnt;
u16 rts_retries_cnt; u32 rts_retries_cnt;
u16 ba_miss_cnt; u32 ba_miss_cnt;
}; };
struct mt7915_hif { struct mt7915_hif {
......
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