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Commit 2c2a5564 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-arm-dt-for-v5.9-tag2' of... 

Merge tag 'renesas-arm-dt-for-v5.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.9 (take two)

  - SPI Multi I/O Bus Controller (RPC-IF) support for R-Car V3H and V3M,
    including QSPI support for the Condor, Eagle, V3HSK, and V3MSK
    boards,
  - Initial support for the RZ/G2H SoC on the HopeRun HiHope RZ/G2H
    board,
  - Initial support for the Beacon EmbeddedWorks RZ/G2M board,
  - Minor fixes and improvements.

* tag 'renesas-arm-dt-for-v5.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
  ARM: dts: sh73a0: Add missing clocks to sound node
  arm64: dts: renesas: r8a774e1: Add CAN[FD] support
  arm64: dts: renesas: r8a774e1: Add RWDT node
  arm64: dts: renesas: r8a774e1: Add MSIOF nodes
  arm64: dts: renesas: r8a774e1: Add I2C and IIC-DVFS support
  arm64: dts: renesas: r8a774e1: Add SDHI nodes
  arm64: dts: renesas: r8a774e1: Add SCIF and HSCIF nodes
  arm64: dts: renesas: r8a774e1: Add TMU device nodes
  arm64: dts: renesas: r8a774e1: Add CMT device nodes
  arm64: dts: renesas: r8a774e1: Add RZ/G2H thermal support
  arm64: dts: renesas: r8a774e1: Add operating points
  arm64: dts: renesas: Introduce r8a774a1-beacon-rzg2m-kit
  arm64: dts: renesas: r8a774e1: Add Ethernet AVB node
  arm64: dts: renesas: r8a774e1: Add GPIO device nodes
  arm64: dts: renesas: r8a774e1: Add SYS-DMAC device nodes
  arm64: dts: renesas: r8a774e1: Add IPMMU device nodes
  ARM: dts: gose: Fix ports node name for adv7612
  ARM: dts: renesas: Fix SD Card/eMMC interface device node names
  arm64: dts: renesas: Fix SD Card/eMMC interface device node names
  arm64: dts: renesas: add full-pwr-cycle-in-suspend into eMMC nodes
  ...

Link: https://lore.kernel.org/r/20200717112427.26032-2-geert+renesas@glider.beSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 39a85f6d 8aa937cb
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Showing with 3342 additions and 119 deletions
arch/arm/boot/dts/r7s72100.dtsi
View file @ 2c2a5564
......@@ -323,7 +323,7 @@ mmcif: mmc@e804c800 {
status = "disabled";
};
sdhi0: sd@e804e000 {
sdhi0: mmc@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
......@@ -339,7 +339,7 @@ sdhi0: sd@e804e000 {
status = "disabled";
};
sdhi1: sd@e804e800 {
sdhi1: mmc@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
......
arch/arm/boot/dts/r7s9210.dtsi
View file @ 2c2a5564
......@@ -416,7 +416,7 @@ usbhs1: usb@e821b000 {
status = "disabled";
};
sdhi0: sd@e8228000 {
sdhi0: mmc@e8228000 {
compatible = "renesas,sdhi-r7s9210";
reg = <0xe8228000 0x8c0>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
......@@ -428,7 +428,7 @@ sdhi0: sd@e8228000 {
status = "disabled";
};
sdhi1: sd@e822a000 {
sdhi1: mmc@e822a000 {
compatible = "renesas,sdhi-r7s9210";
reg = <0xe822a000 0x8c0>;
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm/boot/dts/r8a73a4.dtsi
View file @ 2c2a5564
......@@ -409,7 +409,7 @@ scifb3: serial@e6cf0000 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee100000 0 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
......@@ -419,7 +419,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee120000 0 0x100>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
......@@ -429,7 +429,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm/boot/dts/r8a7740.dtsi
View file @ 2c2a5564
......@@ -349,7 +349,7 @@ mmcif0: mmc@e6bd0000 {
status = "disabled";
};
sdhi0: sd@e6850000 {
sdhi0: mmc@e6850000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6850000 0x100>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
......@@ -362,7 +362,7 @@ sdhi0: sd@e6850000 {
status = "disabled";
};
sdhi1: sd@e6860000 {
sdhi1: mmc@e6860000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6860000 0x100>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
......@@ -375,7 +375,7 @@ sdhi1: sd@e6860000 {
status = "disabled";
};
sdhi2: sd@e6870000 {
sdhi2: mmc@e6870000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6870000 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
......
arch/arm/boot/dts/r8a7742.dtsi
View file @ 2c2a5564
......@@ -1286,7 +1286,7 @@ usb@2,0 {
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -1301,7 +1301,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
......@@ -1316,7 +1316,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
......@@ -1331,7 +1331,7 @@ sdhi2: sd@ee140000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7742",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
......
arch/arm/boot/dts/r8a7743.dtsi
View file @ 2c2a5564
......@@ -1520,7 +1520,7 @@ usb@2,0 {
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -1535,7 +1535,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
......@@ -1550,7 +1550,7 @@ sdhi1: sd@ee140000 {
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
......
arch/arm/boot/dts/r8a7744.dtsi
View file @ 2c2a5564
......@@ -1520,7 +1520,7 @@ usb@2,0 {
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -1535,7 +1535,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
......@@ -1550,7 +1550,7 @@ sdhi1: sd@ee140000 {
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
......
arch/arm/boot/dts/r8a7745.dtsi
View file @ 2c2a5564
......@@ -1396,7 +1396,7 @@ usb@2,0 {
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -1411,7 +1411,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
......@@ -1426,7 +1426,7 @@ sdhi1: sd@ee140000 {
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
......
arch/arm/boot/dts/r8a77470.dtsi
View file @ 2c2a5564
......@@ -882,7 +882,7 @@ usb2_phy1: usb-phy@ee0c0200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77470",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -897,7 +897,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee300000 {
sdhi1: mmc@ee300000 {
compatible = "renesas,sdhi-mmc-r8a77470";
reg = <0 0xee300000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
......@@ -908,7 +908,7 @@ sdhi1: sd@ee300000 {
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77470",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x328>;
......
arch/arm/boot/dts/r8a7778.dtsi
View file @ 2c2a5564
......@@ -401,7 +401,7 @@ mmcif: mmc@ffe4e000 {
status = "disabled";
};
sdhi0: sd@ffe4c000 {
sdhi0: mmc@ffe4c000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
......@@ -411,7 +411,7 @@ sdhi0: sd@ffe4c000 {
status = "disabled";
};
sdhi1: sd@ffe4d000 {
sdhi1: mmc@ffe4d000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
......@@ -421,7 +421,7 @@ sdhi1: sd@ffe4d000 {
status = "disabled";
};
sdhi2: sd@ffe4f000 {
sdhi2: mmc@ffe4f000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;
......
arch/arm/boot/dts/r8a7779.dtsi
View file @ 2c2a5564
......@@ -385,7 +385,7 @@ sata: sata@fc600000 {
status = "disabled";
};
sdhi0: sd@ffe4c000 {
sdhi0: mmc@ffe4c000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
......@@ -395,7 +395,7 @@ sdhi0: sd@ffe4c000 {
status = "disabled";
};
sdhi1: sd@ffe4d000 {
sdhi1: mmc@ffe4d000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
......@@ -405,7 +405,7 @@ sdhi1: sd@ffe4d000 {
status = "disabled";
};
sdhi2: sd@ffe4e000 {
sdhi2: mmc@ffe4e000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4e000 0x100>;
......@@ -415,7 +415,7 @@ sdhi2: sd@ffe4e000 {
status = "disabled";
};
sdhi3: sd@ffe4f000 {
sdhi3: mmc@ffe4f000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;
......
arch/arm/boot/dts/r8a7790-lager.dts
View file @ 2c2a5564
......@@ -343,7 +343,6 @@ ak4643: codec@12 {
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
......
arch/arm/boot/dts/r8a7790.dtsi
View file @ 2c2a5564
......@@ -1467,7 +1467,7 @@ usb@2,0 {
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -1482,7 +1482,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
......@@ -1497,7 +1497,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
......@@ -1512,7 +1512,7 @@ sdhi2: sd@ee140000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
......
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ 2c2a5564
......@@ -366,7 +366,6 @@ ak4643: codec@12 {
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
......
arch/arm/boot/dts/r8a7791-porter.dts
View file @ 2c2a5564
......@@ -162,7 +162,6 @@ ak4642: codec@12 {
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ 2c2a5564
......@@ -1563,7 +1563,7 @@ usb@2,0 {
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -1578,7 +1578,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
......@@ -1593,7 +1593,7 @@ sdhi1: sd@ee140000 {
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
......
arch/arm/boot/dts/r8a7792.dtsi
View file @ 2c2a5564
......@@ -780,7 +780,7 @@ vin5: video@e6ef5000 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7792",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......
arch/arm/boot/dts/r8a7793-gose.dts
View file @ 2c2a5564
......@@ -334,9 +334,8 @@ ak4643: codec@12 {
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
remote = <&vin1>;
port {
ports {
#address-cells = <1>;
#size-cells = <0>;
......@@ -394,7 +393,7 @@ hdmi-in@4c {
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
port {
ports {
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm/boot/dts/r8a7793.dtsi
View file @ 2c2a5564
......@@ -1227,7 +1227,7 @@ audma1: dma-controller@ec720000 {
dma-channels = <13>;
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -1242,7 +1242,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
......@@ -1257,7 +1257,7 @@ sdhi1: sd@ee140000 {
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
......
arch/arm/boot/dts/r8a7794-alt.dts
View file @ 2c2a5564
......@@ -167,7 +167,6 @@ i2chdmi: i2c-11 {
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
......
arch/arm/boot/dts/r8a7794-silk.dts
View file @ 2c2a5564
......@@ -236,7 +236,6 @@ ak4643: codec@12 {
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
......
arch/arm/boot/dts/r8a7794.dtsi
View file @ 2c2a5564
......@@ -1232,7 +1232,7 @@ usb@2,0 {
};
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
......@@ -1247,7 +1247,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee140000 {
sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
......@@ -1262,7 +1262,7 @@ sdhi1: sd@ee140000 {
status = "disabled";
};
sdhi2: sd@ee160000 {
sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
......
arch/arm/boot/dts/sh73a0.dtsi
View file @ 2c2a5564
......@@ -321,7 +321,7 @@ msiof3: spi@e6c90000 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee100000 0x100>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
......@@ -334,7 +334,7 @@ sdhi0: sd@ee100000 {
};
/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee120000 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
......@@ -346,7 +346,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee140000 0x100>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
......@@ -584,6 +584,7 @@ sh_fsi2: sound@ec230000 {
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
reg = <0xec230000 0x400>;
interrupts = <GIC_SPI 146 0x4>;
clocks = <&mstp3_clks SH73A0_CLK_FSI>;
power-domains = <&pd_a4mp>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/Makefile
View file @ 2c2a5564
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb \
r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb \
r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb \
r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb \
r8a774b1-hihope-rzg2n-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb \
r8a774b1-hihope-rzg2n-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb \
r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \
r8a774c0-ek874-idk-2121wr.dtb \
r8a774c0-ek874-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-idk-2121wr.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb r8a77951-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb r8a77960-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb r8a77960-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb r8a77965-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi 0 → 100644
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
power-supply = <&reg_lcd>;
enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_LOW>;
pwms = <&pwm2 0 50000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
backlight_rgb: backlight-rgb {
compatible = "pwm-backlight";
power-supply = <&reg_lcd>;
enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>;
pwms = <&pwm0 0 50000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
hdmi0-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi0_con: endpoint {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
};
};
keys {
compatible = "gpio-keys";
key-1 {
gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "Switch-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "Switch-2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "Switch-3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "Switch-4";
wakeup-source;
debounce-interval = <20>;
};
key-5 {
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_5>;
label = "Switch-4";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led0 {
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
label = "LED0";
linux,default-trigger = "heartbeat";
};
led1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
label = "LED1";
};
led2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
label = "LED2";
};
led3 {
gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
label = "LED3";
};
};
lvds {
compatible = "panel-lvds";
power-supply = <&reg_lcd_reset>;
width-mm = <223>;
height-mm = <125>;
backlight = <&backlight_lvds>;
data-mapping = "vesa-24";
panel-timing {
/* 800x480@60Hz */
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hsync-len = <48>;
hfront-porch = <40>;
hback-porch = <40>;
vfront-porch = <13>;
vback-porch = <29>;
vsync-len = <3>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
rgb {
/* Different LCD with compatible timings */
compatible = "rocktech,rk070er9427";
backlight = <&backlight_rgb>;
enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_lcd>;
port {
rgb_panel: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
};
reg_audio: regulator_audio {
compatible = "regulator-fixed";
regulator-name = "audio-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "lcd_panel_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lcd_reset: regulator-lcd-reset {
compatible = "regulator-fixed";
regulator-name = "nLCD_RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_lcd>;
};
reg_cam0: regulator_camera {
compatible = "regulator-fixed";
regulator-name = "reg_cam0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp2 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_cam1: regulator_camera {
compatible = "regulator-fixed";
regulator-name = "reg_cam1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
};
sound_card {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port0>, <&rsnd_port1>;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
regulator-always-on;
};
/* External DU dot clocks */
x302_clk: x302-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33000000>;
};
x304_clk: x304-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
&audio_clk_a {
clock-frequency = <24576000>;
assigned-clocks = <&versaclock6_bb 4>;
assigned-clock-rates = <24576000>;
};
&audio_clk_b {
clock-frequency = <22579200>;
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
renesas,can-clock-select = <0x0>;
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
renesas,can-clock-select = <0x0>;
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
&du_out_rgb {
remote-endpoint = <&rgb_panel>;
};
&ehci0 {
dr_mode = "otg";
status = "okay";
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
};
&ehci1 {
status = "okay";
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
};
&hdmi0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi0_in: endpoint {
remote-endpoint = <&du_out_hdmi0>;
};
};
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
};
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
gpio_exp2: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_exp3: gpio@22 {
compatible = "onnn,pca9654";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_exp4: gpio@23 {
compatible = "onnn,pca9654";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
versaclock6_bb: clock-controller@6a {
compatible = "idt,5p49v6965";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
/* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */
assigned-clocks = <&versaclock6_bb 1>,
<&versaclock6_bb 2>,
<&versaclock6_bb 3>,
<&versaclock6_bb 4>;
assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
&i2c5 {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c5_pins>;
pinctrl-names = "default";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:Default */
0x0000 /* 3:Default */
0x0000 /* 4:Default */
0x0000 /* 5:Default */
>;
port {
wm8962_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint0>;
};
};
};
/* 0 - lcd_reset */
/* 1 - lcd_pwr */
/* 2 - lcd_select */
/* 3 - backlight-enable */
/* 4 - Touch_shdwn */
/* 5 - LCD_H_pol */
/* 6 - lcd_V_pol */
gpio_exp1: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
touchscreen@26 {
compatible = "ilitek,ili2117";
reg = <0x26>;
interrupt-parent = <&gpio5>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
wakeup-source;
};
hd3ss3220@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
interrupt-parent = <&gpio6>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
hd3ss3220_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&ohci1 {
status = "okay";
};
&pciec0 {
status = "okay";
};
&pciec1 {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pfc {
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_clk_out_1", "du_disp";
function = "du";
};
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
};
i2c5_pins: i2c5 {
groups = "i2c5";
function = "i2c5";
};
led_pins: leds {
/* GP_0_4 , AVS1, AVS2, GP_7_3 */
pins = "GP_0_4", "GP_7_0", "GP_7_1", "GP_7_3";
bias-pull-down;
};
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
pwm2_pins: pwm2 {
groups = "pwm2_a";
function = "pwm2_a";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
function = "ssi";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a_a";
function = "audio_clk";
};
usb0_pins: usb0 {
mux {
groups = "usb0";
function = "usb0";
};
};
usb1_pins: usb1 {
mux {
groups = "usb1";
function = "usb1";
};
};
usb30_pins: usb30 {
mux {
groups = "usb30";
function = "usb30";
};
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm2 {
pinctrl-0 = <&pwm2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
ports {
#address-cells = <1>;
#size-cells = <0>;
rsnd_port0: port@0 {
reg = <0>;
rsnd_endpoint0: endpoint {
remote-endpoint = <&wm8962_endpoint>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
playback = <&ssi1 &dvc1 &src1>;
capture = <&ssi0>;
};
};
rsnd_port1: port@1 {
reg = <0x01>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
&rwdt {
status = "okay";
timeout-sec = <60>;
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif5 {
pinctrl-0 = <&scif5_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&ssi1 {
shared-pin;
};
&tmu0 {
status = "okay";
};
&tmu1 {
status = "okay";
};
&tmu2 {
status = "okay";
};
&tmu3 {
status = "okay";
};
&tmu4 {
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_peri0 {
companion = <&xhci0>;
status = "okay";
usb-role-switch;
port {
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_ep>;
};
};
};
&usb3_phy0 {
status = "okay";
};
&vin0 {
status = "okay";
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&vin6 {
status = "okay";
};
&vin7 {
status = "okay";
};
&xhci0
{
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi 0 → 100644
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
#include <dt-bindings/gpio/gpio.h>
/ {
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
osc_32k: osc_32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
wlan_pwrseq: wlan_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
clocks = <&osc_32k>;
clock-names = "ext_clock";
post-power-on-delay-ms = <80>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gpio6 {
usb_hub_reset {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
max-speed = <4000000>;
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
clocks = <&osc_32k>;
clock-names = "extclk";
};
};
&hscif2 {
status = "okay";
pinctrl-0 = <&hscif2_pins>;
pinctrl-names = "default";
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
pca9654: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"i2c4_20_0",
"wl_reg_on",
"bt_reg_on",
"i2c4_20_3",
"i2c4_20_4",
"bt_dev_wake",
"i2c4_20_6",
"i2c4_20_7";
};
pca9654_lte: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
interrupt-parent = <&gpio5>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"i2c4_21_0",
"zoe_pwr_on",
"zoe_extint",
"zoe_reset_n",
"sara_reset",
"i2c4_21_5",
"sara_pwr_off",
"sara_networking_status";
};
eeprom@50 {
compatible = "microchip,at24c64", "atmel,24c64";
pagesize = <32>;
read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x50>;
};
rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};
versaclock5: versaclock_som@6a {
compatible = "idt,5p49v6965";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&x304_clk>;
clock-names = "xin";
/* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
assigned-clocks = <&versaclock5 1>,
<&versaclock5 2>,
<&versaclock5 3>,
<&versaclock5 4>;
assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
};
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
hscif1_pins: hscif1 {
groups = "hscif1_data_a", "hscif1_ctrl_a";
function = "hscif1";
};
hscif2_pins: hscif2 {
groups = "hscif2_data_a";
function = "hscif2";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif5_pins: scif5 {
groups = "scif5_data_a";
function = "scif5";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
};
&scif_clk {
clock-frequency = <14745600>;
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi2 {
pinctrl-names = "default";
pinctrl-0 = <&sdhi2_pins>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
cap-power-off-card;
pm-ignore-notify;
keep-power-in-suspend;
mmc-pwrseq = <&wlan_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
&usb_extal_clk {
clock-frequency = <50000000>;
};
&usb3s0_clk {
clock-frequency = <100000000>;
};
&vspb {
status = "okay";
};
&vspi0 {
status = "okay";
};
arch/arm64/boot/dts/renesas/cat875.dtsi
View file @ 2c2a5564
......@@ -18,7 +18,6 @@ &avb {
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii";
status = "okay";
phy0: ethernet-phy@0 {
......
arch/arm64/boot/dts/renesas/hihope-common.dtsi
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[MN] main board
* Rev.[2.0/3.0/4.0] common parts
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
......
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2[MN] Rev.3.0/4.0 main board
* common parts
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
......
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZ/G2[MN] HiHope sub board common parts
* Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
......
arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts 0 → 100644
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Compass Electronics Group, LLC
*/
/dts-v1/;
#include "r8a774a1.dtsi"
#include "beacon-renesom-som.dtsi"
#include "beacon-renesom-baseboard.dtsi"
/ {
model = "Beacon EmbeddedWorks RZ/G2M Development Kit";
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
aliases {
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;
serial3 = &scif0;
serial4 = &hscif2;
serial5 = &scif5;
ethernet0 = &avb;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View file @ 2c2a5564
......@@ -2252,7 +2252,7 @@ usb2_phy1: usb-phy@ee0a0200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
......@@ -2264,7 +2264,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
......@@ -2276,7 +2276,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
......@@ -2288,7 +2288,7 @@ sdhi2: sd@ee140000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View file @ 2c2a5564
......@@ -2110,7 +2110,7 @@ usb2_phy1: usb-phy@ee0a0200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774b1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
......@@ -2122,7 +2122,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774b1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
......@@ -2134,7 +2134,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774b1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
......@@ -2146,7 +2146,7 @@ sdhi2: sd@ee140000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774b1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View file @ 2c2a5564
......@@ -1618,7 +1618,7 @@ usb2_phy0: usb-phy@ee080200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774c0",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
......@@ -1630,7 +1630,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774c0",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
......@@ -1642,7 +1642,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774c0",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts 0 → 100644
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H sub board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a774e1-hihope-rzg2h.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
"renesas,r8a774e1";
};
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts 0 → 100644
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2H main board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774e1.dtsi"
#include "hihope-rev4.dtsi"
/ {
model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x80000000>;
};
};
arch/arm64/boot/dts/renesas/r8a774e1.dtsi 0 → 100644
View file @ 2c2a5564
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a774e1 SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
#include <dt-bindings/power/r8a774e1-sysc.h>
#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4
/ {
compatible = "renesas,r8a774e1";
#address-cells = <2>;
#size-cells = <2>;
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&a57_0>;
};
core1 {
cpu = <&a57_1>;
};
core2 {
cpu = <&a57_2>;
};
core3 {
cpu = <&a57_3>;
};
};
cluster1 {
core0 {
cpu = <&a53_0>;
};
core1 {
cpu = <&a53_1>;
};
core2 {
cpu = <&a53_2>;
};
core3 {
cpu = <&a53_3>;
};
};
};
a57_0: cpu@0 {
compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
a57_1: cpu@1 {
compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
a57_2: cpu@2 {
compatible = "arm,cortex-a57";
reg = <0x2>;
device_type = "cpu";
power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
a57_3: cpu@3 {
compatible = "arm,cortex-a57";
reg = <0x3>;
device_type = "cpu";
power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
a53_0: cpu@100 {
compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
#cooling-cells = <2>;
dynamic-power-coefficient = <277>;
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
};
a53_1: cpu@101 {
compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
};
a53_2: cpu@102 {
compatible = "arm,cortex-a53";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
};
a53_3: cpu@103 {
compatible = "arm,cortex-a53";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
};
L2_CA57: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};
L2_CA53: cache-controller-1 {
compatible = "cache";
power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a774e1-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a774e1",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 16>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a774e1",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 29>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a774e1",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 15>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a774e1",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 16>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a774e1",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 18>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a774e1",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 26>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a774e1",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 906>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 906>;
};
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a774e1",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 224 4>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 905>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 905>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a774e1";
reg = <0 0xe6060000 0 0x50c>;
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a774e1-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a774e1-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a774e1-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a774e1-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a774e1-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a774e1-rst";
reg = <0 0xe6160000 0 0x0200>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a774e1-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
};
tsc: thermal@e6198000 {
compatible = "renesas,r8a774e1-thermal";
reg = <0 0xe6198000 0 0x100>,
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 125>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 124>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 123>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 122>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 121>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a774e1",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 931>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c1: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a774e1",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 930>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a774e1",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 929>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a774e1",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 928>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c4: i2c@e66d8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a774e1",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 927>;
dmas = <&dmac0 0x99>, <&dmac0 0x98>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c5: i2c@e66e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a774e1",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 919>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c6: i2c@e66e8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a774e1",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e8000 0 0x40>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 918>;
dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c_dvfs: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a774e1",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled";
};
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a774e1",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 520>;
status = "disabled";
};
hscif1: serial@e6550000 {
compatible = "renesas,hscif-r8a774e1",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe6550000 0 0x60>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
<&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 519>;
status = "disabled";
};
hscif2: serial@e6560000 {
compatible = "renesas,hscif-r8a774e1",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe6560000 0 0x60>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 518>;
status = "disabled";
};
hscif3: serial@e66a0000 {
compatible = "renesas,hscif-r8a774e1",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe66a0000 0 0x60>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x37>, <&dmac0 0x36>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 517>;
status = "disabled";
};
hscif4: serial@e66b0000 {
compatible = "renesas,hscif-r8a774e1",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe66b0000 0 0x60>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x39>, <&dmac0 0x38>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 516>;
status = "disabled";
};
hsusb: usb@e6590000 {
reg = <0 0xe6590000 0 0x200>;
status = "disabled";
/* placeholder */
};
usb3_phy0: usb-phy@e65ee000 {
reg = <0 0xe65ee000 0 0x90>;
#phy-cells = <0>;
status = "disabled";
/* placeholder */
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a774e1",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x10000>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a774e1",
"renesas,rcar-dmac";
reg = <0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
};
dmac2: dma-controller@e7310000 {
compatible = "renesas,dmac-r8a774e1",
"renesas,rcar-dmac";
reg = <0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
ipmmu_ds0: iommu@e6740000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds1: iommu@e7740000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_hc: iommu@e6570000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mm: iommu@e67b0000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mp0: iommu@ec670000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv0: iommu@fd800000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv1: iommu@fd950000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv2: iommu@fd960000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfd960000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv3: iommu@fd970000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfd970000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vc0: iommu@fe6b0000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
power-domains = <&sysc R8A774E1_PD_A3VC>;
#iommu-cells = <1>;
};
ipmmu_vc1: iommu@fe6f0000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfe6f0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 13>;
power-domains = <&sysc R8A774E1_PD_A3VC>;
#iommu-cells = <1>;
};
ipmmu_vi0: iommu@febd0000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vi1: iommu@febe0000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfebe0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 15>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vp0: iommu@fe990000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
power-domains = <&sysc R8A774E1_PD_A3VP>;
#iommu-cells = <1>;
};
ipmmu_vp1: iommu@fe980000 {
compatible = "renesas,ipmmu-r8a774e1";
reg = <0 0xfe980000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 17>;
power-domains = <&sysc R8A774E1_PD_A3VP>;
#iommu-cells = <1>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a774e1",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
can0: can@e6c30000 {
compatible = "renesas,can-r8a774e1",
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A774E1_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6c38000 {
compatible = "renesas,can-r8a774e1",
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A774E1_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a774e1-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774E1_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
pwm0: pwm@e6e30000 {
reg = <0 0xe6e30000 0 0x8>;
#pwm-cells = <2>;
status = "disabled";
/* placeholder */
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a774e1",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e60000 0 0x40>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a774e1",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e68000 0 0x40>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a774e1",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 0x40>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
<&dmac2 0x13>, <&dmac2 0x12>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a774e1",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c50000 0 0x40>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
scif4: serial@e6c40000 {
compatible = "renesas,scif-r8a774e1",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c40000 0 0x40>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
scif5: serial@e6f30000 {
compatible = "renesas,scif-r8a774e1",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6f30000 0 0x40>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 202>,
<&cpg CPG_CORE R8A774E1_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
<&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a774e1",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 211>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a774e1",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a774e1",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 209>;
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 209>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a774e1",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 208>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rcar_sound: sound@ec500000 {
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
status = "disabled";
/* placeholder */
rcar_sound,ssi {
ssi2: ssi-2 {
/* placeholder */
};
};
};
xhci0: usb@ee000000 {
reg = <0 0xee000000 0 0xc00>;
status = "disabled";
/* placeholder */
};
usb3_peri0: usb@ee020000 {
reg = <0 0xee020000 0 0x400>;
status = "disabled";
/* placeholder */
};
ohci0: usb@ee080000 {
reg = <0 0xee080000 0 0x100>;
status = "disabled";
/* placeholder */
};
ohci1: usb@ee0a0000 {
reg = <0 0xee0a0000 0 0x100>;
status = "disabled";
/* placeholder */
};
ehci0: usb@ee080100 {
reg = <0 0xee080100 0 0x100>;
status = "disabled";
/* placeholder */
};
ehci1: usb@ee0a0100 {
reg = <0 0xee0a0100 0 0x100>;
status = "disabled";
/* placeholder */
};
usb2_phy0: usb-phy@ee080200 {
reg = <0 0xee080200 0 0x700>;
status = "disabled";
/* placeholder */
};
usb2_phy1: usb-phy@ee0a0200 {
reg = <0 0xee0a0200 0 0x700>;
status = "disabled";
/* placeholder */
};
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a774e1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a774e1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
iommus = <&ipmmu_ds1 33>;
status = "disabled";
};
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a774e1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
iommus = <&ipmmu_ds1 34>;
status = "disabled";
};
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a774e1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 311>;
iommus = <&ipmmu_ds1 35>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
pciec0: pcie@fe000000 {
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
/* placeholder */
};
hdmi0: hdmi@fead0000 {
reg = <0 0xfead0000 0 0x10000>;
status = "disabled";
/* placeholder */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
};
};
du: display@feb00000 {
reg = <0 0xfeb00000 0 0x80000>;
status = "disabled";
/* placeholder */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
};
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
sustainable-power = <6313>;
trips {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
sustainable-power = <6313>;
trips {
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
sustainable-power = <6313>;
trips {
target: trip-point1 {
temperature = <100000>;
hysteresis = <1000>;
type = "passive";
};
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&a57_0 0 2>;
contribution = <1024>;
};
map1 {
trip = <&target>;
cooling-device = <&a53_0 0 2>;
contribution = <1024>;
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
};
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View file @ 2c2a5564
......@@ -2590,7 +2590,7 @@ usb2_phy3: usb-phy@ee0e0200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
......@@ -2603,7 +2603,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
......@@ -2616,7 +2616,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
......@@ -2629,7 +2629,7 @@ sdhi2: sd@ee140000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View file @ 2c2a5564
......@@ -2394,7 +2394,7 @@ usb2_phy1: usb-phy@ee0a0200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
......@@ -2407,7 +2407,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
......@@ -2420,7 +2420,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
......@@ -2433,7 +2433,7 @@ sdhi2: sd@ee140000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View file @ 2c2a5564
......@@ -1346,7 +1346,7 @@ usb2_phy1: usb-phy@ee0a0200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77961",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
......@@ -1358,7 +1358,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a77961",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
......@@ -1370,7 +1370,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77961",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
......@@ -1382,7 +1382,7 @@ sdhi2: sd@ee140000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77961",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View file @ 2c2a5564
......@@ -2120,7 +2120,7 @@ usb2_phy1: usb-phy@ee0a0200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
......@@ -2133,7 +2133,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
......@@ -2146,7 +2146,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
......@@ -2159,7 +2159,7 @@ sdhi2: sd@ee140000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77965",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
View file @ 2c2a5564
......@@ -187,12 +187,79 @@ i2c0_pins: i2c0 {
function = "i2c0";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
......
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View file @ 2c2a5564
......@@ -212,12 +212,79 @@ mmc_pins: mmc_3_3v {
power-source = <3300>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
......
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View file @ 2c2a5564
......@@ -1039,6 +1039,23 @@ mmc0: mmc@ee140000 {
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77970-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x4000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
......
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
View file @ 2c2a5564
......@@ -262,6 +262,11 @@ mmc_pins_uhs: mmc_uhs {
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
......@@ -273,6 +278,68 @@ scif_clk_pins: scif_clk {
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
......
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
View file @ 2c2a5564
......@@ -187,6 +187,11 @@ i2c0_pins: i2c0 {
function = "i2c0";
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
......@@ -198,6 +203,68 @@ scif_clk_pins: scif_clk {
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
......
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View file @ 2c2a5564
......@@ -1344,6 +1344,23 @@ mmc0: mmc@ee140000 {
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a77980-rpc-if",
"renesas,rcar-gen3-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x4000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
......
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
View file @ 2c2a5564
......@@ -715,6 +715,7 @@ &sdhi3 {
mmc-hs400-1_8v;
bus-width = <8>;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
......
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View file @ 2c2a5564
......@@ -1595,7 +1595,7 @@ usb2_phy0: usb-phy@ee080200 {
status = "disabled";
};
sdhi0: sd@ee100000 {
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
......@@ -1608,7 +1608,7 @@ sdhi0: sd@ee100000 {
status = "disabled";
};
sdhi1: sd@ee120000 {
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
......@@ -1621,7 +1621,7 @@ sdhi1: sd@ee120000 {
status = "disabled";
};
sdhi3: sd@ee160000 {
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77990",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View file @ 2c2a5564
......@@ -916,7 +916,7 @@ usb2_phy0: usb-phy@ee080200 {
status = "disabled";
};
sdhi2: sd@ee140000 {
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77995",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
......
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View file @ 2c2a5564
......@@ -833,6 +833,7 @@ &sdhi2 {
mmc-hs400-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
full-pwr-cycle-in-suspend;
status = "okay";
};
......
arch/arm64/configs/defconfig
View file @ 2c2a5564
......@@ -865,6 +865,7 @@ CONFIG_QCOM_APR=m
CONFIG_ARCH_R8A774A1=y
CONFIG_ARCH_R8A774B1=y
CONFIG_ARCH_R8A774C0=y
CONFIG_ARCH_R8A774E1=y
CONFIG_ARCH_R8A77950=y
CONFIG_ARCH_R8A77951=y
CONFIG_ARCH_R8A77960=y
......
include/dt-bindings/clock/r8a774e1-cpg-mssr.h 0 → 100644
View file @ 2c2a5564
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R8A774E1 CPG Core Clocks */
#define R8A774E1_CLK_Z 0
#define R8A774E1_CLK_Z2 1
#define R8A774E1_CLK_ZG 2
#define R8A774E1_CLK_ZTR 3
#define R8A774E1_CLK_ZTRD2 4
#define R8A774E1_CLK_ZT 5
#define R8A774E1_CLK_ZX 6
#define R8A774E1_CLK_S0D1 7
#define R8A774E1_CLK_S0D2 8
#define R8A774E1_CLK_S0D3 9
#define R8A774E1_CLK_S0D4 10
#define R8A774E1_CLK_S0D6 11
#define R8A774E1_CLK_S0D8 12
#define R8A774E1_CLK_S0D12 13
#define R8A774E1_CLK_S1D2 14
#define R8A774E1_CLK_S1D4 15
#define R8A774E1_CLK_S2D1 16
#define R8A774E1_CLK_S2D2 17
#define R8A774E1_CLK_S2D4 18
#define R8A774E1_CLK_S3D1 19
#define R8A774E1_CLK_S3D2 20
#define R8A774E1_CLK_S3D4 21
#define R8A774E1_CLK_LB 22
#define R8A774E1_CLK_CL 23
#define R8A774E1_CLK_ZB3 24
#define R8A774E1_CLK_ZB3D2 25
#define R8A774E1_CLK_ZB3D4 26
#define R8A774E1_CLK_CR 27
#define R8A774E1_CLK_CRD2 28
#define R8A774E1_CLK_SD0H 29
#define R8A774E1_CLK_SD0 30
#define R8A774E1_CLK_SD1H 31
#define R8A774E1_CLK_SD1 32
#define R8A774E1_CLK_SD2H 33
#define R8A774E1_CLK_SD2 34
#define R8A774E1_CLK_SD3H 35
#define R8A774E1_CLK_SD3 36
#define R8A774E1_CLK_RPC 37
#define R8A774E1_CLK_RPCD2 38
#define R8A774E1_CLK_MSO 39
#define R8A774E1_CLK_HDMI 40
#define R8A774E1_CLK_CSI0 41
#define R8A774E1_CLK_CP 42
#define R8A774E1_CLK_CPEX 43
#define R8A774E1_CLK_R 44
#define R8A774E1_CLK_OSC 45
#define R8A774E1_CLK_CANFD 46
#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */
include/dt-bindings/power/r8a774e1-sysc.h 0 → 100644
View file @ 2c2a5564
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774E1_PD_CA57_CPU0 0
#define R8A774E1_PD_CA57_CPU1 1
#define R8A774E1_PD_CA57_CPU2 2
#define R8A774E1_PD_CA57_CPU3 3
#define R8A774E1_PD_CA53_CPU0 5
#define R8A774E1_PD_CA53_CPU1 6
#define R8A774E1_PD_CA53_CPU2 7
#define R8A774E1_PD_CA53_CPU3 8
#define R8A774E1_PD_A3VP 9
#define R8A774E1_PD_CA57_SCU 12
#define R8A774E1_PD_A3VC 14
#define R8A774E1_PD_3DG_A 17
#define R8A774E1_PD_3DG_B 18
#define R8A774E1_PD_3DG_C 19
#define R8A774E1_PD_3DG_D 20
#define R8A774E1_PD_CA53_SCU 21
#define R8A774E1_PD_3DG_E 22
#define R8A774E1_PD_A2VC1 26
/* Always-on power area */
#define R8A774E1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */
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