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Commit 2c72404e authored by Jin Yao's avatar Jin Yao Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Update core event list for SkyLake Server 

Update JSON core events for SkyLake Server.

Based on JSON list v1.24:

https://download.01.org/perfmon/SKX/

Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linux-kernel@vger.kernel.org
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https //lore.kernel.org/r/20210810020508.31261-5-yao.jin@linux.intel.com
Signed-off-by: default avatarJin Yao <yao.jin@linux.intel.com>
parent ed97cc6c
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Showing with 2565 additions and 2555 deletions
tools/perf/pmu-events/arch/x86/skylakex/cache.json
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tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
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...@@ -9,22 +9,13 @@ ...@@ -9,22 +9,13 @@
"UMask": "0x4" "UMask": "0x4"
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x2" "UMask": "0x8"
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
...@@ -36,33 +27,31 @@ ...@@ -36,33 +27,31 @@
"UMask": "0x10" "UMask": "0x10"
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x80" "UMask": "0x20"
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x20" "UMask": "0x40"
}, },
{ {
"BriefDescription": "Cycles with any input/output SSE or FP assist", "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "EventCode": "0xC7",
"EventCode": "0xCA", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"EventName": "FP_ASSIST.ANY", "SampleAfterValue": "2000003",
"PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", "UMask": "0x80"
"SampleAfterValue": "100003",
"UMask": "0x1e"
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
...@@ -74,12 +63,23 @@ ...@@ -74,12 +63,23 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x8" "UMask": "0x2"
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
"PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
"SampleAfterValue": "100003",
"UMask": "0x1e"
} }
] ]
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tools/perf/pmu-events/arch/x86/skylakex/memory.json
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tools/perf/pmu-events/arch/x86/skylakex/other.json
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[ [
{
"BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.THROTTLE",
"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE",
"EventName": "IDI_MISC.WB_DOWNGRADE",
"PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
...@@ -49,13 +20,24 @@ ...@@ -49,13 +20,24 @@
"UMask": "0x18" "UMask": "0x18"
}, },
{ {
"BriefDescription": "Number of PREFETCHT0 instructions executed.", "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32", "EventCode": "0x28",
"EventName": "SW_PREFETCH_ACCESS.T0", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"SampleAfterValue": "2000003", "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
"UMask": "0x2" "SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.THROTTLE",
"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
"SampleAfterValue": "200003",
"UMask": "0x40"
}, },
{ {
"BriefDescription": "Number of hardware interrupts received by the processor.", "BriefDescription": "Number of hardware interrupts received by the processor.",
...@@ -68,14 +50,32 @@ ...@@ -68,14 +50,32 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28", "EventCode": "0xFE",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "EventName": "IDI_MISC.WB_DOWNGRADE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
"SampleAfterValue": "200003", "SampleAfterValue": "100003",
"UMask": "0x20" "UMask": "0x4"
},
{
"BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE",
"EventName": "IDI_MISC.WB_UPGRADE",
"PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x09",
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Number of PREFETCHNTA instructions executed.", "BriefDescription": "Number of PREFETCHNTA instructions executed.",
...@@ -87,30 +87,30 @@ ...@@ -87,30 +87,30 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", "BriefDescription": "Number of PREFETCHW instructions executed.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32", "EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x4" "UMask": "0x8"
}, },
{ {
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x09", "EventCode": "0x32",
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "EventName": "SW_PREFETCH_ACCESS.T0",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"UMask": "0x1" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE", "EventCode": "0x32",
"EventName": "IDI_MISC.WB_UPGRADE", "EventName": "SW_PREFETCH_ACCESS.T1_T2",
"PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", "SampleAfterValue": "2000003",
"SampleAfterValue": "100003", "UMask": "0x4"
"UMask": "0x2"
} }
] ]
\ No newline at end of file
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