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Commit 2c89ce4f authored by Maxime Ripard's avatar Maxime Ripard
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ARM: sun8i: Convert the A23 and A33 to the CCU 

Now that we have support for the CCU driver in sunxi-ng, convert the A23
and A33 DTs to that driver.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 78a9f0db
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Showing with 75 additions and 306 deletions
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View file @ 2c89ce4f
This diff is collapsed.
arch/arm/boot/dts/sun8i-a23.dtsi
View file @ 2c89ce4f
......@@ -49,47 +49,12 @@ memory {
reg = <0x40000000 0x40000000>;
};
clocks {
ahb1_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
clock-indices = <1>, <6>,
<8>, <9>, <10>,
<13>, <14>,
<19>, <20>,
<21>, <24>, <26>,
<29>, <32>, <36>,
<40>, <44>, <46>,
<52>, <53>,
<54>, <57>;
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
"ahb1_nand", "ahb1_sdram",
"ahb1_hstimer", "ahb1_spi0",
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
"ahb1_csi", "ahb1_be", "ahb1_fe",
"ahb1_gpu", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_drc";
};
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
};
soc@01c00000 {
usb_otg: usb@01c19000 {
compatible = "allwinner,sun6i-a31-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ahb1_gates 24>;
resets = <&ahb1_rst 24>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
......@@ -104,12 +69,12 @@ usbphy: phy@01c19400 {
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu1";
clocks = <&usb_clk 8>,
<&usb_clk 9>;
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&usb_clk 0>,
<&usb_clk 1>;
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
......@@ -118,6 +83,10 @@ usbphy: phy@01c19400 {
};
};
&ccu {
compatible = "allwinner,sun8i-a23-ccu";
};
&pio {
compatible = "allwinner,sun8i-a23-pinctrl";
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
......
arch/arm/boot/dts/sun8i-a33.dtsi
View file @ 2c89ce4f
......@@ -63,75 +63,22 @@ memory {
reg = <0x40000000 0x80000000>;
};
clocks {
/* Dummy clock for pll11 (DDR1) until actually implemented */
pll11: pll11_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
clock-output-names = "pll11";
};
ahb1_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a33-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
clock-indices = <1>, <5>,
<6>, <8>, <9>,
<10>, <13>, <14>,
<19>, <20>,
<21>, <24>, <26>,
<29>, <32>, <36>,
<40>, <44>, <46>,
<52>, <53>,
<54>, <57>,
<58>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma","ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_nand", "ahb1_sdram",
"ahb1_hstimer", "ahb1_spi0",
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
"ahb1_csi", "ahb1_be", "ahb1_fe",
"ahb1_gpu", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_drc",
"ahb1_sat";
};
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "ss";
};
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>;
clock-output-names = "mbus";
};
};
soc@01c00000 {
crypto: crypto-engine@01c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 5>, <&ss_clk>;
clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
clock-names = "ahb", "mod";
resets = <&ahb1_rst 5>;
resets = <&ccu RST_BUS_SS>;
reset-names = "ahb";
};
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ahb1_gates 24>;
resets = <&ahb1_rst 24>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
......@@ -146,12 +93,12 @@ usbphy: phy@01c19400 {
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu1";
clocks = <&usb_clk 8>,
<&usb_clk 9>;
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&usb_clk 0>,
<&usb_clk 1>;
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
......@@ -160,6 +107,10 @@ usbphy: phy@01c19400 {
};
};
&ccu {
compatible = "allwinner,sun8i-a33-ccu";
};
&pio {
compatible = "allwinner,sun8i-a33-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
......
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