Commit 2cfcf8a8 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Ralf Baechle

MIPS: math-emu: Remove `modeindex' macro

Commit 56a64733 [MIPS: math-emu: Switch to using the MIPS rounding
modes.] removed the distinction between hardware and emulator rounding
mode encodings, the hardware encoding is now used in emulation as well.
Complement the change and remove the `modeindex' macro previously used
for indexing into encoding translation tables, it now does nothing and
only obfuscates code by reinserting the value extracted from FCSR.
Adjust comments accordingly.
Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9680/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4a7c2371
...@@ -65,9 +65,6 @@ static int fpux_emu(struct pt_regs *, ...@@ -65,9 +65,6 @@ static int fpux_emu(struct pt_regs *,
#define FPCREG_RID 0 /* $0 = revision id */ #define FPCREG_RID 0 /* $0 = revision id */
#define FPCREG_CSR 31 /* $31 = csr */ #define FPCREG_CSR 31 /* $31 = csr */
/* Determine rounding mode from the RM bits of the FCSR */
#define modeindex(v) ((v) & FPU_CSR_RM)
/* convert condition code register number to csr bit */ /* convert condition code register number to csr bit */
const unsigned int fpucondbit[8] = { const unsigned int fpucondbit[8] = {
FPU_CSR_COND0, FPU_CSR_COND0,
...@@ -1051,7 +1048,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -1051,7 +1048,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
/* cop control register rd -> gpr[rt] */ /* cop control register rd -> gpr[rt] */
if (MIPSInst_RD(ir) == FPCREG_CSR) { if (MIPSInst_RD(ir) == FPCREG_CSR) {
value = ctx->fcr31; value = ctx->fcr31;
value = (value & ~FPU_CSR_RM) | modeindex(value);
pr_debug("%p gpr[%d]<-csr=%08x\n", pr_debug("%p gpr[%d]<-csr=%08x\n",
(void *) (xcp->cp0_epc), (void *) (xcp->cp0_epc),
MIPSInst_RT(ir), value); MIPSInst_RT(ir), value);
...@@ -1078,12 +1074,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -1078,12 +1074,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
(void *) (xcp->cp0_epc), (void *) (xcp->cp0_epc),
MIPSInst_RT(ir), value); MIPSInst_RT(ir), value);
/* /* Don't write reserved bits. */
* Don't write reserved bits, ctx->fcr31 = value & ~FPU_CSR_RSVD;
* and convert to ieee library modes
*/
ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
modeindex(value);
} }
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
return SIGFPE; return SIGFPE;
...@@ -1675,7 +1667,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -1675,7 +1667,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
oldrm = ieee754_csr.rm; oldrm = ieee754_csr.rm;
SPFROMREG(fs, MIPSInst_FS(ir)); SPFROMREG(fs, MIPSInst_FS(ir));
ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); ieee754_csr.rm = MIPSInst_FUNC(ir);
rv.w = ieee754sp_tint(fs); rv.w = ieee754sp_tint(fs);
ieee754_csr.rm = oldrm; ieee754_csr.rm = oldrm;
rfmt = w_fmt; rfmt = w_fmt;
...@@ -1699,7 +1691,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -1699,7 +1691,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
oldrm = ieee754_csr.rm; oldrm = ieee754_csr.rm;
SPFROMREG(fs, MIPSInst_FS(ir)); SPFROMREG(fs, MIPSInst_FS(ir));
ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); ieee754_csr.rm = MIPSInst_FUNC(ir);
rv.l = ieee754sp_tlong(fs); rv.l = ieee754sp_tlong(fs);
ieee754_csr.rm = oldrm; ieee754_csr.rm = oldrm;
rfmt = l_fmt; rfmt = l_fmt;
...@@ -1852,7 +1844,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -1852,7 +1844,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
oldrm = ieee754_csr.rm; oldrm = ieee754_csr.rm;
DPFROMREG(fs, MIPSInst_FS(ir)); DPFROMREG(fs, MIPSInst_FS(ir));
ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); ieee754_csr.rm = MIPSInst_FUNC(ir);
rv.w = ieee754dp_tint(fs); rv.w = ieee754dp_tint(fs);
ieee754_csr.rm = oldrm; ieee754_csr.rm = oldrm;
rfmt = w_fmt; rfmt = w_fmt;
...@@ -1876,7 +1868,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -1876,7 +1868,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
oldrm = ieee754_csr.rm; oldrm = ieee754_csr.rm;
DPFROMREG(fs, MIPSInst_FS(ir)); DPFROMREG(fs, MIPSInst_FS(ir));
ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); ieee754_csr.rm = MIPSInst_FUNC(ir);
rv.l = ieee754dp_tlong(fs); rv.l = ieee754dp_tlong(fs);
ieee754_csr.rm = oldrm; ieee754_csr.rm = oldrm;
rfmt = l_fmt; rfmt = l_fmt;
...@@ -2081,10 +2073,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, ...@@ -2081,10 +2073,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
else { else {
/* /*
* The 'ieee754_csr' is an alias of * The 'ieee754_csr' is an alias of ctx->fcr31.
* ctx->fcr31. No need to copy ctx->fcr31 to * No need to copy ctx->fcr31 to ieee754_csr.
* ieee754_csr. But ieee754_csr.rm is ieee
* library modes. (not mips rounding mode)
*/ */
sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
} }
......
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