ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA

Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts

@@ -96,10 +96,14 @@ phy1: ethernet-phy@1 {
 			rxd1-skew-ps = <0>;
 			rxd2-skew-ps = <0>;
 			rxd3-skew-ps = <0>;
+			txd0-skew-ps = <0>;
+			txd1-skew-ps = <0>;
+			txd2-skew-ps = <0>;
+			txd3-skew-ps = <0>;
 			txen-skew-ps = <0>;
-			txc-skew-ps = <2600>;
+			txc-skew-ps = <1860>;
 			rxdv-skew-ps = <0>;
-			rxc-skew-ps = <2000>;
+			rxc-skew-ps = <1860>;
 		};
 	};
 };