Commit 2ded1881 authored by Dave Airlie's avatar Dave Airlie

Merge branch 'drm-fixes-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Fixes for 5.1:
- Fix for pcie dpm
- Powerplay fixes for vega20
- Fix vbios display on reboot if driver display state is retained
- Gfx9 resume robustness fix
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190404042939.3386-1-alexander.deucher@amd.com
parents 79a3aaa7 d939f44d
...@@ -3625,6 +3625,7 @@ static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev, ...@@ -3625,6 +3625,7 @@ static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
struct pci_dev *pdev = adev->pdev; struct pci_dev *pdev = adev->pdev;
enum pci_bus_speed cur_speed; enum pci_bus_speed cur_speed;
enum pcie_link_width cur_width; enum pcie_link_width cur_width;
u32 ret = 1;
*speed = PCI_SPEED_UNKNOWN; *speed = PCI_SPEED_UNKNOWN;
*width = PCIE_LNK_WIDTH_UNKNOWN; *width = PCIE_LNK_WIDTH_UNKNOWN;
...@@ -3632,6 +3633,10 @@ static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev, ...@@ -3632,6 +3633,10 @@ static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
while (pdev) { while (pdev) {
cur_speed = pcie_get_speed_cap(pdev); cur_speed = pcie_get_speed_cap(pdev);
cur_width = pcie_get_width_cap(pdev); cur_width = pcie_get_width_cap(pdev);
ret = pcie_bandwidth_available(adev->pdev, NULL,
NULL, &cur_width);
if (!ret)
cur_width = PCIE_LNK_WIDTH_RESRV;
if (cur_speed != PCI_SPEED_UNKNOWN) { if (cur_speed != PCI_SPEED_UNKNOWN) {
if (*speed == PCI_SPEED_UNKNOWN) if (*speed == PCI_SPEED_UNKNOWN)
......
...@@ -2405,8 +2405,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) ...@@ -2405,8 +2405,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
/* disable CG */ /* disable CG */
WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
adev->gfx.rlc.funcs->reset(adev);
gfx_v9_0_init_pg(adev); gfx_v9_0_init_pg(adev);
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
......
...@@ -2660,12 +2660,18 @@ void core_link_enable_stream( ...@@ -2660,12 +2660,18 @@ void core_link_enable_stream(
void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
{ {
struct dc *core_dc = pipe_ctx->stream->ctx->dc; struct dc *core_dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
core_dc->hwss.blank_stream(pipe_ctx); core_dc->hwss.blank_stream(pipe_ctx);
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
deallocate_mst_payload(pipe_ctx); deallocate_mst_payload(pipe_ctx);
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
dal_ddc_service_write_scdc_data(
stream->link->ddc, 0,
stream->timing.flags.LTE_340MCSC_SCRAMBLE);
core_dc->hwss.disable_stream(pipe_ctx, option); core_dc->hwss.disable_stream(pipe_ctx, option);
disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal); disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
......
...@@ -91,6 +91,12 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) ...@@ -91,6 +91,12 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
* MP0CLK DS * MP0CLK DS
*/ */
data->registry_data.disallowed_features = 0xE0041C00; data->registry_data.disallowed_features = 0xE0041C00;
/* ECC feature should be disabled on old SMUs */
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr->smu_version = smum_get_argument(hwmgr);
if (hwmgr->smu_version < 0x282100)
data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
data->registry_data.od_state_in_dc_support = 0; data->registry_data.od_state_in_dc_support = 0;
data->registry_data.thermal_support = 1; data->registry_data.thermal_support = 1;
data->registry_data.skip_baco_hardware = 0; data->registry_data.skip_baco_hardware = 0;
...@@ -357,6 +363,7 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr) ...@@ -357,6 +363,7 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT; data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT; data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT; data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
for (i = 0; i < GNLD_FEATURES_MAX; i++) { for (i = 0; i < GNLD_FEATURES_MAX; i++) {
data->smu_features[i].smu_feature_bitmap = data->smu_features[i].smu_feature_bitmap =
...@@ -3020,7 +3027,8 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) ...@@ -3020,7 +3027,8 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
"FCLK_DS", "FCLK_DS",
"MP1CLK_DS", "MP1CLK_DS",
"MP0CLK_DS", "MP0CLK_DS",
"XGMI"}; "XGMI",
"ECC"};
static const char *output_title[] = { static const char *output_title[] = {
"FEATURES", "FEATURES",
"BITMASK", "BITMASK",
...@@ -3462,6 +3470,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) ...@@ -3462,6 +3470,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
struct vega20_single_dpm_table *dpm_table; struct vega20_single_dpm_table *dpm_table;
bool vblank_too_short = false; bool vblank_too_short = false;
bool disable_mclk_switching; bool disable_mclk_switching;
bool disable_fclk_switching;
uint32_t i, latency; uint32_t i, latency;
disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
...@@ -3537,13 +3546,20 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) ...@@ -3537,13 +3546,20 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
if (hwmgr->display_config->nb_pstate_switch_disable) if (hwmgr->display_config->nb_pstate_switch_disable)
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
if ((disable_mclk_switching &&
(dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||
hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
disable_fclk_switching = true;
else
disable_fclk_switching = false;
/* fclk */ /* fclk */
dpm_table = &(data->dpm_table.fclk_table); dpm_table = &(data->dpm_table.fclk_table);
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
if (hwmgr->display_config->nb_pstate_switch_disable) if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
/* vclk */ /* vclk */
......
...@@ -80,6 +80,7 @@ enum { ...@@ -80,6 +80,7 @@ enum {
GNLD_DS_MP1CLK, GNLD_DS_MP1CLK,
GNLD_DS_MP0CLK, GNLD_DS_MP0CLK,
GNLD_XGMI, GNLD_XGMI,
GNLD_ECC,
GNLD_FEATURES_MAX GNLD_FEATURES_MAX
}; };
......
...@@ -99,7 +99,7 @@ ...@@ -99,7 +99,7 @@
#define FEATURE_DS_MP1CLK_BIT 30 #define FEATURE_DS_MP1CLK_BIT 30
#define FEATURE_DS_MP0CLK_BIT 31 #define FEATURE_DS_MP0CLK_BIT 31
#define FEATURE_XGMI_BIT 32 #define FEATURE_XGMI_BIT 32
#define FEATURE_SPARE_33_BIT 33 #define FEATURE_ECC_BIT 33
#define FEATURE_SPARE_34_BIT 34 #define FEATURE_SPARE_34_BIT 34
#define FEATURE_SPARE_35_BIT 35 #define FEATURE_SPARE_35_BIT 35
#define FEATURE_SPARE_36_BIT 36 #define FEATURE_SPARE_36_BIT 36
...@@ -165,7 +165,8 @@ ...@@ -165,7 +165,8 @@
#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT ) #define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT ) #define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT ) #define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
#define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT ) #define FEATURE_XGMI_MASK (1ULL << FEATURE_XGMI_BIT )
#define FEATURE_ECC_MASK (1ULL << FEATURE_ECC_BIT )
#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 #define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
......
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