Commit 2e4c7588 authored by Dinh Nguyen's avatar Dinh Nguyen

ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk

The dbg_base_clk can also have osc1 has a parent.
Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent 7db85dd0
......@@ -164,7 +164,7 @@ mainclk: mainclk {
dbg_base_clk: dbg_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
clocks = <&main_pll>, <&osc1>;
div-reg = <0xe8 0 9>;
reg = <0x50>;
};
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment