[PATCH] ppc32: PPC44x MMU update/fixes

From: Matt Porter <mporter@kernel.crashing.org>

The following patch enhances and fixes a number of bugs in PPC44x MMU
handling.

arch/ppc/kernel/misc.S

@@ -406,17 +406,18 @@ _GLOBAL(_tlbia)
 	tlbia
 	isync			/* Flush shadow TLB */
 #elif defined(CONFIG_44x)
-	lis	r3,0
+	li	r3,0
 	sync
-1:
-	tlbwe	r3,r3,PPC44x_TLB_PAGEID
-	addi	r3,r3,1
+
 	/* Load high watermark */
-	lis	r4,tlb_44x_hwater@h
-	ori	r4,r4,tlb_44x_hwater@l
-	lwz	r5,0(r4)
+	lis	r4,tlb_44x_hwater@ha
+	lwz	r5,tlb_44x_hwater@l(r4)
+
+1:	tlbwe	r3,r3,PPC44x_TLB_PAGEID
+	addi	r3,r3,1
 	cmpw	0,r3,r5
 	ble	1b
+
 	isync
 #else /* !(CONFIG_40x || CONFIG_44x) */
 #if defined(CONFIG_SMP)
@@ -470,17 +471,10 @@ _GLOBAL(_tlbie)
 	isync
 10:
 #elif defined(CONFIG_44x)
-	mfspr	r4,SPRN_MMUCR			/* Get MMUCR */
-	lis	r5,PPC44x_MMUCR_STS@h
-	ori	r5,r5,PPC44x_MMUCR_TID@l	/* Create mask */
-	andc	r4,r4,r5			/* Clear out TID/STS bits */
+	mfspr	r4,SPRN_MMUCR
 	mfspr	r5,SPRN_PID			/* Get PID */
-	or	r4,r4,r5			/* Set TID bits */
-	mfmsr	r6				/* Get MSR */
-	andi.	r6,r6,MSR_IS@l			/* TS=1? */
-	beq	11f				/* If not, leave STS=0 */
-	oris	r4,r4,PPC44x_MMUCR_STS@h	/* Set STS=1 */
-11:	mtspr	SPRN_MMUCR, r4			/* Put MMUCR */
+	rlwimi	r4,r5,0,24,31			/* Set TID */
+	mtspr	SPRN_MMUCR,r4
 
 	tlbsx.	r3, 0, r3
 	bne	10f

arch/ppc/mm/44x_mmu.c

@@ -64,7 +64,7 @@ extern struct mem_pieces phys_avail;
  * Just needed it declared someplace.
  */
 unsigned int tlb_44x_index = 0;
-unsigned int tlb_44x_hwater = 61;
+unsigned int tlb_44x_hwater = 62;
 
 /*
  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
@@ -85,7 +85,7 @@ ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys)
 	tlbwe	%0,%3,%8"
 	:
 	: "r" (attrib), "r" (phys), "r" (virt), "r" (slot),
-	  "i" (PPC44x_TLB_VALID | PPC44x_TLB_PAGESZ(PPC44x_PAGESZ_256M)),
+	  "i" (PPC44x_TLB_VALID | PPC44x_TLB_256M),
 	  "i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
 	  "i" (PPC44x_TLB_PAGEID),
 	  "i" (PPC44x_TLB_XLAT),

include/asm-ppc/ibm44x.h

@@ -51,7 +51,7 @@ typedef struct board_info {
 #define PPC44x_PIN_SIZE		(1 << PPC44x_PIN_SHIFT)
 
 /* Lowest TLB slot consumed by the default pinned TLBs */
-#define PPC44x_LOW_SLOT		62
+#define PPC44x_LOW_SLOT		63
 
 /*
  * Standard 4GB "page" definitions

include/asm-ppc/mmu.h

@@ -346,16 +346,14 @@ typedef struct _P601_BAT {
 #define PPC44x_TLB_EPN_MASK	0xfffffc00      /* Effective Page Number */
 #define	PPC44x_TLB_VALID	0x00000200      /* Valid flag */
 #define PPC44x_TLB_TS		0x00000100	/* Translation address space */
-#define PPC44x_TLB_PAGESZ_MASK	0x000000f0
-#define PPC44x_TLB_PAGESZ(x)	(x << 4)
-#define PPC44x_PAGESZ_1K	0
-#define PPC44x_PAGESZ_4K	1
-#define PPC44x_PAGESZ_16K	2
-#define PPC44x_PAGESZ_64K	3
-#define PPC44x_PAGESZ_256K	4
-#define PPC44x_PAGESZ_1M	5
-#define PPC44x_PAGESZ_16M	7
-#define	PPC44x_PAGESZ_256M	9
+#define PPC44x_TLB_1K		0x00000000	/* Page sizes */
+#define PPC44x_TLB_4K		0x00000010
+#define PPC44x_TLB_16K		0x00000020
+#define PPC44x_TLB_64K		0x00000030
+#define PPC44x_TLB_256K		0x00000040
+#define PPC44x_TLB_1M		0x00000050
+#define PPC44x_TLB_16M		0x00000070
+#define	PPC44x_TLB_256M		0x00000090
 
 /* Translation fields */
 #define PPC44x_TLB_RPN_MASK	0xfffffc00      /* Real Page Number */

include/asm-ppc/pgtable.h

@@ -320,13 +320,13 @@ extern unsigned long ioremap_bot, ioremap_base;
  * another purpose.  -- paulus.
  */
 
+#ifdef CONFIG_44x
+#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
+#else
 #define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED)
+#endif
 #define _PAGE_WRENABLE	(_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
-#ifndef CONFIG_44x
 #define _PAGE_KERNEL	(_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
-#else
-#define _PAGE_KERNEL	(_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE | _PAGE_GUARDED)
-#endif
 
 #ifdef CONFIG_PPC_STD_MMU
 /* On standard PPC MMU, no user access implies kernel read/write access,

include/asm-ppc/reg_booke.h

@@ -47,7 +47,11 @@ do {						\
 #define MSR_DS		MSR_DR	/* Data Space */
 
 /* Default MSR for kernel mode. */
+#if defined (CONFIG_40x)
 #define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE|MSR_DE)
+#elif defined(CONFIG_BOOKE)
+#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_CE|MSR_DE)
+#endif
 
 /* Special Purpose Registers (SPRNs)*/
 #define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */