Commit 2e539b73 authored by Tom Rix's avatar Tom Rix Committed by Bartosz Golaszewski

gpio: tegra186: remove unneeded loop in tegra186_gpio_init_route_mapping()

Reviewing the j loop over num_irqs_per_bank, in the code previous
to the fixes: commit, every j was used. now only when j == 0.
If only j == 0 is used, there is no need for the loop.

Fixes: 21038680 ("gpio: tegra186: Support multiple interrupts per bank")
Signed-off-by: default avatarTom Rix <trix@redhat.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarBartosz Golaszewski <bartosz.golaszewski@linaro.org>
parent eed5a3bf
...@@ -677,7 +677,7 @@ static const struct of_device_id tegra186_pmc_of_match[] = { ...@@ -677,7 +677,7 @@ static const struct of_device_id tegra186_pmc_of_match[] = {
static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
{ {
struct device *dev = gpio->gpio.parent; struct device *dev = gpio->gpio.parent;
unsigned int i, j; unsigned int i;
u32 value; u32 value;
for (i = 0; i < gpio->soc->num_ports; i++) { for (i = 0; i < gpio->soc->num_ports; i++) {
...@@ -699,27 +699,23 @@ static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) ...@@ -699,27 +699,23 @@ static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
* On Tegra194 and later, each pin can be routed to one or more * On Tegra194 and later, each pin can be routed to one or more
* interrupts. * interrupts.
*/ */
for (j = 0; j < gpio->num_irqs_per_bank; j++) { dev_dbg(dev, "programming default interrupt routing for port %s\n",
dev_dbg(dev, "programming default interrupt routing for port %s\n", port->name);
port->name);
offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
/*
/* * By default we only want to route GPIO pins to IRQ 0. This works
* By default we only want to route GPIO pins to IRQ 0. This works * only under the assumption that we're running as the host kernel
* only under the assumption that we're running as the host kernel * and hence all GPIO pins are owned by Linux.
* and hence all GPIO pins are owned by Linux. *
* * For cases where Linux is the guest OS, the hypervisor will have
* For cases where Linux is the guest OS, the hypervisor will have * to configure the interrupt routing and pass only the valid
* to configure the interrupt routing and pass only the valid * interrupts via device tree.
* interrupts via device tree. */
*/ value = readl(base + offset);
if (j == 0) { value = BIT(port->pins) - 1;
value = readl(base + offset); writel(value, base + offset);
value = BIT(port->pins) - 1;
writel(value, base + offset);
}
}
} }
} }
} }
......
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