Commit 2eee83e8 authored by Jonathan Bakker's avatar Jonathan Bakker Committed by Greg Kroah-Hartman

phy: samsung: s5pv210-usb2: Add delay after reset

[ Upstream commit 05942b8c ]

The USB phy takes some time to reset, so make sure we give it to it. The
delay length was taken from the 4x12 phy driver.

This manifested in issues with the DWC2 driver since commit fe369e18
("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.")
where the endianness check would read the DWC ID as 0 due to the phy still
resetting, resulting in the wrong endian mode being chosen.
Signed-off-by: default avatarJonathan Bakker <xc-racer2@live.ca>
Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.comSigned-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 54d019cd
...@@ -142,6 +142,10 @@ static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on) ...@@ -142,6 +142,10 @@ static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
udelay(10); udelay(10);
rst &= ~rstbits; rst &= ~rstbits;
writel(rst, drv->reg_phy + S5PV210_UPHYRST); writel(rst, drv->reg_phy + S5PV210_UPHYRST);
/* The following delay is necessary for the reset sequence to be
* completed
*/
udelay(80);
} else { } else {
pwr = readl(drv->reg_phy + S5PV210_UPHYPWR); pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
pwr |= phypwr; pwr |= phypwr;
......
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