Commit 2ef6b06a authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi

PCI: dwc: Simplify config space handling

The config space is divided in half for type 0 and type 1 accesses, but
this is pointless as there's only one iATU window which is
reconfigured on each access.

The only platform doing something custom is TI Keystone (surprise!).
It does its own mapping of the config space to avoid spliting the
config space and never actually uses va_cfg1_base as it has its own
config space accessors. With the splitting removed, Keystone can use the
default mapping of config space.

Link: https://lore.kernel.org/r/20200821035420.380495-20-robh@kernel.orgSigned-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
parent 0f71c60f
...@@ -873,16 +873,8 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, ...@@ -873,16 +873,8 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie,
struct dw_pcie *pci = ks_pcie->pci; struct dw_pcie *pci = ks_pcie->pci;
struct pcie_port *pp = &pci->pp; struct pcie_port *pp = &pci->pp;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
struct resource *res;
int ret; int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
if (IS_ERR(pp->va_cfg0_base))
return PTR_ERR(pp->va_cfg0_base);
pp->va_cfg1_base = pp->va_cfg0_base;
ret = dw_pcie_host_init(pp); ret = dw_pcie_host_init(pp);
if (ret) { if (ret) {
dev_err(dev, "failed to initialize host\n"); dev_err(dev, "failed to initialize host\n");
......
...@@ -308,10 +308,8 @@ int dw_pcie_host_init(struct pcie_port *pp) ...@@ -308,10 +308,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
if (cfg_res) { if (cfg_res) {
pp->cfg0_size = resource_size(cfg_res) >> 1; pp->cfg0_size = resource_size(cfg_res);
pp->cfg1_size = resource_size(cfg_res) >> 1;
pp->cfg0_base = cfg_res->start; pp->cfg0_base = cfg_res->start;
pp->cfg1_base = cfg_res->start + pp->cfg0_size;
} else if (!pp->va_cfg0_base) { } else if (!pp->va_cfg0_base) {
dev_err(dev, "Missing *config* reg space\n"); dev_err(dev, "Missing *config* reg space\n");
} }
...@@ -331,25 +329,22 @@ int dw_pcie_host_init(struct pcie_port *pp) ...@@ -331,25 +329,22 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->io_base = pci_pio_to_address(win->res->start); pp->io_base = pci_pio_to_address(win->res->start);
break; break;
case 0: case 0:
pp->cfg = win->res; dev_err(dev, "Missing *config* reg space\n");
pp->cfg0_size = resource_size(pp->cfg) >> 1; pp->cfg0_size = resource_size(win->res);
pp->cfg1_size = resource_size(pp->cfg) >> 1; pp->cfg0_base = win->res->start;
pp->cfg0_base = pp->cfg->start; if (!pci->dbi_base) {
pp->cfg1_base = pp->cfg->start + pp->cfg0_size; pci->dbi_base = devm_pci_remap_cfgspace(dev,
pp->cfg0_base,
pp->cfg0_size);
if (!pci->dbi_base) {
dev_err(dev, "Error with ioremap\n");
return -ENOMEM;
}
}
break; break;
} }
} }
if (!pci->dbi_base) {
pci->dbi_base = devm_pci_remap_cfgspace(dev,
pp->cfg->start,
resource_size(pp->cfg));
if (!pci->dbi_base) {
dev_err(dev, "Error with ioremap\n");
return -ENOMEM;
}
}
if (!pp->va_cfg0_base) { if (!pp->va_cfg0_base) {
pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
pp->cfg0_base, pp->cfg0_size); pp->cfg0_base, pp->cfg0_size);
...@@ -359,16 +354,6 @@ int dw_pcie_host_init(struct pcie_port *pp) ...@@ -359,16 +354,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
} }
} }
if (!pp->va_cfg1_base) {
pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
pp->cfg1_base,
pp->cfg1_size);
if (!pp->va_cfg1_base) {
dev_err(dev, "Error with ioremap\n");
return -ENOMEM;
}
}
ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
if (ret) if (ret)
pci->num_viewport = 2; pci->num_viewport = 2;
...@@ -446,32 +431,24 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, ...@@ -446,32 +431,24 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
unsigned int devfn, int where) unsigned int devfn, int where)
{ {
int type; int type;
u32 busdev, cfg_size; u32 busdev;
u64 cpu_addr;
void __iomem *va_cfg_base;
struct pcie_port *pp = bus->sysdata; struct pcie_port *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn)); PCIE_ATU_FUNC(PCI_FUNC(devfn));
if (pci_is_root_bus(bus->parent)) { if (pci_is_root_bus(bus->parent))
type = PCIE_ATU_TYPE_CFG0; type = PCIE_ATU_TYPE_CFG0;
cpu_addr = pp->cfg0_base; else
cfg_size = pp->cfg0_size;
va_cfg_base = pp->va_cfg0_base;
} else {
type = PCIE_ATU_TYPE_CFG1; type = PCIE_ATU_TYPE_CFG1;
cpu_addr = pp->cfg1_base;
cfg_size = pp->cfg1_size;
va_cfg_base = pp->va_cfg1_base;
}
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
type, cpu_addr, type, pp->cfg0_base,
busdev, cfg_size); busdev, pp->cfg0_size);
return va_cfg_base + where; return pp->va_cfg0_base + where;
} }
static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
......
...@@ -169,13 +169,9 @@ struct pcie_port { ...@@ -169,13 +169,9 @@ struct pcie_port {
u64 cfg0_base; u64 cfg0_base;
void __iomem *va_cfg0_base; void __iomem *va_cfg0_base;
u32 cfg0_size; u32 cfg0_size;
u64 cfg1_base;
void __iomem *va_cfg1_base;
u32 cfg1_size;
resource_size_t io_base; resource_size_t io_base;
phys_addr_t io_bus_addr; phys_addr_t io_bus_addr;
u32 io_size; u32 io_size;
struct resource *cfg;
int irq; int irq;
const struct dw_pcie_host_ops *ops; const struct dw_pcie_host_ops *ops;
int msi_irq; int msi_irq;
......
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