Commit 30e4247e authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Simon Horman

sh-pfc: r8a7790: Remove GPIO data

GPIOs are now handled by a separate driver, remove GPIO data from the
SoC information structure.
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 45c6c85d
......@@ -52,32 +52,12 @@
CPU_32_PORT(fn, pfx##_5_, sfx) \
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
GP##pfx##_IN, GP##pfx##_OUT)
#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN)
#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
#define PORT_10_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
#define CPU_32_PORT_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
PORT_10_REV(fn, pfx, sfx)
#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
......@@ -89,14 +69,6 @@ enum {
GP_ALL(DATA),
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
GP_ALL(IN),
PINMUX_INPUT_END,
PINMUX_OUTPUT_BEGIN,
GP_ALL(OUT),
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
......@@ -3824,106 +3796,6 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_I2C1 [2] */
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
},
{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
0, 0,
0, 0,
GP_1_29_IN, GP_1_29_OUT,
GP_1_28_IN, GP_1_28_OUT,
GP_1_27_IN, GP_1_27_OUT,
GP_1_26_IN, GP_1_26_OUT,
GP_1_25_IN, GP_1_25_OUT,
GP_1_24_IN, GP_1_24_OUT,
GP_1_23_IN, GP_1_23_OUT,
GP_1_22_IN, GP_1_22_OUT,
GP_1_21_IN, GP_1_21_OUT,
GP_1_20_IN, GP_1_20_OUT,
GP_1_19_IN, GP_1_19_OUT,
GP_1_18_IN, GP_1_18_OUT,
GP_1_17_IN, GP_1_17_OUT,
GP_1_16_IN, GP_1_16_OUT,
GP_1_15_IN, GP_1_15_OUT,
GP_1_14_IN, GP_1_14_OUT,
GP_1_13_IN, GP_1_13_OUT,
GP_1_12_IN, GP_1_12_OUT,
GP_1_11_IN, GP_1_11_OUT,
GP_1_10_IN, GP_1_10_OUT,
GP_1_9_IN, GP_1_9_OUT,
GP_1_8_IN, GP_1_8_OUT,
GP_1_7_IN, GP_1_7_OUT,
GP_1_6_IN, GP_1_6_OUT,
GP_1_5_IN, GP_1_5_OUT,
GP_1_4_IN, GP_1_4_OUT,
GP_1_3_IN, GP_1_3_OUT,
GP_1_2_IN, GP_1_2_OUT,
GP_1_1_IN, GP_1_1_OUT,
GP_1_0_IN, GP_1_0_OUT, }
},
{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
0, 0,
0, 0,
GP_2_29_IN, GP_2_29_OUT,
GP_2_28_IN, GP_2_28_OUT,
GP_2_27_IN, GP_2_27_OUT,
GP_2_26_IN, GP_2_26_OUT,
GP_2_25_IN, GP_2_25_OUT,
GP_2_24_IN, GP_2_24_OUT,
GP_2_23_IN, GP_2_23_OUT,
GP_2_22_IN, GP_2_22_OUT,
GP_2_21_IN, GP_2_21_OUT,
GP_2_20_IN, GP_2_20_OUT,
GP_2_19_IN, GP_2_19_OUT,
GP_2_18_IN, GP_2_18_OUT,
GP_2_17_IN, GP_2_17_OUT,
GP_2_16_IN, GP_2_16_OUT,
GP_2_15_IN, GP_2_15_OUT,
GP_2_14_IN, GP_2_14_OUT,
GP_2_13_IN, GP_2_13_OUT,
GP_2_12_IN, GP_2_12_OUT,
GP_2_11_IN, GP_2_11_OUT,
GP_2_10_IN, GP_2_10_OUT,
GP_2_9_IN, GP_2_9_OUT,
GP_2_8_IN, GP_2_8_OUT,
GP_2_7_IN, GP_2_7_OUT,
GP_2_6_IN, GP_2_6_OUT,
GP_2_5_IN, GP_2_5_OUT,
GP_2_4_IN, GP_2_4_OUT,
GP_2_3_IN, GP_2_3_OUT,
GP_2_2_IN, GP_2_2_OUT,
GP_2_1_IN, GP_2_1_OUT,
GP_2_0_IN, GP_2_0_OUT, }
},
{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
{ },
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("INDT0", 0xE605000C, 32) { GP_INDT(0) } },
{ PINMUX_DATA_REG("INDT1", 0xE605100C, 32) {
0, 0, GP_1_29_DATA, GP_1_28_DATA,
GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
},
{ PINMUX_DATA_REG("INDT2", 0xE605200C, 32) {
0, 0, GP_2_29_DATA, GP_2_28_DATA,
GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
},
{ PINMUX_DATA_REG("INDT3", 0xE605300C, 32) { GP_INDT(3) } },
{ PINMUX_DATA_REG("INDT4", 0xE605400C, 32) { GP_INDT(4) } },
{ PINMUX_DATA_REG("INDT5", 0xE605500C, 32) { GP_INDT(5) } },
{ },
};
......@@ -3931,8 +3803,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.name = "r8a77900_pfc",
.unlock_reg = 0xe6060000, /* PMMR */
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
......@@ -3946,7 +3816,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
......
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