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Commit 3215501f authored by Charles Keepax's avatar Charles Keepax Committed by Lee Jones
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mfd: wm5110: Add new interrupt register definitions 

Newer versions of the IP have a lot of new interrupts and move several
existing interrupts. This patch adds the register definitions and regmap
hookup for these interrupts.
Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
parent c0fe2c5b
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Showing with 827 additions and 3 deletions
drivers/mfd/arizona-irq.c
View file @ 3215501f
......@@ -203,7 +203,15 @@ int arizona_irq_init(struct arizona *arizona)
#ifdef CONFIG_MFD_WM5110
case WM5110:
aod = &wm5110_aod;
irq = &wm5110_irq;
switch (arizona->rev) {
case 0 ... 2:
irq = &wm5110_irq;
break;
default:
irq = &wm5110_revd_irq;
break;
}
ctrlif_error = false;
break;
......
drivers/mfd/arizona.h
View file @ 3215501f
......@@ -36,6 +36,7 @@ extern const struct regmap_irq_chip wm5102_irq;
extern const struct regmap_irq_chip wm5110_aod;
extern const struct regmap_irq_chip wm5110_irq;
extern const struct regmap_irq_chip wm5110_revd_irq;
extern const struct regmap_irq_chip wm8997_aod;
extern const struct regmap_irq_chip wm8997_irq;
......
drivers/mfd/wm5110-tables.c
View file @ 3215501f
......@@ -457,6 +457,209 @@ const struct regmap_irq_chip wm5110_irq = {
};
EXPORT_SYMBOL_GPL(wm5110_irq);
static const struct regmap_irq wm5110_revd_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_DSP4_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP3_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP2_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP1_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP_IRQ8] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
},
[ARIZONA_IRQ_DSP_IRQ7] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
},
[ARIZONA_IRQ_DSP_IRQ6] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
},
[ARIZONA_IRQ_DSP_IRQ5] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
},
[ARIZONA_IRQ_DSP_IRQ4] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
},
[ARIZONA_IRQ_DSP_IRQ3] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
},
[ARIZONA_IRQ_DSP_IRQ2] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
},
[ARIZONA_IRQ_DSP_IRQ1] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_HPDET] = {
.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
},
[ARIZONA_IRQ_MICDET] = {
.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC2_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_ASRC2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
},
[ARIZONA_IRQ_ASRC1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC3_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1
},
[ARIZONA_IRQ_HP3R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1
},
[ARIZONA_IRQ_HP3L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1
},
[ARIZONA_IRQ_HP2R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1
},
[ARIZONA_IRQ_HP2L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1
},
[ARIZONA_IRQ_HP1R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1
},
[ARIZONA_IRQ_HP1L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_ASRC_CFG_ERR] = {
.reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_DSP_SHARED_WR_COLL] = {
.reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1
},
[ARIZONA_IRQ_SPK_SHUTDOWN] = {
.reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1
},
[ARIZONA_IRQ_SPK1R_SHORT] = {
.reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1
},
[ARIZONA_IRQ_SPK1L_SHORT] = {
.reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1
},
[ARIZONA_IRQ_HP3R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP3R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP3R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP3R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP3L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP3L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP3L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP3L_SC_POS_EINT1
},
[ARIZONA_IRQ_HP2R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP2R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP2R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP2R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP2L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP2L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP2L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP2L_SC_POS_EINT1
},
[ARIZONA_IRQ_HP1R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP1R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP1R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP1L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP1L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP1L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1
},
};
const struct regmap_irq_chip wm5110_revd_irq = {
.name = "wm5110 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 6,
.irqs = wm5110_revd_irqs,
.num_irqs = ARRAY_SIZE(wm5110_revd_irqs),
};
EXPORT_SYMBOL_GPL(wm5110_revd_irq);
static const struct reg_default wm5110_reg_default[] = {
{ 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
{ 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
......@@ -1286,12 +1489,14 @@ static const struct reg_default wm5110_reg_default[] = {
{ 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
{ 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */
{ 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */
{ 0x00000D0D, 0xFFFF }, /* R3341 - Interrupt Status 6 Mask */
{ 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
{ 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */
{ 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */
{ 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */
{ 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
{ 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */
{ 0x00000D1D, 0xFFFF }, /* R3357 - IRQ2 Status 6 Mask */
{ 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
{ 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
{ 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
......@@ -2323,22 +2528,26 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_6:
case ARIZONA_INTERRUPT_STATUS_1_MASK:
case ARIZONA_INTERRUPT_STATUS_2_MASK:
case ARIZONA_INTERRUPT_STATUS_3_MASK:
case ARIZONA_INTERRUPT_STATUS_4_MASK:
case ARIZONA_INTERRUPT_STATUS_5_MASK:
case ARIZONA_INTERRUPT_STATUS_6_MASK:
case ARIZONA_INTERRUPT_CONTROL:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_6:
case ARIZONA_IRQ2_STATUS_1_MASK:
case ARIZONA_IRQ2_STATUS_2_MASK:
case ARIZONA_IRQ2_STATUS_3_MASK:
case ARIZONA_IRQ2_STATUS_4_MASK:
case ARIZONA_IRQ2_STATUS_5_MASK:
case ARIZONA_IRQ2_STATUS_6_MASK:
case ARIZONA_IRQ2_CONTROL:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
......@@ -2347,6 +2556,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_INTERRUPT_RAW_STATUS_9:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
......@@ -2622,11 +2832,13 @@ static bool wm5110_volatile_register(struct device *dev, unsigned int reg)
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_6:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
......@@ -2634,6 +2846,7 @@ static bool wm5110_volatile_register(struct device *dev, unsigned int reg)
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_INTERRUPT_RAW_STATUS_9:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
......
include/linux/mfd/arizona/core.h
View file @ 3215501f
......@@ -84,8 +84,25 @@ enum arizona_type {
#define ARIZONA_IRQ_HP2L_DONE 55
#define ARIZONA_IRQ_HP1R_DONE 56
#define ARIZONA_IRQ_HP1L_DONE 57
#define ARIZONA_NUM_IRQ 58
#define ARIZONA_IRQ_ISRC3_CFG_ERR 58
#define ARIZONA_IRQ_DSP_SHARED_WR_COLL 59
#define ARIZONA_IRQ_SPK_SHUTDOWN 60
#define ARIZONA_IRQ_SPK1R_SHORT 61
#define ARIZONA_IRQ_SPK1L_SHORT 62
#define ARIZONA_IRQ_HP3R_SC_NEG 63
#define ARIZONA_IRQ_HP3R_SC_POS 64
#define ARIZONA_IRQ_HP3L_SC_NEG 65
#define ARIZONA_IRQ_HP3L_SC_POS 66
#define ARIZONA_IRQ_HP2R_SC_NEG 67
#define ARIZONA_IRQ_HP2R_SC_POS 68
#define ARIZONA_IRQ_HP2L_SC_NEG 69
#define ARIZONA_IRQ_HP2L_SC_POS 70
#define ARIZONA_IRQ_HP1R_SC_NEG 71
#define ARIZONA_IRQ_HP1R_SC_POS 72
#define ARIZONA_IRQ_HP1L_SC_NEG 73
#define ARIZONA_IRQ_HP1L_SC_POS 74
#define ARIZONA_NUM_IRQ 75
struct snd_soc_dapm_context;
......
include/linux/mfd/arizona/registers.h
View file @ 3215501f
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