Commit 3225de1b authored by Rui Miguel Silva's avatar Rui Miguel Silva Committed by Rob Herring

dt-bindings: net: smsc,lan91c111 convert to schema

Convert the smsc lan91c9x and lan91c1xx controller device tree
bindings documentation to json-schema.
Signed-off-by: default avatarRui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220331154536.1544220-2-rui.silva@linaro.org
parent a1a2b712
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
maintainers:
- Nicolas Pitre <nico@fluxnic.net>
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
const: smsc,lan91c111
reg:
maxItems: 1
interrupts:
maxItems: 1
reg-shift: true
reg-io-width:
enum: [ 1, 2, 4 ]
default: 4
reset-gpios:
description: GPIO connected to control RESET pin
maxItems: 1
power-gpios:
description: GPIO connect to control PWRDWN pin
maxItems: 1
pxa-u16-align4:
description: put in place the workaround the force all u16 writes to be
32 bits aligned
type: boolean
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
ethernet@4010000 {
compatible = "smsc,lan91c111";
reg = <0x40100000 0x10000>;
phy-mode = "mii";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <2>;
};
SMSC LAN91c111 Ethernet mac
Required properties:
- compatible = "smsc,lan91c111";
- reg : physical address and size of registers
- interrupts : interrupt connection
Optional properties:
- phy-device : see ethernet.txt file in the same directory
- reg-io-width : Mask of sizes (in bytes) of the IO accesses that
are supported on the device. Valid value for SMSC LAN91c111 are
1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning
16-bit access only.
- power-gpios: GPIO to control the PWRDWN pin
- reset-gpios: GPIO to control the RESET pin
- pxa-u16-align4 : Boolean, put in place the workaround the force all
u16 writes to be 32 bits aligned
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