Commit 33e141ed authored by arun.siluvery@linux.intel.com's avatar arun.siluvery@linux.intel.com Committed by Tvrtko Ursulin

drm/i915:bxt: Enable Pooled EU support

This mode allows to assign EUs to pools which can process work collectively.
The command to enable this mode should be issued as part of context initialization.

The pooled mode is global, once enabled it has to stay the same across all
contexts until HW reset hence this is sent in auxiliary golden context batch.
Thanks to Mika for the preliminary review and comments.

v2: explain why this is enabled in golden context, use feature flag while
enabling the support (Chris)

v3: Include only kernel support as userspace support is not available yet.

User space clients need to know when the pooled EU feature is present
and enabled on the hardware so that they can adapt work submissions.
Create a new device info flag for this purpose.

Set has_pooled_eu to true in the Broxton static device info - Broxton
supports the feature in hardware and the driver will enable it by
default.

We need to add getparam ioctls to enable userspace to query availability of
this feature and to retrieve min. no of eus in a pool but we will expose
them once userspace support is available. Opensource users for this feature
are mesa, libva and beignet.

Beignet team is currently working on adding userspace support.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
Cc: Winiarski, Michal <michal.winiarski@intel.com>
Cc: Zou, Nanhai <nanhai.zou@intel.com>
Cc: Yang, Rong R <rong.r.yang@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Armin Reese <armin.c.reese@intel.com>
Cc: Tim Gore <tim.gore@intel.com>
Signed-off-by: default avatarJeff McGee <jeff.mcgee@intel.com>
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent beffa517
...@@ -5306,6 +5306,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused) ...@@ -5306,6 +5306,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
INTEL_INFO(dev)->eu_total); INTEL_INFO(dev)->eu_total);
seq_printf(m, " Available EU Per Subslice: %u\n", seq_printf(m, " Available EU Per Subslice: %u\n",
INTEL_INFO(dev)->eu_per_subslice); INTEL_INFO(dev)->eu_per_subslice);
seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
if (HAS_POOLED_EU(dev))
seq_printf(m, " Min EU in pool: %u\n",
INTEL_INFO(dev)->min_eu_in_pool);
seq_printf(m, " Has Slice Power Gating: %s\n", seq_printf(m, " Has Slice Power Gating: %s\n",
yesno(INTEL_INFO(dev)->has_slice_pg)); yesno(INTEL_INFO(dev)->has_slice_pg));
seq_printf(m, " Has Subslice Power Gating: %s\n", seq_printf(m, " Has Subslice Power Gating: %s\n",
......
...@@ -764,6 +764,22 @@ static void gen9_sseu_info_init(struct drm_device *dev) ...@@ -764,6 +764,22 @@ static void gen9_sseu_info_init(struct drm_device *dev)
(info->slice_total > 1)); (info->slice_total > 1));
info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
info->has_eu_pg = (info->eu_per_subslice > 2); info->has_eu_pg = (info->eu_per_subslice > 2);
if (IS_BROXTON(dev)) {
#define IS_SS_DISABLED(_ss_disable, ss) (_ss_disable & (0x1 << ss))
info->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
if (IS_SS_DISABLED(ss_disable, 0) ||
IS_SS_DISABLED(ss_disable, 2))
info->min_eu_in_pool = 3;
else if (IS_SS_DISABLED(ss_disable, 1))
info->min_eu_in_pool = 6;
else
info->min_eu_in_pool = 9;
}
#undef IS_SS_DISABLED
}
} }
static void broadwell_sseu_info_init(struct drm_device *dev) static void broadwell_sseu_info_init(struct drm_device *dev)
...@@ -962,6 +978,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev) ...@@ -962,6 +978,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total); DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice); DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
DRM_DEBUG_DRIVER("Has Pooled EU: %s\n", HAS_POOLED_EU(dev) ? "y" : "n");
if (HAS_POOLED_EU(dev))
DRM_DEBUG_DRIVER("Min EU in pool: %u\n", info->min_eu_in_pool);
DRM_DEBUG_DRIVER("has slice power gating: %s\n", DRM_DEBUG_DRIVER("has slice power gating: %s\n",
info->has_slice_pg ? "y" : "n"); info->has_slice_pg ? "y" : "n");
DRM_DEBUG_DRIVER("has subslice power gating: %s\n", DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
......
...@@ -355,6 +355,7 @@ static const struct intel_device_info intel_broxton_info = { ...@@ -355,6 +355,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_ddi = 1, .has_ddi = 1,
.has_fpga_dbg = 1, .has_fpga_dbg = 1,
.has_fbc = 1, .has_fbc = 1,
.has_pooled_eu = 1,
GEN_DEFAULT_PIPEOFFSETS, GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS, IVB_CURSOR_OFFSETS,
BDW_COLORS, BDW_COLORS,
......
...@@ -761,7 +761,8 @@ struct intel_csr { ...@@ -761,7 +761,8 @@ struct intel_csr {
func(has_llc) sep \ func(has_llc) sep \
func(has_snoop) sep \ func(has_snoop) sep \
func(has_ddi) sep \ func(has_ddi) sep \
func(has_fpga_dbg) func(has_fpga_dbg) sep \
func(has_pooled_eu)
#define DEFINE_FLAG(name) u8 name:1 #define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ; #define SEP_SEMICOLON ;
...@@ -787,6 +788,7 @@ struct intel_device_info { ...@@ -787,6 +788,7 @@ struct intel_device_info {
u8 subslice_per_slice; u8 subslice_per_slice;
u8 eu_total; u8 eu_total;
u8 eu_per_subslice; u8 eu_per_subslice;
u8 min_eu_in_pool;
/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
u8 subslice_7eu[3]; u8 subslice_7eu[3];
u8 has_slice_pg:1; u8 has_slice_pg:1;
...@@ -2832,6 +2834,8 @@ struct drm_i915_cmd_table { ...@@ -2832,6 +2834,8 @@ struct drm_i915_cmd_table {
!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
!IS_BROXTON(dev)) !IS_BROXTON(dev))
#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
#define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
......
...@@ -94,6 +94,7 @@ static int render_state_init(struct render_state *so, ...@@ -94,6 +94,7 @@ static int render_state_init(struct render_state *so,
static int render_state_setup(struct render_state *so) static int render_state_setup(struct render_state *so)
{ {
struct drm_device *dev = so->obj->base.dev;
const struct intel_renderstate_rodata *rodata = so->rodata; const struct intel_renderstate_rodata *rodata = so->rodata;
unsigned int i = 0, reloc_index = 0; unsigned int i = 0, reloc_index = 0;
struct page *page; struct page *page;
...@@ -135,6 +136,33 @@ static int render_state_setup(struct render_state *so) ...@@ -135,6 +136,33 @@ static int render_state_setup(struct render_state *so)
so->aux_batch_offset = i * sizeof(u32); so->aux_batch_offset = i * sizeof(u32);
if (HAS_POOLED_EU(dev)) {
/*
* We always program 3x6 pool config but depending upon which
* subslice is disabled HW drops down to appropriate config
* shown below.
*
* In the below table 2x6 config always refers to
* fused-down version, native 2x6 is not available and can
* be ignored
*
* SNo subslices config eu pool configuration
* -----------------------------------------------------------
* 1 3 subslices enabled (3x6) - 0x00777000 (9+9)
* 2 ss0 disabled (2x6) - 0x00777000 (3+9)
* 3 ss1 disabled (2x6) - 0x00770000 (6+6)
* 4 ss2 disabled (2x6) - 0x00007000 (9+3)
*/
u32 eu_pool_config = 0x00777000;
OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
OUT_BATCH(d, i, eu_pool_config);
OUT_BATCH(d, i, 0);
OUT_BATCH(d, i, 0);
OUT_BATCH(d, i, 0);
}
OUT_BATCH(d, i, MI_BATCH_BUFFER_END); OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
......
...@@ -445,6 +445,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) ...@@ -445,6 +445,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
*/ */
#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
#define GEN9_MEDIA_POOL_ENABLE (1 << 31)
#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define SC_UPDATE_SCISSOR (0x1<<1) #define SC_UPDATE_SCISSOR (0x1<<1)
......
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