Commit 33e88286 authored by Saleemkhan Jamadar's avatar Saleemkhan Jamadar Committed by Alex Deucher

Revert "drm/amdgpu:update kernel vcn ring test"

VCN FW depncencies revert it to unblock others

This reverts commit f3fa86f5.
Signed-off-by: default avatarSaleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: default avatarVeerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 093b21f4
...@@ -573,15 +573,13 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand ...@@ -573,15 +573,13 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
int r, i; int r, i;
memset(ib, 0, sizeof(*ib)); memset(ib, 0, sizeof(*ib));
/* 34 pages : 128KiB session context buffer size and 8KiB ib msg */ r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 34,
AMDGPU_IB_POOL_DIRECT, AMDGPU_IB_POOL_DIRECT,
ib); ib);
if (r) if (r)
return r; return r;
msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
memset(msg, 0, (AMDGPU_GPU_PAGE_SIZE * 34));
msg[0] = cpu_to_le32(0x00000028); msg[0] = cpu_to_le32(0x00000028);
msg[1] = cpu_to_le32(0x00000038); msg[1] = cpu_to_le32(0x00000038);
msg[2] = cpu_to_le32(0x00000001); msg[2] = cpu_to_le32(0x00000001);
...@@ -610,15 +608,13 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han ...@@ -610,15 +608,13 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
int r, i; int r, i;
memset(ib, 0, sizeof(*ib)); memset(ib, 0, sizeof(*ib));
/* 34 pages : 128KiB session context buffer size and 8KiB ib msg */ r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 34,
AMDGPU_IB_POOL_DIRECT, AMDGPU_IB_POOL_DIRECT,
ib); ib);
if (r) if (r)
return r; return r;
msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
memset(msg, 0, (AMDGPU_GPU_PAGE_SIZE * 34));
msg[0] = cpu_to_le32(0x00000028); msg[0] = cpu_to_le32(0x00000028);
msg[1] = cpu_to_le32(0x00000018); msg[1] = cpu_to_le32(0x00000018);
msg[2] = cpu_to_le32(0x00000000); msg[2] = cpu_to_le32(0x00000000);
...@@ -704,7 +700,6 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, ...@@ -704,7 +700,6 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
struct amdgpu_job *job; struct amdgpu_job *job;
struct amdgpu_ib *ib; struct amdgpu_ib *ib;
uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
uint64_t session_ctx_buf_gaddr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr + 8192);
bool sq = amdgpu_vcn_using_unified_queue(ring); bool sq = amdgpu_vcn_using_unified_queue(ring);
uint32_t *ib_checksum; uint32_t *ib_checksum;
uint32_t ib_pack_in_dw; uint32_t ib_pack_in_dw;
...@@ -735,10 +730,6 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, ...@@ -735,10 +730,6 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
decode_buffer->valid_buf_flag |=
cpu_to_le32(AMDGPU_VCN_CMD_FLAG_SESSION_CONTEXT_BUFFER);
decode_buffer->session_context_buffer_address_hi = upper_32_bits(session_ctx_buf_gaddr);
decode_buffer->session_context_buffer_address_lo = lower_32_bits(session_ctx_buf_gaddr);
decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32); decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
......
...@@ -171,7 +171,6 @@ ...@@ -171,7 +171,6 @@
#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
#define AMDGPU_VCN_CMD_FLAG_SESSION_CONTEXT_BUFFER 0x00100000
#define VCN_CODEC_DISABLE_MASK_AV1 (1 << 0) #define VCN_CODEC_DISABLE_MASK_AV1 (1 << 0)
#define VCN_CODEC_DISABLE_MASK_VP9 (1 << 1) #define VCN_CODEC_DISABLE_MASK_VP9 (1 << 1)
...@@ -367,9 +366,7 @@ struct amdgpu_vcn_decode_buffer { ...@@ -367,9 +366,7 @@ struct amdgpu_vcn_decode_buffer {
uint32_t valid_buf_flag; uint32_t valid_buf_flag;
uint32_t msg_buffer_address_hi; uint32_t msg_buffer_address_hi;
uint32_t msg_buffer_address_lo; uint32_t msg_buffer_address_lo;
uint32_t session_context_buffer_address_hi; uint32_t pad[30];
uint32_t session_context_buffer_address_lo;
uint32_t pad[28];
}; };
#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80 #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
......
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