Commit 3402a63d authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'imx-dt64-4.9' of...

Merge tag 'imx-dt64-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

Pull "i.MX arm64 device tree changes for 4.9" from Shawn Guo:
 - Add property dma-coherent for ls2080a PCI device to save software
   cache maintenance.
 - Update serial aliases and use stdout-path to sepecify console for
   ls2080a and ls1043a boards.
 - Add DDR memory controller device node for ls2080a and ls1043a SoCs.

* tag 'imx-dt64-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: ls2080a: Add 'dma-coherent' for ls2080a PCI nodes
  arm64: dts: add stdout-path to chosen node for ls2080a/ls1043a boards
  arm64: dts: updates serial aliases for ls1043a rdb and qds boards
  arm64: dts: Add DDR memory controller for Layerscape SoCs
parents 736ad004 e5f51a62
......@@ -56,12 +56,14 @@ aliases {
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
serial4 = &lpuart4;
serial5 = &lpuart5;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
......
......@@ -52,6 +52,14 @@ / {
aliases {
crypto = &crypto;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
......
......@@ -247,6 +247,13 @@ esdhc: esdhc@1560000 {
bus-width = <4>;
};
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <0 144 0x4>;
big-endian;
};
dspi0: dspi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
......
......@@ -57,6 +57,9 @@ aliases {
serial1 = &serial1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&esdhc {
......
......@@ -56,6 +56,10 @@ aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&esdhc {
......
......@@ -588,6 +588,7 @@ pcie@3400000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
......@@ -612,6 +613,7 @@ pcie@3500000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
......@@ -636,6 +638,7 @@ pcie@3600000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
......@@ -660,6 +663,7 @@ pcie@3700000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
......@@ -715,4 +719,18 @@ ccn@4000000 {
interrupts = <0 12 4>;
};
};
ddr1: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <0 17 0x4>;
little-endian;
};
ddr2: memory-controller@1090000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1090000 0x0 0x1000>;
interrupts = <0 18 0x4>;
little-endian;
};
};
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