Commit 34269839 authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher

drm/amdgpu: abstract TLB initialization for gfxhub/mmhub

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fc4b884b
...@@ -114,6 +114,27 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) ...@@ -114,6 +114,27 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp); WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
} }
static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
{
uint32_t tmp;
/* Setup TLB control */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
ENABLE_ADVANCED_DRIVER_MODEL, 1);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
MTYPE, MTYPE_UC);/* XXX for emulation. */
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
}
int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
{ {
u32 tmp; u32 tmp;
...@@ -131,35 +152,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) ...@@ -131,35 +152,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
/* GART Enable. */ /* GART Enable. */
gfxhub_v1_0_init_gart_aperture_regs(adev); gfxhub_v1_0_init_gart_aperture_regs(adev);
gfxhub_v1_0_init_system_aperture_regs(adev); gfxhub_v1_0_init_system_aperture_regs(adev);
gfxhub_v1_0_init_tlb_regs(adev);
/* Setup TLB control */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
tmp = REG_SET_FIELD(tmp,
MC_VM_MX_L1_TLB_CNTL,
SYSTEM_ACCESS_MODE,
3);
tmp = REG_SET_FIELD(tmp,
MC_VM_MX_L1_TLB_CNTL,
ENABLE_ADVANCED_DRIVER_MODEL,
1);
tmp = REG_SET_FIELD(tmp,
MC_VM_MX_L1_TLB_CNTL,
SYSTEM_APERTURE_UNMAPPED_ACCESS,
0);
tmp = REG_SET_FIELD(tmp,
MC_VM_MX_L1_TLB_CNTL,
ECO_BITS,
0);
tmp = REG_SET_FIELD(tmp,
MC_VM_MX_L1_TLB_CNTL,
MTYPE,
MTYPE_UC);/* XXX for emulation. */
tmp = REG_SET_FIELD(tmp,
MC_VM_MX_L1_TLB_CNTL,
ATC_EN,
1);
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
/* Setup L2 cache */ /* Setup L2 cache */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL)); tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
......
...@@ -125,6 +125,27 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) ...@@ -125,6 +125,27 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp); WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
} }
static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
{
uint32_t tmp;
/* Setup TLB control */
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
ENABLE_ADVANCED_DRIVER_MODEL, 1);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
MTYPE, MTYPE_UC);/* XXX for emulation. */
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
}
int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
{ {
u32 tmp; u32 tmp;
...@@ -143,6 +164,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) ...@@ -143,6 +164,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
/* GART Enable. */ /* GART Enable. */
mmhub_v1_0_init_gart_aperture_regs(adev); mmhub_v1_0_init_gart_aperture_regs(adev);
mmhub_v1_0_init_system_aperture_regs(adev); mmhub_v1_0_init_system_aperture_regs(adev);
mmhub_v1_0_init_tlb_regs(adev);
/* Setup TLB control */ /* Setup TLB control */
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL)); tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
......
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