Commit 347b4599 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (32 commits)
  [POWERPC] Remove build warnings in windfarm_core
  [POWERPC] Pass per-file CFLAGs for platform specific op codes
  [POWERPC] Correct #endif comment
  [POWERPC] Fix ppc_rtas_progress_show()
  [POWERPC] Fix sed command lines for zlib source construction
  [POWERPC] Specify GNUTARGET on $(AR) invocations
  [POWERPC] Make sure device node type/name is not NULL on hot-added nodes
  [POWERPC] Small fixes for the Ebony device tree
  [POWERPC] Fix warning on UP
  [POWERPC] cell_defconfig: Disable cpufreq and pmi
  [POWERPC] Fix IO space on PCI buses created from of_platform
  [POWERPC] Add spinlock to request_phb_iospace()
  [POWERPC] Fix make rules for treeImage.initrd
  [POWERPC] Remove warning in mpic.c
  [POWERPC] Update pasemi_defconfig
  [POWERPC] pasemi: CONFIG_GENERIC_TBSYNC no longer needed
  [POWERPC] Update iseries_defconfig
  [POWERPC] Wire up some more syscalls
  [POWERPC] Fix bug adding properties with flatdevtree.c's ft_set_prop()
  [POWERPC] Remove fixup_bigphys_addr() for arch/powerpc to avoid link error
  ...
parents 939e3428 ccd308f0
......@@ -29,7 +29,7 @@ CROSS32CC := $(CC) -m32
CROSS32AS := $(AS) -a32
CROSS32LD := $(LD) -m elf32ppc
CROSS32OBJCOPY := $(OBJCOPY)
CROSS32AR := $(AR)
CROSS32AR := GNUTARGET=elf32-powerpc $(AR)
endif
endif
......@@ -58,6 +58,7 @@ ifeq ($(HAS_BIARCH),y)
override AS += -a$(SZ)
override LD += -m elf$(SZ)ppc
override CC += -m$(SZ)
override AR := GNUTARGET=elf$(SZ)-powerpc $(AR)
endif
LDFLAGS_vmlinux := -Bstatic
......
......@@ -33,6 +33,9 @@ endif
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj)
$(obj)/44x.o: BOOTCFLAGS += -Wa,-mbooke
$(obj)/ebony.o: BOOTCFLAGS += -Wa,-mbooke
zlib := inffast.c inflate.c inftrees.c
zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
zliblinuxheader := zlib.h zconf.h zutil.h
......@@ -54,13 +57,13 @@ obj-wlib := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-wlib))))
obj-plat := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-plat))))
quiet_cmd_copy_zlib = COPY $@
cmd_copy_zlib = sed "s@__attribute_used__@@;s@<linux/\([^>]\+\).*@\"\1\"@" $< > $@
cmd_copy_zlib = sed "s@__attribute_used__@@;s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
quiet_cmd_copy_zlibheader = COPY $@
cmd_copy_zlibheader = sed "s@<linux/\([^>]\+\).*@\"\1\"@" $< > $@
cmd_copy_zlibheader = sed "s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
# stddef.h for NULL
quiet_cmd_copy_zliblinuxheader = COPY $@
cmd_copy_zliblinuxheader = sed "s@<linux/string.h>@\"string.h\"@;s@<linux/kernel.h>@<stddef.h>@;s@<linux/\([^>]\+\).*@\"\1\"@" $< > $@
cmd_copy_zliblinuxheader = sed "s@<linux/string.h>@\"string.h\"@;s@<linux/kernel.h>@<stddef.h>@;s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
$(addprefix $(obj)/,$(zlib)): $(obj)/%: $(srctree)/lib/zlib_inflate/%
$(call cmd,copy_zlib)
......@@ -204,12 +207,12 @@ dts = $(if $(shell echo $(CONFIG_DEVICE_TREE) | grep '^/'),\
$(obj)/cuImage.%: vmlinux $(dts) $(wrapperbits)
$(call if_changed,wrap,cuboot-$*,$(dts))
$(obj)/treeImage.%: vmlinux $(dts) $(wrapperbits)
$(call if_changed,wrap,treeboot-$*,$(dts))
$(obj)/treeImage.initrd.%: vmlinux $(dts) $(wrapperbits)
$(call if_changed,wrap,treeboot-$*,$(dts),,$(obj)/ramdisk.image.gz)
$(obj)/treeImage.%: vmlinux $(dts) $(wrapperbits)
$(call if_changed,wrap,treeboot-$*,$(dts))
$(obj)/zImage: $(addprefix $(obj)/, $(image-y))
@rm -f $@; ln $< $@
$(obj)/zImage.initrd: $(addprefix $(obj)/, $(initrd-y))
......
......@@ -33,8 +33,8 @@ PowerPC,440GP@0 {
timebase-frequency = <0>; // Filled in by zImage
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <0>;
d-cache-size = <0>;
i-cache-size = <8000>; /* 32 kB */
d-cache-size = <8000>; /* 32 kB */
dcr-controller;
dcr-access-method = "native";
};
......@@ -46,7 +46,6 @@ memory {
};
UIC0: interrupt-controller0 {
device_type = "ibm,uic";
compatible = "ibm,uic-440gp", "ibm,uic";
interrupt-controller;
cell-index = <0>;
......@@ -58,7 +57,6 @@ UIC0: interrupt-controller0 {
};
UIC1: interrupt-controller1 {
device_type = "ibm,uic";
compatible = "ibm,uic-440gp", "ibm,uic";
interrupt-controller;
cell-index = <1>;
......@@ -71,36 +69,36 @@ UIC1: interrupt-controller1 {
};
CPC0: cpc {
device_type = "ibm,cpc";
compatible = "ibm,cpc-440gp";
dcr-reg = <0b0 003 0e0 010>;
// FIXME: anything else?
};
plb {
device_type = "ibm,plb";
compatible = "ibm,plb-440gp", "ibm,plb4";
#address-cells = <2>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; // Filled in by zImage
SDRAM0: sdram {
device_type = "memory-controller";
compatible = "ibm,sdram-440gp", "ibm,sdram";
SDRAM0: memory-controller {
compatible = "ibm,sdram-440gp";
dcr-reg = <010 2>;
// FIXME: anything else?
};
SRAM0: sram {
compatible = "ibm,sram-440gp";
dcr-reg = <020 8 00a 1>;
};
DMA0: dma {
// FIXME: ???
device_type = "ibm,dma-4xx";
compatible = "ibm,dma-440gp", "ibm,dma-4xx";
compatible = "ibm,dma-440gp";
dcr-reg = <100 027>;
};
MAL0: mcmal {
device_type = "mcmal-dma";
compatible = "ibm,mcmal-440gp", "ibm,mcmal";
dcr-reg = <180 62>;
num-tx-chans = <4>;
......@@ -119,7 +117,6 @@ MAL0: mcmal {
};
POB0: opb {
device_type = "ibm,opb";
compatible = "ibm,opb-440gp", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
......@@ -133,8 +130,7 @@ range */
clock-frequency = <0>; // Filled in by zImage
EBC0: ebc {
device_type = "ibm,ebc";
compatible = "ibm,ebc-440gp";
compatible = "ibm,ebc-440gp", "ibm,ebc";
dcr-reg = <012 2>;
#address-cells = <2>;
#size-cells = <1>;
......@@ -147,7 +143,7 @@ EBC0: ebc {
interrupts = <5 4>;
interrupt-parent = <&UIC1>;
small-flash@0,0 {
small-flash@0,80000 {
device_type = "rom";
compatible = "direct-mapped";
probe-type = "JEDEC";
......@@ -159,7 +155,6 @@ small-flash@0,0 {
ds1743@1,0 {
/* NVRAM & RTC */
device_type = "nvram";
compatible = "ds1743";
reg = <1 0 2000>;
};
......@@ -170,7 +165,7 @@ large-flash@2,0 {
probe-type = "JEDEC";
bank-width = <1>;
partitions = <0 380000
280000 80000>;
380000 80000>;
partition-names = "fs", "firmware";
reg = <2 0 400000>;
};
......@@ -226,13 +221,11 @@ IIC1: i2c@40000500 {
GPIO0: gpio@40000700 {
/* FIXME */
device_type = "gpio";
compatible = "ibm,gpio-440gp";
reg = <40000700 20>;
};
ZMII0: emac-zmii@40000780 {
device_type = "emac-zmii";
compatible = "ibm,zmii-440gp", "ibm,zmii";
reg = <40000780 c>;
};
......@@ -299,9 +292,5 @@ PCIX0: pci@1234 {
chosen {
linux,stdout-path = "/plb/opb/serial@40000200";
// linux,initrd-start = <0>; /* FIXME */
// linux,initrd-end = <0>;
// bootargs = "";
};
};
......@@ -21,19 +21,16 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
*/
/ {
linux,phandle = <1000>;
model = "KuroboxHD";
compatible = "linkstation";
#address-cells = <1>;
#size-cells = <1>;
cpus {
linux,phandle = <2000>;
#address-cells = <1>;
#size-cells = <0>;
PowerPC,603e { /* Really 8241 */
linux,phandle = <2100>;
device_type = "cpu";
reg = <0>;
clock-frequency = <bebc200>; /* Fixed by bootwrapper */
......@@ -48,13 +45,11 @@ PowerPC,603e { /* Really 8241 */
};
memory {
linux,phandle = <3000>;
device_type = "memory";
reg = <00000000 04000000>;
};
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
linux,phandle = <4000>;
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
......@@ -69,38 +64,34 @@ fec00000 fec00000 00300000 /* pci cfg regs */
fef00000 fef00000 00100000>; /* pci iack */
i2c@80003000 {
linux,phandle = <4300>;
device_type = "i2c";
compatible = "fsl-i2c";
reg = <80003000 1000>;
interrupts = <5 2>;
interrupt-parent = <4400>;
interrupt-parent = <&mpic>;
};
serial@80004500 {
linux,phandle = <4511>;
device_type = "serial";
compatible = "ns16550";
reg = <80004500 8>;
clock-frequency = <5d08d88>;
current-speed = <2580>;
interrupts = <9 2>;
interrupt-parent = <4400>;
interrupt-parent = <&mpic>;
};
serial@80004600 {
linux,phandle = <4512>;
device_type = "serial";
compatible = "ns16550";
reg = <80004600 8>;
clock-frequency = <5d08d88>;
current-speed = <e100>;
interrupts = <a 0>;
interrupt-parent = <4400>;
interrupt-parent = <&mpic>;
};
pic@80040000 {
linux,phandle = <4400>;
mpic: pic@80040000 {
#interrupt-cells = <2>;
#address-cells = <0>;
device_type = "open-pic";
......@@ -111,7 +102,6 @@ pic@80040000 {
};
pci@fec00000 {
linux,phandle = <4500>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
......@@ -122,24 +112,24 @@ pci@fec00000 {
02000000 0 80000000 80000000 0 70000000>;
bus-range = <0 ff>;
clock-frequency = <7f28155>;
interrupt-parent = <4400>;
interrupt-parent = <&mpic>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 11 - IRQ0 ETH */
5800 0 0 1 4400 0 1
5800 0 0 2 4400 1 1
5800 0 0 3 4400 2 1
5800 0 0 4 4400 3 1
5800 0 0 1 &mpic 0 1
5800 0 0 2 &mpic 1 1
5800 0 0 3 &mpic 2 1
5800 0 0 4 &mpic 3 1
/* IDSEL 12 - IRQ1 IDE0 */
6000 0 0 1 4400 1 1
6000 0 0 2 4400 2 1
6000 0 0 3 4400 3 1
6000 0 0 4 4400 0 1
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 0 1
/* IDSEL 14 - IRQ3 USB2.0 */
7000 0 0 1 4400 3 1
7000 0 0 2 4400 3 1
7000 0 0 3 4400 3 1
7000 0 0 4 4400 3 1
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 3 1
7000 0 0 3 &mpic 3 1
7000 0 0 4 &mpic 3 1
>;
};
};
......
......@@ -21,19 +21,16 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
*/
/ {
linux,phandle = <1000>;
model = "KuroboxHG";
compatible = "linkstation";
#address-cells = <1>;
#size-cells = <1>;
cpus {
linux,phandle = <2000>;
#address-cells = <1>;
#size-cells = <0>;
PowerPC,603e { /* Really 8241 */
linux,phandle = <2100>;
device_type = "cpu";
reg = <0>;
clock-frequency = <fdad680>; /* Fixed by bootwrapper */
......@@ -48,13 +45,11 @@ PowerPC,603e { /* Really 8241 */
};
memory {
linux,phandle = <3000>;
device_type = "memory";
reg = <00000000 08000000>;
};
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
linux,phandle = <4000>;
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
......@@ -69,38 +64,35 @@ fec00000 fec00000 00300000 /* pci cfg regs */
fef00000 fef00000 00100000>; /* pci iack */
i2c@80003000 {
linux,phandle = <4300>;
device_type = "i2c";
compatible = "fsl-i2c";
reg = <80003000 1000>;
interrupts = <5 2>;
interrupt-parent = <4400>;
interrupt-parent = <&mpic>;
};
serial@80004500 {
linux,phandle = <4511>;
device_type = "serial";
compatible = "ns16550";
reg = <80004500 8>;
clock-frequency = <7c044a8>;
current-speed = <2580>;
interrupts = <9 2>;
interrupt-parent = <4400>;
interrupt-parent = <&mpic>;
};
serial@80004600 {
linux,phandle = <4512>;
device_type = "serial";
compatible = "ns16550";
reg = <80004600 8>;
clock-frequency = <7c044a8>;
current-speed = <e100>;
interrupts = <a 0>;
interrupt-parent = <4400>;
interrupt-parent = <&mpic>;
};
pic@80040000 {
linux,phandle = <4400>;
mpic: pic@80040000 {
interrupt-parent = <&mpic>;
#interrupt-cells = <2>;
#address-cells = <0>;
device_type = "open-pic";
......@@ -111,7 +103,6 @@ pic@80040000 {
};
pci@fec00000 {
linux,phandle = <4500>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
......@@ -122,24 +113,24 @@ pci@fec00000 {
02000000 0 80000000 80000000 0 70000000>;
bus-range = <0 ff>;
clock-frequency = <7f28155>;
interrupt-parent = <4400>;
interrupt-parent = <&mpic>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 11 - IRQ0 ETH */
5800 0 0 1 4400 0 1
5800 0 0 2 4400 1 1
5800 0 0 3 4400 2 1
5800 0 0 4 4400 3 1
5800 0 0 1 &mpic 0 1
5800 0 0 2 &mpic 1 1
5800 0 0 3 &mpic 2 1
5800 0 0 4 &mpic 3 1
/* IDSEL 12 - IRQ1 IDE0 */
6000 0 0 1 4400 1 1
6000 0 0 2 4400 2 1
6000 0 0 3 4400 3 1
6000 0 0 4 4400 0 1
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 0 1
/* IDSEL 14 - IRQ3 USB2.0 */
7000 0 0 1 4400 3 1
7000 0 0 2 4400 3 1
7000 0 0 3 4400 3 1
7000 0 0 4 4400 3 1
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 3 1
7000 0 0 3 &mpic 3 1
7000 0 0 4 &mpic 3 1
>;
};
};
......
......@@ -49,7 +49,7 @@ memory {
soc5200@f0000000 {
model = "fsl,mpc5200";
compatible = "mpc5200";
revision = "" // from bootloader
revision = ""; // from bootloader
#interrupt-cells = <3>;
device_type = "soc";
ranges = <0 f0000000 f0010000>;
......@@ -62,13 +62,12 @@ cdm@200 {
reg = <200 38>;
};
pic@500 {
mpc5200_pic: pic@500 {
// 5200 interrupts are encoded into two levels;
linux,phandle = <500>;
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
compatible = "mpc5200_pic";
reg = <500 80>;
built-in;
};
......@@ -79,7 +78,7 @@ gpt@600 { // General Purpose Timer
cell-index = <0>;
reg = <600 10>;
interrupts = <1 9 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
has-wdt;
};
......@@ -89,7 +88,7 @@ gpt@610 { // General Purpose Timer
cell-index = <1>;
reg = <610 10>;
interrupts = <1 a 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@620 { // General Purpose Timer
......@@ -98,7 +97,7 @@ gpt@620 { // General Purpose Timer
cell-index = <2>;
reg = <620 10>;
interrupts = <1 b 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@630 { // General Purpose Timer
......@@ -107,7 +106,7 @@ gpt@630 { // General Purpose Timer
cell-index = <3>;
reg = <630 10>;
interrupts = <1 c 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@640 { // General Purpose Timer
......@@ -116,7 +115,7 @@ gpt@640 { // General Purpose Timer
cell-index = <4>;
reg = <640 10>;
interrupts = <1 d 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@650 { // General Purpose Timer
......@@ -125,7 +124,7 @@ gpt@650 { // General Purpose Timer
cell-index = <5>;
reg = <650 10>;
interrupts = <1 e 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@660 { // General Purpose Timer
......@@ -134,7 +133,7 @@ gpt@660 { // General Purpose Timer
cell-index = <6>;
reg = <660 10>;
interrupts = <1 f 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@670 { // General Purpose Timer
......@@ -143,7 +142,7 @@ gpt@670 { // General Purpose Timer
cell-index = <7>;
reg = <670 10>;
interrupts = <1 10 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
......@@ -151,7 +150,7 @@ rtc@800 { // Real time clock
device_type = "rtc";
reg = <800 100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
mscan@900 {
......@@ -159,7 +158,7 @@ mscan@900 {
compatible = "mpc5200-mscan";
cell-index = <0>;
interrupts = <2 11 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
reg = <900 80>;
};
......@@ -168,7 +167,7 @@ mscan@980 {
compatible = "mpc5200-mscan";
cell-index = <1>;
interrupts = <2 12 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
reg = <980 80>;
};
......@@ -176,14 +175,14 @@ gpio@b00 {
compatible = "mpc5200-gpio";
reg = <b00 40>;
interrupts = <1 7 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpio-wkup@c00 {
compatible = "mpc5200-gpio-wkup";
reg = <c00 40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
pci@0d00 {
......@@ -194,13 +193,13 @@ pci@0d00 {
compatible = "mpc5200-pci";
reg = <d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 500 0 0 3
c000 0 0 2 500 0 0 3
c000 0 0 3 500 0 0 3
c000 0 0 4 500 0 0 3>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
c000 0 0 2 &mpc5200_pic 0 0 3
c000 0 0 3 &mpc5200_pic 0 0 3
c000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
......@@ -212,7 +211,7 @@ spi@f00 {
compatible = "mpc5200-spi";
reg = <f00 20>;
interrupts = <2 d 0 2 e 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
......@@ -220,7 +219,7 @@ usb@1000 {
compatible = "mpc5200-ohci\0ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
bestcomm@1200 {
......@@ -231,7 +230,7 @@ bestcomm@1200 {
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 a 0 3 b 0
3 c 0 3 d 0 3 e 0 3 f 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
......@@ -246,7 +245,7 @@ serial@2000 { // PSC1
cell-index = <0>;
reg = <2000 100>;
interrupts = <2 1 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
// PSC2 in ac97 mode example
......@@ -256,7 +255,7 @@ serial@2000 { // PSC1
// cell-index = <1>;
// reg = <2200 100>;
// interrupts = <2 2 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC3 in CODEC mode example
......@@ -266,7 +265,7 @@ serial@2000 { // PSC1
// cell-index = <2>;
// reg = <2400 100>;
// interrupts = <2 3 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC4 in uart mode example
......@@ -276,7 +275,7 @@ serial@2000 { // PSC1
// cell-index = <3>;
// reg = <2600 100>;
// interrupts = <2 b 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC5 in uart mode example
......@@ -286,7 +285,7 @@ serial@2000 { // PSC1
// cell-index = <4>;
// reg = <2800 100>;
// interrupts = <2 c 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC6 in spi mode example
......@@ -296,7 +295,7 @@ serial@2000 { // PSC1
// cell-index = <5>;
// reg = <2c00 100>;
// interrupts = <2 4 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
ethernet@3000 {
......@@ -305,7 +304,7 @@ ethernet@3000 {
reg = <3000 800>;
mac-address = [ 02 03 04 05 06 07 ]; // Bad!
interrupts = <2 5 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
ata@3a00 {
......@@ -313,7 +312,7 @@ ata@3a00 {
compatible = "mpc5200-ata";
reg = <3a00 100>;
interrupts = <2 7 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
i2c@3d00 {
......@@ -322,7 +321,7 @@ i2c@3d00 {
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
......@@ -332,7 +331,7 @@ i2c@3d40 {
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
sram@8000 {
......
......@@ -62,13 +62,12 @@ cdm@200 {
reg = <200 38>;
};
pic@500 {
mpc5200_pic: pic@500 {
// 5200 interrupts are encoded into two levels;
linux,phandle = <500>;
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "mpc5200b-pic\0mpc5200-pic";
compatible = "mpc5200b-pic\0mpc5200_pic";
reg = <500 80>;
built-in;
};
......@@ -79,7 +78,7 @@ gpt@600 { // General Purpose Timer
cell-index = <0>;
reg = <600 10>;
interrupts = <1 9 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
has-wdt;
};
......@@ -89,7 +88,7 @@ gpt@610 { // General Purpose Timer
cell-index = <1>;
reg = <610 10>;
interrupts = <1 a 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@620 { // General Purpose Timer
......@@ -98,7 +97,7 @@ gpt@620 { // General Purpose Timer
cell-index = <2>;
reg = <620 10>;
interrupts = <1 b 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@630 { // General Purpose Timer
......@@ -107,7 +106,7 @@ gpt@630 { // General Purpose Timer
cell-index = <3>;
reg = <630 10>;
interrupts = <1 c 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@640 { // General Purpose Timer
......@@ -116,7 +115,7 @@ gpt@640 { // General Purpose Timer
cell-index = <4>;
reg = <640 10>;
interrupts = <1 d 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@650 { // General Purpose Timer
......@@ -125,7 +124,7 @@ gpt@650 { // General Purpose Timer
cell-index = <5>;
reg = <650 10>;
interrupts = <1 e 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@660 { // General Purpose Timer
......@@ -134,7 +133,7 @@ gpt@660 { // General Purpose Timer
cell-index = <6>;
reg = <660 10>;
interrupts = <1 f 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpt@670 { // General Purpose Timer
......@@ -143,7 +142,7 @@ gpt@670 { // General Purpose Timer
cell-index = <7>;
reg = <670 10>;
interrupts = <1 10 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
......@@ -151,7 +150,7 @@ rtc@800 { // Real time clock
device_type = "rtc";
reg = <800 100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
mscan@900 {
......@@ -159,7 +158,7 @@ mscan@900 {
compatible = "mpc5200b-mscan\0mpc5200-mscan";
cell-index = <0>;
interrupts = <2 11 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
reg = <900 80>;
};
......@@ -168,7 +167,7 @@ mscan@980 {
compatible = "mpc5200b-mscan\0mpc5200-mscan";
cell-index = <1>;
interrupts = <2 12 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
reg = <980 80>;
};
......@@ -176,14 +175,14 @@ gpio@b00 {
compatible = "mpc5200b-gpio\0mpc5200-gpio";
reg = <b00 40>;
interrupts = <1 7 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
gpio-wkup@c00 {
compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
reg = <c00 40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
pci@0d00 {
......@@ -194,18 +193,18 @@ pci@0d00 {
compatible = "mpc5200b-pci\0mpc5200-pci";
reg = <d00 100>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot
c000 0 0 2 500 1 1 3
c000 0 0 3 500 1 2 3
c000 0 0 4 500 1 3 3
c800 0 0 1 500 1 1 3 // 2nd slot
c800 0 0 2 500 1 2 3
c800 0 0 3 500 1 3 3
c800 0 0 4 500 0 0 3>;
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
c000 0 0 2 &mpc5200_pic 1 1 3
c000 0 0 3 &mpc5200_pic 1 2 3
c000 0 0 4 &mpc5200_pic 1 3 3
c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
c800 0 0 2 &mpc5200_pic 1 2 3
c800 0 0 3 &mpc5200_pic 1 3 3
c800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 a 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 10000000
......@@ -217,7 +216,7 @@ spi@f00 {
compatible = "mpc5200b-spi\0mpc5200-spi";
reg = <f00 20>;
interrupts = <2 d 0 2 e 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
......@@ -225,7 +224,7 @@ usb@1000 {
compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
bestcomm@1200 {
......@@ -236,7 +235,7 @@ bestcomm@1200 {
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 a 0 3 b 0
3 c 0 3 d 0 3 e 0 3 f 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
......@@ -251,7 +250,7 @@ serial@2000 { // PSC1
cell-index = <0>;
reg = <2000 100>;
interrupts = <2 1 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
// PSC2 in ac97 mode example
......@@ -261,7 +260,7 @@ serial@2000 { // PSC1
// cell-index = <1>;
// reg = <2200 100>;
// interrupts = <2 2 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC3 in CODEC mode example
......@@ -271,7 +270,7 @@ serial@2000 { // PSC1
// cell-index = <2>;
// reg = <2400 100>;
// interrupts = <2 3 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC4 in uart mode example
......@@ -281,7 +280,7 @@ serial@2000 { // PSC1
// cell-index = <3>;
// reg = <2600 100>;
// interrupts = <2 b 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC5 in uart mode example
......@@ -291,7 +290,7 @@ serial@2000 { // PSC1
// cell-index = <4>;
// reg = <2800 100>;
// interrupts = <2 c 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
// PSC6 in spi mode example
......@@ -301,7 +300,7 @@ serial@2000 { // PSC1
// cell-index = <5>;
// reg = <2c00 100>;
// interrupts = <2 4 0>;
// interrupt-parent = <500>;
// interrupt-parent = <&mpc5200_pic>;
//};
ethernet@3000 {
......@@ -310,7 +309,7 @@ ethernet@3000 {
reg = <3000 800>;
mac-address = [ 02 03 04 05 06 07 ]; // Bad!
interrupts = <2 5 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
ata@3a00 {
......@@ -318,7 +317,7 @@ ata@3a00 {
compatible = "mpc5200b-ata\0mpc5200-ata";
reg = <3a00 100>;
interrupts = <2 7 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
};
i2c@3d00 {
......@@ -327,7 +326,7 @@ i2c@3d00 {
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
......@@ -337,7 +336,7 @@ i2c@3d40 {
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
interrupt-parent = <500>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
sram@8000 {
......
......@@ -16,12 +16,10 @@ / {
compatible = "mpc74xx";
#address-cells = <1>;
#size-cells = <1>;
linux,phandle = <100>;
cpus {
#address-cells = <1>;
#size-cells =<0>;
linux,phandle = <200>;
PowerPC,7448@0 {
device_type = "cpu";
......@@ -34,13 +32,11 @@ PowerPC,7448@0 {
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
32-bit;
linux,phandle = <201>;
};
};
memory {
device_type = "memory";
linux,phandle = <300>;
reg = <00000000 20000000 // DDR2 512M at 0
>;
};
......@@ -55,7 +51,7 @@ tsi108@c0000000 {
bus-frequency = <0>;
i2c@7000 {
interrupt-parent = <7400>;
interrupt-parent = <&mpic>;
interrupts = <E 0>;
reg = <7000 400>;
device_type = "i2c";
......@@ -66,18 +62,16 @@ mdio@6000 {
device_type = "mdio";
compatible = "tsi-ethernet";
ethernet-phy@6000 {
linux,phandle = <6000>;
interrupt-parent = <7400>;
phy8: ethernet-phy@6000 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <6000 50>;
phy-id = <8>;
device_type = "ethernet-phy";
};
ethernet-phy@6400 {
linux,phandle = <6400>;
interrupt-parent = <7400>;
phy9: ethernet-phy@6400 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <6000 50>;
phy-id = <9>;
......@@ -94,8 +88,8 @@ ethernet@6200 {
reg = <6000 200>;
address = [ 00 06 D2 00 00 01 ];
interrupts = <10 2>;
interrupt-parent = <7400>;
phy-handle = <6000>;
interrupt-parent = <&mpic>;
phy-handle = <&phy8>;
};
ethernet@6600 {
......@@ -107,8 +101,8 @@ ethernet@6600 {
reg = <6400 200>;
address = [ 00 06 D2 00 00 02 ];
interrupts = <11 2>;
interrupt-parent = <7400>;
phy-handle = <6400>;
interrupt-parent = <&mpic>;
phy-handle = <&phy9>;
};
serial@7808 {
......@@ -117,7 +111,7 @@ serial@7808 {
reg = <7808 200>;
clock-frequency = <3f6b5a00>;
interrupts = <c 0>;
interrupt-parent = <7400>;
interrupt-parent = <&mpic>;
};
serial@7c08 {
......@@ -126,11 +120,10 @@ serial@7c08 {
reg = <7c08 200>;
clock-frequency = <3f6b5a00>;
interrupts = <d 0>;
interrupt-parent = <7400>;
interrupt-parent = <&mpic>;
};
pic@7400 {
linux,phandle = <7400>;
mpic: pic@7400 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
......@@ -144,7 +137,6 @@ pic@7400 {
pci@1000 {
compatible = "tsi10x";
device_type = "pci";
linux,phandle = <1000>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
......@@ -153,37 +145,37 @@ pci@1000 {
ranges = <02000000 0 e0000000 e0000000 0 1A000000
01000000 0 00000000 fa000000 0 00010000>;
clock-frequency = <7f28154>;
interrupt-parent = <7400>;
interrupt-parent = <&mpic>;
interrupts = <17 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
0800 0 0 1 1180 24 0
0800 0 0 2 1180 25 0
0800 0 0 3 1180 26 0
0800 0 0 4 1180 27 0
0800 0 0 1 &RT0 24 0
0800 0 0 2 &RT0 25 0
0800 0 0 3 &RT0 26 0
0800 0 0 4 &RT0 27 0
/* IDSEL 0x12 */
1000 0 0 1 1180 25 0
1000 0 0 2 1180 26 0
1000 0 0 3 1180 27 0
1000 0 0 4 1180 24 0
1000 0 0 1 &RT0 25 0
1000 0 0 2 &RT0 26 0
1000 0 0 3 &RT0 27 0
1000 0 0 4 &RT0 24 0
/* IDSEL 0x13 */
1800 0 0 1 1180 26 0
1800 0 0 2 1180 27 0
1800 0 0 3 1180 24 0
1800 0 0 4 1180 25 0
1800 0 0 1 &RT0 26 0
1800 0 0 2 &RT0 27 0
1800 0 0 3 &RT0 24 0
1800 0 0 4 &RT0 25 0
/* IDSEL 0x14 */
2000 0 0 1 1180 27 0
2000 0 0 2 1180 24 0
2000 0 0 3 1180 25 0
2000 0 0 4 1180 26 0
2000 0 0 1 &RT0 27 0
2000 0 0 2 &RT0 24 0
2000 0 0 3 &RT0 25 0
2000 0 0 4 &RT0 26 0
>;
router@1180 {
linux,phandle = <1180>;
RT0: router@1180 {
clock-frequency = <0>;
interrupt-controller;
device_type = "pic-router";
......@@ -192,7 +184,7 @@ router@1180 {
built-in;
big-endian;
interrupts = <17 2>;
interrupt-parent = <7400>;
interrupt-parent = <&mpic>;
};
};
};
......
......@@ -48,6 +48,22 @@ soc8540@e0000000 {
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
......
......@@ -48,6 +48,22 @@ soc8541@e0000000 {
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8541-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
......
......@@ -48,6 +48,22 @@ soc8544@e0000000 {
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 {
compatible = "fsl,8544-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
......
......@@ -48,6 +48,22 @@ soc8548@e0000000 {
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
......
......@@ -48,6 +48,22 @@ soc8555@e0000000 {
reg = <e0000000 00100000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8555-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8555-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
......
......@@ -48,6 +48,22 @@ soc8560@e0000000 {
reg = <e0000000 00000200>;
bus-frequency = <13ab6680>;
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
mdio@24520 {
device_type = "mdio";
compatible = "gianfar";
......@@ -110,7 +126,7 @@ pci@8000 {
#address-cells = <3>;
compatible = "85xx";
device_type = "pci";
reg = <8000 400>;
reg = <8000 1000>;
clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
......
......@@ -57,6 +57,22 @@ soc8568@e0000000 {
reg = <e0000000 00100000>;
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8568-memory-controller";
reg = <2000 1000>;
interrupt-parent = <&mpic>;
interrupts = <2 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8568-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <0 2>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
......
......@@ -891,28 +891,27 @@ int ft_set_prop(struct ft_cxt *cxt, const void *phandle, const char *propname,
struct ft_atom atom;
void *node;
char *p, *next;
int nextra, depth;
int nextra;
node = ft_node_ph2node(cxt, phandle);
if (node == NULL)
return -1;
depth = 0;
p = node;
next = ft_next(cxt, node, &atom);
if (atom.tag != OF_DT_BEGIN_NODE)
/* phandle didn't point to a node */
return -1;
p = next;
while ((next = ft_next(cxt, p, &atom)) != NULL) {
switch (atom.tag) {
case OF_DT_BEGIN_NODE:
++depth;
break;
case OF_DT_BEGIN_NODE: /* properties must go before subnodes */
case OF_DT_END_NODE:
if (--depth > 0)
break;
/* haven't found the property, insert here */
cxt->p = p;
return ft_prop(cxt, propname, buf, buflen);
case OF_DT_PROP:
if ((depth != 1) || strcmp(atom.name, propname))
if (strcmp(atom.name, propname))
break;
/* found an existing property, overwrite it */
nextra = _ALIGN(buflen, 4) - _ALIGN(atom.size, 4);
......
......@@ -163,7 +163,6 @@ CONFIG_SPU_FS=m
CONFIG_SPU_BASE=y
CONFIG_CBE_RAS=y
CONFIG_CBE_THERM=m
CONFIG_CBE_CPUFREQ=m
CONFIG_PPC_NATIVE=y
CONFIG_UDBG_RTAS_CONSOLE=y
CONFIG_PPC_UDBG_BEAT=y
......@@ -172,24 +171,12 @@ CONFIG_PPC_RTAS=y
# CONFIG_RTAS_ERROR_LOGGING is not set
CONFIG_RTAS_PROC=y
CONFIG_RTAS_FLASH=y
CONFIG_PPC_PMI=m
# CONFIG_PPC_PMI is not set
CONFIG_MMIO_NVRAM=y
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set
CONFIG_PPC_INDIRECT_IO=y
CONFIG_GENERIC_IOMAP=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_TABLE=y
CONFIG_CPU_FREQ_DEBUG=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_STAT_DETAILS is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
# CONFIG_CPU_FREQ_PMAC64 is not set
# CONFIG_WANT_EARLY_SERIAL is not set
CONFIG_MPIC=y
......
This diff is collapsed.
This diff is collapsed.
......@@ -836,7 +836,7 @@ static struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80040000,
.cpu_name = "7448",
.cpu_features = CPU_FTRS_7447A,
.cpu_features = CPU_FTRS_7448,
.cpu_user_features = COMMON_USER |
PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
.icache_bsize = 32,
......
......@@ -596,7 +596,11 @@ fast_exception_return:
mr r12,r4 /* restart at exc_exit_restart */
b 2b
.comm fee_restarts,4
.section .bss
.align 2
fee_restarts:
.space 4
.previous
/* aargh, a nonrecoverable interrupt, panic */
/* aargh, we don't know which trap this is */
......@@ -851,7 +855,11 @@ load_dbcr0:
mtspr SPRN_DBSR,r11 /* clear all pending debug events */
blr
.comm global_dbcr0,8
.section .bss
.align 4
global_dbcr0:
.space 8
.previous
#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
do_work: /* r10 contains MSR_KERNEL here */
......@@ -926,7 +934,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
/* shouldn't return */
b 4b
.comm ee_restarts,4
.section .bss
.align 2
ee_restarts:
.space 4
.previous
/*
* PROM code for specific machines follows. Put it
......
......@@ -427,11 +427,13 @@ static int __devinit of_pci_phb_probe(struct of_device *dev,
/* Process "ranges" property */
pci_process_bridge_OF_ranges(phb, dev->node, 0);
/* Setup IO space.
* This will not work properly for ISA IOs, something needs to be done
* about it if we ever generalize that way of probing PCI brigdes
/* Setup IO space. We use the non-dynamic version of that code here,
* which doesn't quite support unplugging. Next kernel release will
* have a better fix for this.
* Note also that we don't do ISA, this will also be fixed with a
* more massive rework.
*/
pci_setup_phb_io_dynamic(phb, 0);
pci_setup_phb_io(phb, 0);
/* Init pci_dn data structures */
pci_devs_phb_init_dynamic(phb);
......
......@@ -41,6 +41,7 @@
unsigned long pci_probe_only = 1;
int pci_assign_all_buses = 0;
static int pci_initial_scan_done;
static void fixup_resource(struct resource *res, struct pci_dev *dev);
static void do_bus_setup(struct pci_bus *bus);
......@@ -604,6 +605,8 @@ static int __init pcibios_init(void)
/* map in PCI I/O space */
phbs_remap_io();
pci_initial_scan_done = 1;
printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
return 0;
......@@ -1042,13 +1045,16 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
}
}
void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
void __devinit pci_setup_phb_io(struct pci_controller *hose, int primary)
{
unsigned long size = hose->pci_io_size;
unsigned long io_virt_offset;
struct resource *res;
struct device_node *isa_dn;
if (size == 0)
return;
hose->io_base_virt = reserve_phb_iospace(size);
DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
hose->global_number, hose->io_base_phys,
......@@ -1069,6 +1075,15 @@ void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
res = &hose->io_resource;
res->start += io_virt_offset;
res->end += io_virt_offset;
/* If this is called after the initial PCI scan, then we need to
* proceed to IO mappings now
*/
if (pci_initial_scan_done)
__ioremap_explicit(hose->io_base_phys,
(unsigned long)hose->io_base_virt,
hose->pci_io_size,
_PAGE_NO_CACHE | _PAGE_GUARDED);
}
void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
......@@ -1078,6 +1093,9 @@ void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
unsigned long io_virt_offset;
struct resource *res;
if (size == 0)
return;
hose->io_base_virt = __ioremap(hose->io_base_phys, size,
_PAGE_NO_CACHE | _PAGE_GUARDED);
DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
......@@ -1106,6 +1124,9 @@ static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
/* Root Bus */
res = &hose->io_resource;
if (res->end == 0 && res->start == 0)
return 1;
*start_virt = pci_io_base + res->start;
*start_phys = *start_virt + hose->io_base_phys
- (unsigned long) hose->io_base_virt;
......
......@@ -1472,6 +1472,11 @@ static int of_finish_dynamic_node(struct device_node *node)
node->name = of_get_property(node, "name", NULL);
node->type = of_get_property(node, "device_type", NULL);
if (!node->name)
node->name = "<NULL>";
if (!node->type)
node->type = "<NULL>";
if (!parent) {
err = -ENODEV;
goto out;
......
......@@ -379,7 +379,7 @@ static ssize_t ppc_rtas_progress_write(struct file *file,
/* ****************************************************************** */
static int ppc_rtas_progress_show(struct seq_file *m, void *v)
{
if (progress_led)
if (progress_led[0])
seq_printf(m, "%s\n", progress_led);
return 0;
}
......
......@@ -468,25 +468,19 @@ unsigned long rh_alloc_align(rh_info_t * info, int size, int alignment, const ch
if (blk->size == size) {
/* Move from free list to taken list */
list_del(&blk->list);
blk->owner = owner;
start = blk->start;
attach_taken_block(info, blk);
newblk = blk;
} else {
newblk = get_slot(info);
newblk->start = blk->start;
newblk->size = size;
return start;
/* blk still in free list, with updated start, size */
blk->start += size;
blk->size -= size;
}
newblk = get_slot(info);
newblk->start = blk->start;
newblk->size = size;
newblk->owner = owner;
/* blk still in free list, with updated start, size */
blk->start += size;
blk->size -= size;
start = newblk->start;
attach_taken_block(info, newblk);
/* for larger alignment return fixed up pointer */
......
......@@ -30,7 +30,11 @@
#include <asm/asm-offsets.h>
#ifdef CONFIG_SMP
.comm mmu_hash_lock,4
.section .bss
.align 2
.globl mmu_hash_lock
mmu_hash_lock:
.space 4
#endif /* CONFIG_SMP */
/*
......@@ -455,9 +459,15 @@ found_slot:
sync /* make sure pte updates get to memory */
blr
.comm next_slot,4
.comm primary_pteg_full,4
.comm htab_hash_searches,4
.section .bss
.align 2
next_slot:
.space 4
primary_pteg_full:
.space 4
htab_hash_searches:
.space 4
.previous
/*
* Flush the entry for a particular page from the hash table.
......
......@@ -430,7 +430,7 @@ static void __init htab_finish_init(void)
make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
#endif /* CONFIG_PPC_64K_PAGES */
#endif /* CONFIG_PPC_HAS_HASH_64K */
make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
......@@ -837,7 +837,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
if (mm->context.user_psize == MMU_PAGE_64K)
__hash_page_64K(ea, access, vsid, ptep, trap, local);
else
#endif /* CONFIG_PPC_64K_PAGES */
#endif /* CONFIG_PPC_HAS_HASH_64K */
__hash_page_4K(ea, access, vsid, ptep, trap, local);
local_irq_restore(flags);
......
......@@ -322,6 +322,8 @@ EXPORT_SYMBOL(__ioremap);
EXPORT_SYMBOL(iounmap);
EXPORT_SYMBOL(__iounmap);
static DEFINE_SPINLOCK(phb_io_lock);
void __iomem * reserve_phb_iospace(unsigned long size)
{
void __iomem *virt_addr;
......@@ -329,8 +331,10 @@ void __iomem * reserve_phb_iospace(unsigned long size)
if (phbs_io_bot >= IMALLOC_BASE)
panic("reserve_phb_iospace(): phb io space overflow\n");
spin_lock(&phb_io_lock);
virt_addr = (void __iomem *) phbs_io_bot;
phbs_io_bot += size;
spin_unlock(&phb_io_lock);
return virt_addr;
}
......@@ -38,7 +38,8 @@ config 440EP
config 440GP
bool
select IBM_NEW_EMAC_ZMII
# Disabled until the new EMAC Driver is merged.
# select IBM_NEW_EMAC_ZMII
config 440GX
bool
......
......@@ -27,9 +27,9 @@
#include "44x.h"
static struct of_device_id ebony_of_bus[] = {
{ .type = "ibm,plb", },
{ .type = "ibm,opb", },
{ .type = "ibm,ebc", },
{ .compatible = "ibm,plb4", },
{ .compatible = "ibm,opb", },
{ .compatible = "ibm,ebc", },
{},
};
......
......@@ -37,6 +37,7 @@
#include <linux/wait.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/completion.h>
#include <asm/system.h>
#include <asm/uaccess.h>
......@@ -81,7 +82,7 @@ static void handleMonitorEvent(struct HvLpEvent *event);
* if system_state is not SYSTEM_RUNNING, then wait_atomic is used ...
*/
struct alloc_parms {
struct semaphore sem;
struct completion done;
int number;
atomic_t wait_atomic;
int used_wait_atomic;
......@@ -115,7 +116,7 @@ static int proc_viopath_show(struct seq_file *m, void *v)
u16 vlanMap;
dma_addr_t handle;
HvLpEvent_Rc hvrc;
DECLARE_MUTEX_LOCKED(Semaphore);
DECLARE_COMPLETION(done);
struct device_node *node;
const char *sysid;
......@@ -132,13 +133,13 @@ static int proc_viopath_show(struct seq_file *m, void *v)
HvLpEvent_AckInd_DoAck, HvLpEvent_AckType_ImmediateAck,
viopath_sourceinst(viopath_hostLp),
viopath_targetinst(viopath_hostLp),
(u64)(unsigned long)&Semaphore, VIOVERSION << 16,
(u64)(unsigned long)&done, VIOVERSION << 16,
((u64)handle) << 32, HW_PAGE_SIZE, 0, 0);
if (hvrc != HvLpEvent_Rc_Good)
printk(VIOPATH_KERN_WARN "hv error on op %d\n", (int)hvrc);
down(&Semaphore);
wait_for_completion(&done);
vlanMap = HvLpConfig_getVirtualLanIndexMap();
......@@ -353,7 +354,7 @@ static void handleConfig(struct HvLpEvent *event)
return;
}
up((struct semaphore *)event->xCorrelationToken);
complete((struct completion *)event->xCorrelationToken);
}
/*
......@@ -464,7 +465,7 @@ static void viopath_donealloc(void *parm, int number)
if (parmsp->used_wait_atomic)
atomic_set(&parmsp->wait_atomic, 0);
else
up(&parmsp->sem);
complete(&parmsp->done);
}
static int allocateEvents(HvLpIndex remoteLp, int numEvents)
......@@ -476,7 +477,7 @@ static int allocateEvents(HvLpIndex remoteLp, int numEvents)
atomic_set(&parms.wait_atomic, 1);
} else {
parms.used_wait_atomic = 0;
init_MUTEX_LOCKED(&parms.sem);
init_completion(&parms.done);
}
mf_allocate_lp_events(remoteLp, HvLpEvent_Type_VirtualIo, 250, /* It would be nice to put a real number here! */
numEvents, &viopath_donealloc, &parms);
......@@ -484,7 +485,7 @@ static int allocateEvents(HvLpIndex remoteLp, int numEvents)
while (atomic_read(&parms.wait_atomic))
mb();
} else
down(&parms.sem);
wait_for_completion(&parms.done);
return parms.number;
}
......@@ -585,10 +586,10 @@ int viopath_close(HvLpIndex remoteLp, int subtype, int numReq)
spin_unlock_irqrestore(&statuslock, flags);
parms.used_wait_atomic = 0;
init_MUTEX_LOCKED(&parms.sem);
init_completion(&parms.done);
mf_deallocate_lp_events(remoteLp, HvLpEvent_Type_VirtualIo,
numReq, &viopath_donealloc, &parms);
down(&parms.sem);
wait_for_completion(&parms.done);
spin_lock_irqsave(&statuslock, flags);
for (i = 0, numOpen = 0; i < VIO_MAX_SUBTYPES; i++)
......
......@@ -4,7 +4,6 @@ config PPC_PASEMI
default n
select MPIC
select PPC_UDBG_16550
select GENERIC_TBSYNC
select PPC_NATIVE
help
This option enables support for PA Semi's PWRficient line
......
......@@ -21,8 +21,8 @@ extern int pSeries_machine_check_exception(struct pt_regs *regs);
extern void smp_init_pseries_mpic(void);
extern void smp_init_pseries_xics(void);
#else
static inline smp_init_pseries_mpic(void) { };
static inline smp_init_pseries_xics(void) { };
static inline void smp_init_pseries_mpic(void) { };
static inline void smp_init_pseries_xics(void) { };
#endif
#ifdef CONFIG_KEXEC
......
......@@ -1424,7 +1424,7 @@ unsigned int mpic_get_irq(void)
void mpic_request_ipis(void)
{
struct mpic *mpic = mpic_primary;
int i;
int i, err;
static char *ipi_names[] = {
"IPI0 (call function)",
"IPI1 (reschedule)",
......@@ -1442,8 +1442,14 @@ void mpic_request_ipis(void)
printk(KERN_ERR "Failed to map IPI %d\n", i);
break;
}
request_irq(vipi, mpic_ipi_action, IRQF_DISABLED|IRQF_PERCPU,
ipi_names[i], mpic);
err = request_irq(vipi, mpic_ipi_action,
IRQF_DISABLED|IRQF_PERCPU,
ipi_names[i], mpic);
if (err) {
printk(KERN_ERR "Request of irq %d for IPI %d failed\n",
vipi, i);
break;
}
}
}
......
......@@ -26,7 +26,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
{
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC2, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
}
},
......@@ -39,7 +39,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
{
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4,
MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2,
MPC82xx_CPM_MCC2, MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2,
MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
}
},
......@@ -47,52 +47,56 @@ struct ppc_sys_spec ppc_sys_specs[] = {
.ppc_sys_name = "8260",
.mask = 0x0000ff00,
.value = 0x00000000,
.num_devices = 12,
.num_devices = 13,
.device_list = (enum ppc_sys_devices[])
{
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2,
MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
MPC82xx_CPM_I2C,
}
},
{
.ppc_sys_name = "8264",
.mask = 0x0000ff00,
.value = 0x00000000,
.num_devices = 12,
.num_devices = 13,
.device_list = (enum ppc_sys_devices[])
{
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2,
MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
MPC82xx_CPM_I2C,
}
},
{
.ppc_sys_name = "8265",
.mask = 0x0000ff00,
.value = 0x00000000,
.num_devices = 12,
.num_devices = 13,
.device_list = (enum ppc_sys_devices[])
{
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2,
MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
MPC82xx_CPM_I2C,
}
},
{
.ppc_sys_name = "8266",
.mask = 0x0000ff00,
.value = 0x00000000,
.num_devices = 12,
.num_devices = 13,
.device_list = (enum ppc_sys_devices[])
{
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2,
MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
MPC82xx_CPM_I2C,
}
},
/* below is a list of the 8272 family of processors */
......@@ -159,7 +163,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
{
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC2, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
},
},
......@@ -172,7 +176,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
{
MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC2, MPC82xx_CPM_SMC1,
MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
},
},
......
......@@ -24,7 +24,7 @@
#include <asm/uaccess.h>
#include <asm/system.h>
/* If the kernel parameter wdt_enable=1, the watchdog will be enabled at boot.
/* If the kernel parameter wdt=1, the watchdog will be enabled at boot.
* Also, the wdt_period sets the watchdog timer period timeout.
* For E500 cpus the wdt_period sets which bit changing from 0->1 will
* trigger a watchog timeout. This watchdog timeout will occur 3 times, the
......
......@@ -216,7 +216,10 @@ int wf_register_control(struct wf_control *new_ct)
new_ct->attr.attr.mode = 0644;
new_ct->attr.show = wf_show_control;
new_ct->attr.store = wf_store_control;
device_create_file(&wf_platform_device.dev, &new_ct->attr);
if (device_create_file(&wf_platform_device.dev, &new_ct->attr))
printk(KERN_WARNING "windfarm: device_create_file failed"
" for %s\n", new_ct->name);
/* the subsystem still does useful work without the file */
DBG("wf: Registered control %s\n", new_ct->name);
......@@ -326,7 +329,10 @@ int wf_register_sensor(struct wf_sensor *new_sr)
new_sr->attr.attr.mode = 0444;
new_sr->attr.show = wf_show_sensor;
new_sr->attr.store = NULL;
device_create_file(&wf_platform_device.dev, &new_sr->attr);
if (device_create_file(&wf_platform_device.dev, &new_sr->attr))
printk(KERN_WARNING "windfarm: device_create_file failed"
" for %s\n", new_sr->name);
/* the subsystem still does useful work without the file */
DBG("wf: Registered sensor %s\n", new_sr->name);
......
......@@ -302,6 +302,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7448 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_PPC_LE)
#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
......
......@@ -55,8 +55,6 @@
typedef unsigned long long phys_addr_t;
extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
typedef struct {
unsigned long id;
unsigned long vdso_base;
......
......@@ -5,8 +5,8 @@
* this one and the configuration switching is done here.
*/
#ifdef __KERNEL__
#ifndef __ASM_PPC_MPC8260_H__
#define __ASM_PPC_MPC8260_H__
#ifndef __ASM_POWERPC_MPC8260_H__
#define __ASM_POWERPC_MPC8260_H__
#ifdef CONFIG_8260
......@@ -20,5 +20,5 @@
#endif
#endif /* CONFIG_8260 */
#endif /* !__ASM_PPC_MPC8260_H__ */
#endif /* !__ASM_POWERPC_MPC8260_H__ */
#endif /* __KERNEL__ */
......@@ -782,23 +782,8 @@ extern void kernel_set_cachemode (unsigned long address, unsigned long size,
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define kern_addr_valid(addr) (1)
#ifdef CONFIG_PHYS_64BIT
extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
unsigned long paddr, unsigned long size, pgprot_t prot);
static inline int io_remap_pfn_range(struct vm_area_struct *vma,
unsigned long vaddr,
unsigned long pfn,
unsigned long size,
pgprot_t prot)
{
phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
}
#else
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
remap_pfn_range(vma, vaddr, pfn, size, prot)
#endif
/*
* No page table caches to initialise
......
......@@ -28,8 +28,8 @@
*/
#ifdef __KERNEL__
#ifndef __PPC_ASM_PMAC_FEATURE_H
#define __PPC_ASM_PMAC_FEATURE_H
#ifndef __ASM_POWERPC_PMAC_FEATURE_H
#define __ASM_POWERPC_PMAC_FEATURE_H
#include <asm/macio.h>
#include <asm/machdep.h>
......@@ -393,5 +393,5 @@ extern u32 __iomem *uninorth_base;
#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
#endif /* __PPC_ASM_PMAC_FEATURE_H */
#endif /* __ASM_POWERPC_PMAC_FEATURE_H */
#endif /* __KERNEL__ */
......@@ -308,3 +308,6 @@ COMPAT_SYS_SPU(move_pages)
SYSCALL_SPU(getcpu)
COMPAT_SYS(epoll_pwait)
COMPAT_SYS_SPU(utimensat)
COMPAT_SYS_SPU(signalfd)
COMPAT_SYS_SPU(timerfd)
SYSCALL_SPU(eventfd)
......@@ -26,8 +26,8 @@
* demultiplexing on TSI108EMU/SVB boards.
*/
#ifndef _ASM_PPC_TSI108_IRQ_H
#define _ASM_PPC_TSI108_IRQ_H
#ifndef _ASM_POWERPC_TSI108_IRQ_H
#define _ASM_POWERPC_TSI108_IRQ_H
/*
* Tsi108 interrupts
......@@ -121,4 +121,4 @@ typedef enum {
TSI108_IRQ_DIRECTED,
TSI108_IRQ_DISTRIBUTED,
} TSI108_IRQ_MODE;
#endif /* _ASM_PPC_TSI108_IRQ_H */
#endif /* _ASM_POWERPC_TSI108_IRQ_H */
......@@ -18,8 +18,8 @@
* MA 02111-1307 USA
*/
#ifndef _ASM_PPC_TSI108_PCI_H
#define _ASM_PPC_TSI108_PCI_H
#ifndef _ASM_POWERPC_TSI108_PCI_H
#define _ASM_POWERPC_TSI108_PCI_H
#include <asm/tsi108.h>
......@@ -42,4 +42,4 @@ extern void tsi108_pci_int_init(struct device_node *node);
extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
extern void tsi108_clear_pci_cfg_error(void);
#endif /* _ASM_PPC_TSI108_PCI_H */
#endif /* _ASM_POWERPC_TSI108_PCI_H */
#ifndef _ASM_PPC_UNISTD_H_
#define _ASM_PPC_UNISTD_H_
#ifndef _ASM_POWERPC_UNISTD_H_
#define _ASM_POWERPC_UNISTD_H_
/*
* This file contains the system call numbers.
......@@ -327,10 +327,13 @@
#define __NR_getcpu 302
#define __NR_epoll_pwait 303
#define __NR_utimensat 304
#define __NR_signalfd 305
#define __NR_timerfd 306
#define __NR_eventfd 307
#ifdef __KERNEL__
#define __NR_syscalls 305
#define __NR_syscalls 308
#define __NR__exit __NR_exit
#define NR_syscalls __NR_syscalls
......@@ -381,4 +384,4 @@
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_PPC_UNISTD_H_ */
#endif /* _ASM_POWERPC_UNISTD_H_ */
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