Skip to content

L
linux
Commit 347f56fb authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC fixes from Olof Johansson:
 "A set of fixes that we've merged late, but for the most part that have
  been sitting in -next for a while through platform maintainer trees:

   - Fixes to suspend/resume on Tegra, caused by the added features this
     merge window

   - Cleanups and minor fixes to TI additions this merge window

   - Tee fixes queued up late before the merge window, included here.

   - A handful of other fixlets

  There's also a refresh of the shareed config files (multi_v* on
  32-bit, and defconfig on 64-bit), to avoid conflicts when we get new
  contributions"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits)
  ARM: multi_v7_defconfig: Restore debugfs support
  ARM: defconfig: re-run savedefconfig on multi_v* configs
  arm64: defconfig: re-run savedefconfig
  ARM: pxa: Fix resource properties
  soc: mediatek: cmdq: fixup wrong input order of write api
  soc: aspeed: Fix snoop_file_poll()'s return type
  MAINTAINERS: Switch to Marvell addresses
  MAINTAINERS: update Cavium ThunderX drivers
  Revert "arm64: dts: juno: add dma-ranges property"
  MAINTAINERS: Make Nicolas Saenz Julienne the new bcm2835 maintainer
  firmware: arm_scmi: Avoid double free in error flow
  arm64: dts: juno: Fix UART frequency
  ARM: dts: Fix sgx sysconfig register for omap4
  arm: socfpga: execute cold reboot by default
  ARM: dts: Fix vcsi regulator to be always-on for droid4 to prevent hangs
  ARM: dts: dra7: fix cpsw mdio fck clock
  ARM: dts: am57xx-beagle-x15: Update pinmux name to ddr_3_3v
  ARM: dts: omap3-tao3530: Fix incorrect MMC card detection GPIO polarity
  soc/tegra: pmc: Add reset sources and levels on Tegra194
  soc/tegra: pmc: Add missing IRQ callbacks on Tegra194
  ...
parents 98884281 30f55eae
Hide whitespace changes
Inline Side-by-side
Showing with 312 additions and 139 deletions
.mailmap
View file @ 347f56fb
......@@ -105,6 +105,9 @@ James E Wilson <wilson@specifix.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
James Hogan <jhogan@kernel.org> <james@albanarts.com>
James Ketrenos <jketreno@io.(none)>
Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>
Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>
Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
......
MAINTAINERS
View file @ 347f56fb
......@@ -1584,8 +1584,8 @@ S: Maintained
F: arch/arm/mach-cns3xxx/
ARM/CAVIUM THUNDER NETWORK DRIVER
M: Sunil Goutham <sgoutham@cavium.com>
M: Robert Richter <rric@kernel.org>
M: Sunil Goutham <sgoutham@marvell.com>
M: Robert Richter <rrichter@marvell.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
F: drivers/net/ethernet/cavium/thunder/
......@@ -3228,8 +3228,7 @@ N: kona
F: arch/arm/mach-bcm/
BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
M: Eric Anholt <eric@anholt.net>
M: Stefan Wahren <wahrenst@gmx.net>
M: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
L: bcm-kernel-feedback-list@broadcom.com
L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......@@ -3742,9 +3741,8 @@ S: Maintained
F: drivers/net/wireless/ath/carl9170/
CAVIUM I2C DRIVER
M: Jan Glauber <jglauber@cavium.com>
M: David Daney <david.daney@cavium.com>
W: http://www.cavium.com
M: Robert Richter <rrichter@marvell.com>
W: http://www.marvell.com
S: Supported
F: drivers/i2c/busses/i2c-octeon*
F: drivers/i2c/busses/i2c-thunderx*
......@@ -3754,27 +3752,25 @@ M: Derek Chickles <dchickles@marvell.com>
M: Satanand Burla <sburla@marvell.com>
M: Felix Manlunas <fmanlunas@marvell.com>
L: netdev@vger.kernel.org
W: http://www.cavium.com
W: http://www.marvell.com
S: Supported
F: drivers/net/ethernet/cavium/liquidio/
CAVIUM MMC DRIVER
M: Jan Glauber <jglauber@cavium.com>
M: David Daney <david.daney@cavium.com>
M: Steven J. Hill <Steven.Hill@cavium.com>
W: http://www.cavium.com
M: Robert Richter <rrichter@marvell.com>
W: http://www.marvell.com
S: Supported
F: drivers/mmc/host/cavium*
CAVIUM OCTEON-TX CRYPTO DRIVER
M: George Cherian <george.cherian@cavium.com>
M: George Cherian <gcherian@marvell.com>
L: linux-crypto@vger.kernel.org
W: http://www.cavium.com
W: http://www.marvell.com
S: Supported
F: drivers/crypto/cavium/cpt/
CAVIUM THUNDERX2 ARM64 SOC
M: Robert Richter <rrichter@cavium.com>
M: Robert Richter <rrichter@marvell.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/cavium/thunder2-99xx*
......@@ -5892,15 +5888,14 @@ F: drivers/edac/highbank*
EDAC-CAVIUM OCTEON
M: Ralf Baechle <ralf@linux-mips.org>
M: David Daney <david.daney@cavium.com>
M: Robert Richter <rrichter@marvell.com>
L: linux-edac@vger.kernel.org
L: linux-mips@vger.kernel.org
S: Supported
F: drivers/edac/octeon_edac*
EDAC-CAVIUM THUNDERX
M: David Daney <david.daney@cavium.com>
M: Jan Glauber <jglauber@cavium.com>
M: Robert Richter <rrichter@marvell.com>
L: linux-edac@vger.kernel.org
S: Supported
F: drivers/edac/thunderx_edac*
......@@ -12799,7 +12794,7 @@ F: Documentation/devicetree/bindings/pci/axis,artpec*
F: drivers/pci/controller/dwc/*artpec*
PCIE DRIVER FOR CAVIUM THUNDERX
M: David Daney <david.daney@cavium.com>
M: Robert Richter <rrichter@marvell.com>
L: linux-pci@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
......@@ -16372,7 +16367,7 @@ S: Maintained
F: drivers/net/thunderbolt.c
THUNDERX GPIO DRIVER
M: David Daney <david.daney@cavium.com>
M: Robert Richter <rrichter@marvell.com>
S: Maintained
F: drivers/gpio/gpio-thunderx.c
......@@ -18177,10 +18172,9 @@ S: Supported
F: drivers/char/xillybus/
XLP9XX I2C DRIVER
M: George Cherian <george.cherian@cavium.com>
M: Jan Glauber <jglauber@cavium.com>
M: George Cherian <gcherian@marvell.com>
L: linux-i2c@vger.kernel.org
W: http://www.cavium.com
W: http://www.marvell.com
S: Supported
F: Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt
F: drivers/i2c/busses/i2c-xlp9xx.c
......
arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
View file @ 347f56fb
......@@ -24,7 +24,7 @@ &mmc1 {
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v";
pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
......
arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
View file @ 347f56fb
......@@ -24,7 +24,7 @@ &mmc1 {
};
&mmc2 {
pinctrl-names = "default", "hs", "ddr_1_8v";
pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
......
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View file @ 347f56fb
......@@ -19,6 +19,10 @@ memory@0 {
reg = <0 0 0>;
};
aliases {
ethernet0 = &genet;
};
leds {
act {
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
......@@ -97,6 +101,19 @@ &emmc2 {
status = "okay";
};
&genet {
phy-handle = <&phy1>;
phy-mode = "rgmii-rxid";
status = "okay";
};
&genet_mdio {
phy1: ethernet-phy@1 {
/* No PHY interrupt */
reg = <0x1>;
};
};
/* uart0 communicates with the BT module */
&uart0 {
pinctrl-names = "default";
......
arch/arm/boot/dts/bcm2711.dtsi
View file @ 347f56fb
......@@ -12,6 +12,26 @@ / {
interrupt-parent = <&gicv2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
/*
* arm64 reserves the CMA by default somewhere in ZONE_DMA32,
* that's not good enough for the BCM2711 as some devices can
* only address the lower 1G of memory (ZONE_DMA).
*/
linux,cma {
compatible = "shared-dma-pool";
size = <0x2000000>; /* 32MB */
alloc-ranges = <0x0 0x00000000 0x40000000>;
reusable;
linux,cma-default;
};
};
soc {
/*
* Defined ranges:
......@@ -305,6 +325,32 @@ cpu3: cpu@3 {
cpu-release-addr = <0x0 0x000000f0>;
};
};
scb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
genet: ethernet@7d580000 {
compatible = "brcm,bcm2711-genet-v5";
reg = <0x0 0x7d580000 0x10000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
genet_mdio: mdio@e14 {
compatible = "brcm,genet-mdio-v5";
reg = <0xe14 0x8>;
reg-names = "mdio";
#address-cells = <0x0>;
#size-cells = <0x1>;
};
};
};
};
&clk_osc {
......
arch/arm/boot/dts/dra7-l4.dtsi
View file @ 347f56fb
......@@ -3056,7 +3056,7 @@ mac: ethernet@0 {
davinci_mdio: mdio@1000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
clocks = <&gmac_main_clk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts
View file @ 347f56fb
......@@ -11,6 +11,5 @@
#include "logicpd-torpedo-37xx-devkit.dts"
&lcd0 {
/* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
compatible = "logicpd,type28";
};
arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi
View file @ 347f56fb
......@@ -101,6 +101,12 @@ ethernet@gpmc {
};
};
&hdqw1w {
pinctrl-names = "default";
pinctrl-0 = <&hdq_pins>;
};
&vpll2 {
regulator-always-on;
};
......@@ -126,7 +132,6 @@ aliases {
lcd0: display {
/* This isn't the exact LCD, but the timings meet spec */
/* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
compatible = "newhaven,nhd-4.3-480272ef-atxl";
label = "15";
pinctrl-names = "default";
......@@ -169,6 +174,12 @@ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 *
>;
};
hdq_pins: hdq_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */
>;
};
pwm_pins: pinmux_pwm_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */
......
arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
View file @ 347f56fb
......@@ -162,12 +162,12 @@ vcam: VCAM {
regulator-enable-ramp-delay = <1000>;
};
/* Used by DSS */
/* Used by DSS and is the "zerov_regulator" trigger for SoC off mode */
vcsi: VCSI {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <1000>;
regulator-boot-on;
regulator-always-on;
};
vdac: VDAC {
......
arch/arm/boot/dts/omap3-tao3530.dtsi
View file @ 347f56fb
......@@ -222,7 +222,7 @@ &mmc1 {
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
vqmmc-supply = <&vsim>;
cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
bus-width = <8>;
};
......
arch/arm/boot/dts/omap4.dtsi
View file @ 347f56fb
......@@ -330,8 +330,8 @@ abb_iva: regulator-abb-iva {
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5601fc00 0x4>,
<0x5601fc10 0x4>;
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
......
arch/arm/configs/multi_v4t_defconfig
View file @ 347f56fb
......@@ -4,22 +4,19 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_SLOB=y
CONFIG_JUMP_LABEL=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_AT91=y
CONFIG_SOC_AT91RM9200=y
CONFIG_ARCH_CLPS711X=y
CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX1=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_INTEGRATOR_IMPD1=y
CONFIG_INTEGRATOR_CM720T=y
CONFIG_INTEGRATOR_CM920T=y
CONFIG_INTEGRATOR_CM922T_XA10=y
CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX1=y
CONFIG_ARCH_NSPIRE=y
CONFIG_AEABI=y
# CONFIG_ATAGS is not set
......@@ -28,6 +25,8 @@ CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_CLPS711X_CPUIDLE=y
CONFIG_JUMP_LABEL=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_COREDUMP is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
......@@ -81,7 +80,6 @@ CONFIG_FB=y
CONFIG_FB_CLPS711X=y
CONFIG_FB_IMX=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_PWM=y
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
......@@ -92,12 +90,11 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_PWM=y
CONFIG_PWM_ATMEL=y
CONFIG_PWM_CLPS711X=y
CONFIG_PWM_IMX=y
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_CRAMFS=y
CONFIG_MINIX_FS=y
CONFIG_CRC_CCITT=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_CRC_CCITT=y
arch/arm/configs/multi_v5_defconfig
View file @ 347f56fb
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_ASPEED=y
CONFIG_MACH_ASPEED_G4=y
......@@ -59,8 +56,6 @@ CONFIG_MACH_RD88F5181L_GE=y
CONFIG_MACH_RD88F5181L_FXO=y
CONFIG_MACH_RD88F6183AP_GE=y
CONFIG_ARCH_U300=y
CONFIG_PCI_MVEBU=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
......@@ -72,6 +67,10 @@ CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_KIRKWOOD_CPUIDLE=y
CONFIG_OPROFILE=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
......@@ -84,6 +83,7 @@ CONFIG_NET_DSA=y
CONFIG_NET_PKTGEN=m
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_PCI_MVEBU=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_IMX_WEIM=y
......@@ -187,7 +187,6 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_VIDEO_ASPEED=m
CONFIG_VIDEO_ATMEL_ISI=m
CONFIG_DRM=y
......@@ -267,7 +266,6 @@ CONFIG_DMADEVICES=y
CONFIG_AT_HDMAC=y
CONFIG_MV_XOR=y
CONFIG_STAGING=y
CONFIG_FB_XGI=y
CONFIG_ASPEED_LPC_CTRL=m
CONFIG_ASPEED_LPC_SNOOP=m
CONFIG_ASPEED_P2A_CTRL=m
......@@ -296,6 +294,11 @@ CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_UTF8=y
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
......@@ -304,8 +307,3 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
arch/arm/configs/multi_v7_defconfig
View file @ 347f56fb
......@@ -131,8 +131,6 @@ CONFIG_CRYPTO_AES_ARM_CE=m
CONFIG_CRYPTO_GHASH_ARM_CE=m
CONFIG_CRYPTO_CRC32_ARM_CE=m
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_GCC_PLUGINS=y
CONFIG_GCC_PLUGIN_STRUCTLEAK=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
......@@ -185,7 +183,6 @@ CONFIG_PCI_TEGRA=y
CONFIG_PCI_RCAR_GEN2=y
CONFIG_PCIE_RCAR=y
CONFIG_PCI_DRA7XX_EP=y
CONFIG_PCI_KEYSTONE=y
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
CONFIG_PCI_EPF_TEST=m
......@@ -200,15 +197,14 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_BRCMNAND=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_VF610_NFC=y
CONFIG_MTD_NAND_DAVINCI=y
CONFIG_MTD_NAND_STM32_FMC2=y
......@@ -272,11 +268,11 @@ CONFIG_STMMAC_ETH=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_TI_CPSW=y
CONFIG_XILINX_EMACLITE=y
CONFIG_AT803X_PHY=y
CONFIG_BROADCOM_PHY=y
CONFIG_ICPLUS_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_AT803X_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_USB_PEGASUS=y
......@@ -390,7 +386,6 @@ CONFIG_I2C_DAVINCI=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DIGICOLOR=m
CONFIG_I2C_EMEV2=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IMX=y
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
......@@ -481,8 +476,8 @@ CONFIG_BATTERY_BQ27XXX=m
CONFIG_AXP20X_POWER=m
CONFIG_BATTERY_MAX17040=m
CONFIG_BATTERY_MAX17042=m
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_CPCAP=m
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MAX14577=m
CONFIG_CHARGER_MAX77693=m
CONFIG_CHARGER_MAX8997=m
......@@ -539,10 +534,6 @@ CONFIG_MFD_BCM590XX=y
CONFIG_MFD_AC100=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
CONFIG_MFD_CROS_EC=m
CONFIG_CROS_EC_I2C=m
CONFIG_CROS_EC_SPI=m
CONFIG_MFD_CROS_EC_CHARDEV=m
CONFIG_MFD_DA9063=m
CONFIG_MFD_MAX14577=y
CONFIG_MFD_MAX77686=y
......@@ -644,7 +635,6 @@ CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_VIVID=m
CONFIG_CEC_PLATFORM_DRIVERS=y
CONFIG_VIDEO_SAMSUNG_S5P_CEC=m
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_DRM=y
......@@ -697,7 +687,6 @@ CONFIG_FB_EFI=y
CONFIG_FB_WM8505=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_SIMPLE=y
CONFIG_LCD_PLATFORM=m
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_BACKLIGHT_GPIO=y
......@@ -946,6 +935,9 @@ CONFIG_SERIO_NVEC_PS2=y
CONFIG_NVEC_POWER=y
CONFIG_NVEC_PAZ00=y
CONFIG_STAGING_BOARD=y
CONFIG_MFD_CROS_EC=m
CONFIG_CROS_EC_I2C=m
CONFIG_CROS_EC_SPI=m
CONFIG_COMMON_CLK_MAX77686=y
CONFIG_COMMON_CLK_RK808=m
CONFIG_COMMON_CLK_S2MPS11=m
......@@ -1012,16 +1004,15 @@ CONFIG_BERLIN2_ADC=m
CONFIG_CPCAP_ADC=m
CONFIG_EXYNOS_ADC=m
CONFIG_MESON_SARADC=m
CONFIG_ROCKCHIP_SARADC=m
CONFIG_STM32_ADC_CORE=m
CONFIG_STM32_ADC=m
CONFIG_STM32_DFSDM_ADC=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=y
CONFIG_STM32_LPTIMER_CNT=m
CONFIG_STM32_DAC=m
CONFIG_ROCKCHIP_SARADC=m
CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
CONFIG_STM32_DAC=m
CONFIG_MPU3050_I2C=y
CONFIG_CM36651=m
CONFIG_IIO_CROS_EC_LIGHT_PROX=m
......@@ -1072,11 +1063,11 @@ CONFIG_PHY_DM816X_USB=m
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_TWL4030_USB=m
CONFIG_MESON_MX_EFUSE=m
CONFIG_ROCKCHIP_EFUSE=m
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_ROCKCHIP_EFUSE=m
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_VF610_OCOTP=y
CONFIG_MESON_MX_EFUSE=m
CONFIG_FSI=m
CONFIG_FSI_MASTER_GPIO=m
CONFIG_FSI_MASTER_HUB=m
......@@ -1110,14 +1101,15 @@ CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_USER_API_AEAD=m
CONFIG_CRYPTO_DEV_SUN4I_SS=m
CONFIG_CRYPTO_DEV_MARVELL_CESA=m
CONFIG_CRYPTO_DEV_EXYNOS_RNG=m
CONFIG_CRYPTO_DEV_S5P=m
CONFIG_CRYPTO_DEV_ATMEL_AES=m
CONFIG_CRYPTO_DEV_ATMEL_TDES=m
CONFIG_CRYPTO_DEV_ATMEL_SHA=m
CONFIG_CRYPTO_DEV_SUN4I_SS=m
CONFIG_CRYPTO_DEV_ROCKCHIP=m
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
arch/arm/mach-omap2/timer.c
View file @ 347f56fb
......@@ -545,7 +545,7 @@ static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src
omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
/* Enable the use of clocksource="gp_timer" kernel parameter */
if (use_gptimer_clksrc || gptimer)
if (clksrc_nr && (use_gptimer_clksrc || gptimer))
omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
clksrc_prop);
else
......@@ -586,7 +586,7 @@ void __init omap3_gptimer_timer_init(void)
static void __init omap4_sync32k_timer_init(void)
{
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
2, "sys_clkin_ck", NULL, false);
0, NULL, NULL, false);
}
void __init omap4_local_timer_init(void)
......
arch/arm/mach-pxa/icontrol.c
View file @ 347f56fb
......@@ -89,7 +89,7 @@ static struct spi_board_info mcp251x_board_info[] = {
.max_speed_hz = 6500000,
.bus_num = 3,
.chip_select = 1,
.platform_data = &mcp251x_info,
.properties = mcp251x_properties,
.controller_data = &mcp251x_chip_info2,
.irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ2)
},
......@@ -98,7 +98,7 @@ static struct spi_board_info mcp251x_board_info[] = {
.max_speed_hz = 6500000,
.bus_num = 4,
.chip_select = 0,
.platform_data = &mcp251x_info,
.properties = mcp251x_properties,
.controller_data = &mcp251x_chip_info3,
.irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ3)
},
......@@ -107,7 +107,7 @@ static struct spi_board_info mcp251x_board_info[] = {
.max_speed_hz = 6500000,
.bus_num = 4,
.chip_select = 1,
.platform_data = &mcp251x_info,
.properties = mcp251x_properties,
.controller_data = &mcp251x_chip_info4,
.irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ4)
}
......
arch/arm/mach-socfpga/socfpga.c
View file @ 347f56fb
......@@ -73,10 +73,10 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
if (mode == REBOOT_HARD)
temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
else
if (mode == REBOOT_WARM)
temp |= RSTMGR_CTRL_SWWARMRSTREQ;
else
temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
}
......@@ -86,10 +86,10 @@ static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
if (mode == REBOOT_HARD)
temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
else
if (mode == REBOOT_WARM)
temp |= RSTMGR_CTRL_SWWARMRSTREQ;
else
temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
}
......
arch/arm64/boot/dts/arm/juno-base.dtsi
View file @ 347f56fb
......@@ -6,7 +6,6 @@ / {
/*
* Devices shared by all Juno boards
*/
dma-ranges = <0 0 0 0 0x100 0>;
memtimer: timer@2a810000 {
compatible = "arm,armv7-timer-mem";
......
arch/arm64/boot/dts/arm/juno-clocks.dtsi
View file @ 347f56fb
......@@ -8,10 +8,10 @@
*/
/ {
/* SoC fixed clocks */
soc_uartclk: refclk7273800hz {
soc_uartclk: refclk7372800hz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <7273800>;
clock-frequency = <7372800>;
clock-output-names = "juno:uartclk";
};
......
arch/arm64/configs/defconfig
View file @ 347f56fb
......@@ -7,8 +7,6 @@ CONFIG_PREEMPT=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y
......@@ -94,7 +92,6 @@ CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_INTEL_STRATIX10_SERVICE=y
CONFIG_INTEL_STRATIX10_RSU=m
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_EFI_CAPSULE_LOADER=y
CONFIG_IMX_SCU=y
CONFIG_IMX_SCU_PD=y
......@@ -118,8 +115,6 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_CHACHA20_NEON=m
CONFIG_CRYPTO_AES_ARM64_BS=m
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN8I_CE=m
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
......@@ -127,7 +122,6 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_KSM=y
CONFIG_MEMORY_FAILURE=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
......@@ -211,7 +205,6 @@ CONFIG_HISILICON_LPC=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_MARVELL=y
......@@ -272,18 +265,12 @@ CONFIG_HNS3_ENET=y
CONFIG_E1000E=y
CONFIG_IGB=y
CONFIG_IGBVF=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=m
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
CONFIG_MVNETA=y
CONFIG_MVPP2=y
CONFIG_SKY2=y
CONFIG_MLX4_EN=m
CONFIG_MLX5_CORE=m
CONFIG_MLX5_CORE_EN=y
CONFIG_QCOM_EMAC=m
CONFIG_RAVB=y
CONFIG_SMC91X=y
......@@ -292,11 +279,11 @@ CONFIG_SNI_AVE=y
CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_AT803X_PHY=y
CONFIG_MARVELL_PHY=m
CONFIG_MARVELL_10G_PHY=m
CONFIG_MESON_GXL_PHY=m
CONFIG_MICREL_PHY=y
CONFIG_AT803X_PHY=y
CONFIG_REALTEK_PHY=m
CONFIG_ROCKCHIP_PHY=y
CONFIG_USB_PEGASUS=m
......@@ -402,8 +389,8 @@ CONFIG_SPI_PL022=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_QUP=y
CONFIG_SPI_S3C64XX=y
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_SUN6I=y
CONFIG_SPI_SPIDEV=m
CONFIG_SPMI=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_MAX77620=y
......@@ -477,8 +464,6 @@ CONFIG_MFD_ALTERA_SYSMGR=y
CONFIG_MFD_BD9571MWV=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
CONFIG_MFD_CROS_EC=y
CONFIG_MFD_CROS_EC_CHARDEV=m
CONFIG_MFD_EXYNOS_LPASS=m
CONFIG_MFD_HI6421_PMIC=y
CONFIG_MFD_HI655X_PMIC=y
......@@ -673,9 +658,9 @@ CONFIG_RTC_DRV_SNVS=m
CONFIG_RTC_DRV_IMX_SC=m
CONFIG_RTC_DRV_XGENE=y
CONFIG_DMADEVICES=y
CONFIG_FSL_EDMA=y
CONFIG_DMA_BCM2835=m
CONFIG_DMA_SUN6I=m
CONFIG_FSL_EDMA=y
CONFIG_IMX_SDMA=y
CONFIG_K3_DMA=y
CONFIG_MV_XOR=y
......@@ -694,6 +679,7 @@ CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_MFD_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_SPI=y
CONFIG_COMMON_CLK_RK808=y
......@@ -727,7 +713,6 @@ CONFIG_ARM_MHU=y
CONFIG_IMX_MBOX=y
CONFIG_PLATFORM_MHU=y
CONFIG_BCM2835_MBOX=y
CONFIG_TI_MESSAGE_MANAGER=y
CONFIG_QCOM_APCS_IPC=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_TEGRA_IOMMU_SMMU=y
......@@ -743,7 +728,6 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=m
CONFIG_RPMSG_QCOM_SMD=y
CONFIG_RASPBERRYPI_POWER=y
CONFIG_IMX_SCU_SOC=y
CONFIG_QCOM_COMMAND_DB=y
CONFIG_QCOM_GENI_SE=y
CONFIG_QCOM_GLINK_SSR=m
CONFIG_QCOM_RPMH=y
......@@ -769,9 +753,7 @@ CONFIG_ARCH_TEGRA_186_SOC=y
CONFIG_ARCH_TEGRA_194_SOC=y
CONFIG_ARCH_K3_AM6_SOC=y
CONFIG_ARCH_K3_J721E_SOC=y
CONFIG_SOC_TI=y
CONFIG_TI_SCI_PM_DOMAINS=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
CONFIG_MEMORY=y
......@@ -819,11 +801,11 @@ CONFIG_FSL_IMX8_DDR_PMU=m
CONFIG_HISI_PMU=y
CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_NVMEM_IMX_OCOTP_SCU=y
CONFIG_QCOM_QFPROM=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_UNIPHIER_EFUSE=y
CONFIG_MESON_EFUSE=m
CONFIG_FPGA=y
......@@ -862,8 +844,8 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE=m
CONFIG_CRYPTO_DEV_HISI_ZIP=m
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
......
drivers/bus/ti-sysc.c
View file @ 347f56fb
......@@ -1242,6 +1242,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_QUIRK_SWSUP_SIDLE),
/* Quirks that need to be set based on detected module */
SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff,
SYSC_MODULE_QUIRK_AESS),
SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
SYSC_MODULE_QUIRK_HDQ1W),
SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
......@@ -1270,7 +1272,6 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
#ifdef DEBUG
SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
......@@ -1402,6 +1403,14 @@ static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
sysc_write(ddata, offset, val);
}
/* AESS (Audio Engine SubSystem) needs autogating set after enable */
static void sysc_module_enable_quirk_aess(struct sysc *ddata)
{
int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
sysc_write(ddata, offset, 1);
}
/* I2C needs extra enable bit toggling for reset */
static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
{
......@@ -1484,6 +1493,9 @@ static void sysc_init_module_quirks(struct sysc *ddata)
return;
}
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
......@@ -1766,9 +1778,8 @@ static int sysc_child_add_named_clock(struct sysc *ddata,
clk = clk_get(child, name);
if (!IS_ERR(clk)) {
clk_put(clk);
return -EEXIST;
error = -EEXIST;
goto put_clk;
}
clk = clk_get(ddata->dev, name);
......@@ -1778,7 +1789,7 @@ static int sysc_child_add_named_clock(struct sysc *ddata,
l = clkdev_create(clk, name, dev_name(child));
if (!l)
error = -ENOMEM;
put_clk:
clk_put(clk);
return error;
......
drivers/cpufreq/tegra124-cpufreq.c
View file @ 347f56fb
......@@ -6,6 +6,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
......@@ -128,8 +129,66 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
return ret;
}
static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
{
struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
int err;
/*
* PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
* use during suspend and resume. So, switch the CPU clock source
* to PLLP and disable DFLL.
*/
err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
if (err < 0) {
dev_err(dev, "failed to reparent to PLLP: %d\n", err);
return err;
}
clk_disable_unprepare(priv->dfll_clk);
return 0;
}
static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
{
struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
int err;
/*
* Warmboot code powers up the CPU with PLLP clock source.
* Enable DFLL clock and switch CPU clock source back to DFLL.
*/
err = clk_prepare_enable(priv->dfll_clk);
if (err < 0) {
dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
goto disable_cpufreq;
}
err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
if (err < 0) {
dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
goto disable_dfll;
}
return 0;
disable_dfll:
clk_disable_unprepare(priv->dfll_clk);
disable_cpufreq:
disable_cpufreq();
return err;
}
static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
tegra124_cpufreq_resume)
};
static struct platform_driver tegra124_cpufreq_platdrv = {
.driver.name = "cpufreq-tegra124",
.driver.pm = &tegra124_cpufreq_pm_ops,
.probe = tegra124_cpufreq_probe,
};
......
drivers/firmware/arm_scmi/bus.c
View file @ 347f56fb
......@@ -135,8 +135,10 @@ scmi_device_create(struct device_node *np, struct device *parent, int protocol)
return NULL;
id = ida_simple_get(&scmi_bus_id, 1, 0, GFP_KERNEL);
if (id < 0)
goto free_mem;
if (id < 0) {
kfree(scmi_dev);
return NULL;
}
scmi_dev->id = id;
scmi_dev->protocol_id = protocol;
......@@ -154,8 +156,6 @@ scmi_device_create(struct device_node *np, struct device *parent, int protocol)
put_dev:
put_device(&scmi_dev->dev);
ida_simple_remove(&scmi_bus_id, id);
free_mem:
kfree(scmi_dev);
return NULL;
}
......
drivers/memory/tegra/tegra30-emc.c
View file @ 347f56fb
......@@ -1093,7 +1093,7 @@ static int tegra_emc_probe(struct platform_device *pdev)
if (of_get_child_count(pdev->dev.of_node) == 0) {
dev_info(&pdev->dev,
"device-tree node doesn't have memory timings\n");
return 0;
return -ENODEV;
}
np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0);
......
drivers/soc/aspeed/aspeed-lpc-snoop.c
View file @ 347f56fb
......@@ -97,13 +97,13 @@ static ssize_t snoop_file_read(struct file *file, char __user *buffer,
return ret ? ret : copied;
}
static unsigned int snoop_file_poll(struct file *file,
static __poll_t snoop_file_poll(struct file *file,
struct poll_table_struct *pt)
{
struct aspeed_lpc_snoop_channel *chan = snoop_file_to_chan(file);
poll_wait(file, &chan->wq, pt);
return !kfifo_is_empty(&chan->fifo) ? POLLIN : 0;
return !kfifo_is_empty(&chan->fifo) ? EPOLLIN : 0;
}
static const struct file_operations snoop_fops = {
......
drivers/soc/mediatek/mtk-cmdq-helper.c
View file @ 347f56fb
......@@ -155,7 +155,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
offset_mask |= CMDQ_WRITE_ENABLE_MASK;
}
err |= cmdq_pkt_write(pkt, value, subsys, offset_mask);
err |= cmdq_pkt_write(pkt, subsys, offset_mask, value);
return err;
}
......
drivers/soc/tegra/pmc.c
View file @ 347f56fb
......@@ -2804,7 +2804,7 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = {
.dpd2_status = 0x80,
.rst_status = 0x70,
.rst_source_shift = 0x2,
.rst_source_mask = 0x3C,
.rst_source_mask = 0x3c,
.rst_level_shift = 0x0,
.rst_level_mask = 0x3,
};
......@@ -2926,6 +2926,43 @@ static const struct tegra_io_pad_soc tegra194_io_pads[] = {
{ .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
};
static const struct tegra_pmc_regs tegra194_pmc_regs = {
.scratch0 = 0x2000,
.dpd_req = 0x74,
.dpd_status = 0x78,
.dpd2_req = 0x7c,
.dpd2_status = 0x80,
.rst_status = 0x70,
.rst_source_shift = 0x2,
.rst_source_mask = 0x7c,
.rst_level_shift = 0x0,
.rst_level_mask = 0x3,
};
static const char * const tegra194_reset_sources[] = {
"SYS_RESET_N",
"AOWDT",
"BCCPLEXWDT",
"BPMPWDT",
"SCEWDT",
"SPEWDT",
"APEWDT",
"LCCPLEXWDT",
"SENSOR",
"AOTAG",
"VFSENSOR",
"MAINSWRST",
"SC7",
"HSM",
"CSITE",
"RCEWDT",
"PVA0WDT",
"PVA1WDT",
"L1A_ASYNC",
"BPMPBOOT",
"FUSECRC",
};
static const struct tegra_wake_event tegra194_wake_events[] = {
TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
TEGRA_WAKE_IRQ("rtc", 73, 10),
......@@ -2943,9 +2980,15 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
.maybe_tz_only = false,
.num_io_pads = ARRAY_SIZE(tegra194_io_pads),
.io_pads = tegra194_io_pads,
.regs = &tegra186_pmc_regs,
.regs = &tegra194_pmc_regs,
.init = NULL,
.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
.irq_set_wake = tegra186_pmc_irq_set_wake,
.irq_set_type = tegra186_pmc_irq_set_type,
.reset_sources = tegra194_reset_sources,
.num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
.reset_levels = tegra186_reset_levels,
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.num_wake_events = ARRAY_SIZE(tegra194_wake_events),
.wake_events = tegra194_wake_events,
};
......
drivers/tee/optee/call.c
View file @ 347f56fb
......@@ -554,6 +554,13 @@ static int check_mem_type(unsigned long start, size_t num_pages)
struct mm_struct *mm = current->mm;
int rc;
/*
* Allow kernel address to register with OP-TEE as kernel
* pages are configured as normal memory only.
*/
if (virt_addr_valid(start))
return 0;
down_read(&mm->mmap_sem);
rc = __check_mem_type(find_vma(mm, start),
start + num_pages * PAGE_SIZE);
......
drivers/tee/optee/core.c
View file @ 347f56fb
......@@ -643,11 +643,6 @@ static struct optee *optee_probe(struct device_node *np)
if (optee->sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM)
pr_info("dynamic shared memory is enabled\n");
rc = optee_enumerate_devices();
if (rc)
goto err;
pr_info("initialized driver\n");
return optee;
err:
if (optee) {
......@@ -702,9 +697,10 @@ static struct optee *optee_svc;
static int __init optee_driver_init(void)
{
struct device_node *fw_np;
struct device_node *np;
struct optee *optee;
struct device_node *fw_np = NULL;
struct device_node *np = NULL;
struct optee *optee = NULL;
int rc = 0;
/* Node is supposed to be below /firmware */
fw_np = of_find_node_by_name(NULL, "firmware");
......@@ -723,6 +719,14 @@ static int __init optee_driver_init(void)
if (IS_ERR(optee))
return PTR_ERR(optee);
rc = optee_enumerate_devices();
if (rc) {
optee_remove(optee);
return rc;
}
pr_info("initialized driver\n");
optee_svc = optee;
return 0;
......
drivers/tee/optee/shm_pool.c
View file @ 347f56fb
......@@ -17,6 +17,7 @@ static int pool_op_alloc(struct tee_shm_pool_mgr *poolm,
{
unsigned int order = get_order(size);
struct page *page;
int rc = 0;
page = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
if (!page)
......@@ -26,12 +27,21 @@ static int pool_op_alloc(struct tee_shm_pool_mgr *poolm,
shm->paddr = page_to_phys(page);
shm->size = PAGE_SIZE << order;
return 0;
if (shm->flags & TEE_SHM_DMA_BUF) {
shm->flags |= TEE_SHM_REGISTER;
rc = optee_shm_register(shm->ctx, shm, &page, 1 << order,
(unsigned long)shm->kaddr);
}
return rc;
}
static void pool_op_free(struct tee_shm_pool_mgr *poolm,
struct tee_shm *shm)
{
if (shm->flags & TEE_SHM_DMA_BUF)
optee_shm_unregister(shm->ctx, shm);
free_pages((unsigned long)shm->kaddr, get_order(shm->size));
shm->kaddr = NULL;
}
......
include/linux/platform_data/ti-sysc.h
View file @ 347f56fb
......@@ -49,6 +49,7 @@ struct sysc_regbits {
s8 emufree_shift;
};
#define SYSC_MODULE_QUIRK_AESS BIT(19)
#define SYSC_MODULE_QUIRK_SGX BIT(18)
#define SYSC_MODULE_QUIRK_HDQ1W BIT(17)
#define SYSC_MODULE_QUIRK_I2C BIT(16)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7