Commit 348c2298 authored by Kevin Hao's avatar Kevin Hao Committed by Benjamin Herrenschmidt

powerpc: Don't flush/invalidate the d/icache for an unknown relocation type

For an unknown relocation type since the value of r4 is just the 8bit
relocation type, the sum of r4 and r7 may yield an invalid memory
address. For example:
    In normal case:
             r4 = c00xxxxx
             r7 = 40000000
             r4 + r7 = 000xxxxx

    For an unknown relocation type:
             r4 = 000000xx
             r7 = 40000000
             r4 + r7 = 400000xx
   400000xx is an invalid memory address for a board which has just
   512M memory.

And for operations such as dcbst or icbi may cause bus error for an
invalid memory address on some platforms and then cause the board
reset. So we should skip the flush/invalidate the d/icache for
an unknown relocation type.
Signed-off-by: default avatarKevin Hao <haokexin@gmail.com>
Acked-by: default avatarSuzuki K. Poulose <suzuki@in.ibm.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 4bb29711
...@@ -166,7 +166,7 @@ ha16: ...@@ -166,7 +166,7 @@ ha16:
/* R_PPC_ADDR16_LO */ /* R_PPC_ADDR16_LO */
lo16: lo16:
cmpwi r4, R_PPC_ADDR16_LO cmpwi r4, R_PPC_ADDR16_LO
bne nxtrela bne unknown_type
lwz r4, 0(r9) /* r_offset */ lwz r4, 0(r9) /* r_offset */
lwz r0, 8(r9) /* r_addend */ lwz r0, 8(r9) /* r_addend */
add r0, r0, r3 add r0, r0, r3
...@@ -191,6 +191,7 @@ nxtrela: ...@@ -191,6 +191,7 @@ nxtrela:
dcbst r4,r7 dcbst r4,r7
sync /* Ensure the data is flushed before icbi */ sync /* Ensure the data is flushed before icbi */
icbi r4,r7 icbi r4,r7
unknown_type:
cmpwi r8, 0 /* relasz = 0 ? */ cmpwi r8, 0 /* relasz = 0 ? */
ble done ble done
add r9, r9, r6 /* move to next entry in the .rela table */ add r9, r9, r6 /* move to next entry in the .rela table */
......
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