Commit 355c8db1 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/powerplay: commit get_performance_level API as DAL needed

This can suppress the error reported on driver loading. Also these
are empty APIs as Vega12/Vega20 has no performance levels.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3b2ad16d
...@@ -2356,6 +2356,13 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) ...@@ -2356,6 +2356,13 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
return vega12_disable_gfx_off(hwmgr); return vega12_disable_gfx_off(hwmgr);
} }
static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
PHM_PerformanceLevelDesignation designation, uint32_t index,
PHM_PerformanceLevel *level)
{
return 0;
}
static const struct pp_hwmgr_func vega12_hwmgr_funcs = { static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
.backend_init = vega12_hwmgr_backend_init, .backend_init = vega12_hwmgr_backend_init,
.backend_fini = vega12_hwmgr_backend_fini, .backend_fini = vega12_hwmgr_backend_fini,
...@@ -2406,6 +2413,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = { ...@@ -2406,6 +2413,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
.register_irq_handlers = smu9_register_irq_handlers, .register_irq_handlers = smu9_register_irq_handlers,
.start_thermal_controller = vega12_start_thermal_controller, .start_thermal_controller = vega12_start_thermal_controller,
.powergate_gfx = vega12_gfx_off_control, .powergate_gfx = vega12_gfx_off_control,
.get_performance_level = vega12_get_performance_level,
}; };
int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
......
...@@ -2041,6 +2041,13 @@ int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr, ...@@ -2041,6 +2041,13 @@ int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
return result; return result;
} }
static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
PHM_PerformanceLevelDesignation designation, uint32_t index,
PHM_PerformanceLevel *level)
{
return 0;
}
static int vega20_notify_smc_display_config_after_ps_adjustment( static int vega20_notify_smc_display_config_after_ps_adjustment(
struct pp_hwmgr *hwmgr) struct pp_hwmgr *hwmgr)
{ {
...@@ -3487,6 +3494,8 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = { ...@@ -3487,6 +3494,8 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
vega20_set_watermarks_for_clocks_ranges, vega20_set_watermarks_for_clocks_ranges,
.display_clock_voltage_request = .display_clock_voltage_request =
vega20_display_clock_voltage_request, vega20_display_clock_voltage_request,
.get_performance_level =
vega20_get_performance_level,
/* UMD pstate, profile related */ /* UMD pstate, profile related */
.force_dpm_level = .force_dpm_level =
vega20_dpm_force_dpm_level, vega20_dpm_force_dpm_level,
......
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