Commit 35997ff0 authored by Sebastian Hahn's avatar Sebastian Hahn Committed by Greg Kroah-Hartman

staging/rtl8192u: cleanfile run

Run cleanfile on all files inside drivers/staging/rtl819u
Signed-off-by: default avatarSebastian Hahn <snsehahn@cip.cs.fau.de>
Signed-off-by: default avatarJennifer Naumann <Jennifer.Naumann@informatik.stud.uni-erlangen.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 14de7448
......@@ -2,4 +2,3 @@ v 0.1
First version.
This is based on the rtl8180-sa2400 pre-0.22-CVS code..
......@@ -25,4 +25,3 @@ obj-m +=ieee80211_crypt-rsl.o
obj-m +=ieee80211_crypt_wep-rsl.o
obj-m +=ieee80211_crypt_tkip-rsl.o
obj-m +=ieee80211_crypt_ccmp-rsl.o
......@@ -443,7 +443,7 @@ static struct crypto_alg aes_alg = {
.cipher = {
.cia_min_keysize = AES_MIN_KEY_SIZE,
.cia_max_keysize = AES_MAX_KEY_SIZE,
.cia_setkey = aes_set_key,
.cia_setkey = aes_set_key,
.cia_encrypt = aes_encrypt,
.cia_decrypt = aes_decrypt
}
......@@ -466,4 +466,3 @@ module_exit(aes_fini);
MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm");
MODULE_LICENSE("Dual BSD/GPL");
......@@ -79,7 +79,7 @@ static struct crypto_alg arc4_alg = {
.cra_u = { .cipher = {
.cia_min_keysize = ARC4_MIN_KEY_SIZE,
.cia_max_keysize = ARC4_MAX_KEY_SIZE,
.cia_setkey = arc4_set_key,
.cia_setkey = arc4_set_key,
.cia_encrypt = arc4_crypt,
.cia_decrypt = arc4_crypt } }
};
......
......@@ -56,5 +56,3 @@ static inline int crypto_cipher_decrypt(struct crypto_tfm *tfm,
}
//EXPORT_SYMBOL_GPL(crypto_alloc_tfm);
//EXPORT_SYMBOL_GPL(crypto_free_tfm);
......@@ -218,4 +218,3 @@ EXPORT_SYMBOL(DOT11D_GetMaxTxPwrInDbm);
EXPORT_SYMBOL(DOT11D_ScanComplete);
EXPORT_SYMBOL(IsLegalChannel);
EXPORT_SYMBOL(ToLegalChannel);
......@@ -64,7 +64,7 @@
#endif
#define KEY_TYPE_NA 0x0
#define KEY_TYPE_WEP40 0x1
#define KEY_TYPE_WEP40 0x1
#define KEY_TYPE_TKIP 0x2
#define KEY_TYPE_CCMP 0x4
#define KEY_TYPE_WEP104 0x5
......@@ -195,21 +195,21 @@ enum _ReasonCode{
auth_not_valid = 0x2,
deauth_lv_ss = 0x3,
inactivity = 0x4,
ap_overload = 0x5,
ap_overload = 0x5,
class2_err = 0x6,
class3_err = 0x7,
disas_lv_ss = 0x8,
disas_lv_ss = 0x8,
asoc_not_auth = 0x9,
//----MIC_CHECK
mic_failure = 0xe,
mic_failure = 0xe,
//----END MIC_CHECK
// Reason code defined in 802.11i D10.0 p.28.
invalid_IE = 0x0d,
four_way_tmout = 0x0f,
two_way_tmout = 0x10,
IE_dismatch = 0x11,
IE_dismatch = 0x11,
invalid_Gcipher = 0x12,
invalid_Pcipher = 0x13,
invalid_AKMP = 0x14,
......@@ -222,7 +222,7 @@ enum _ReasonCode{
QoS_unspec = 0x20, // 32
QAP_bandwidth = 0x21, // 33
poor_condition = 0x22, // 34
no_facility = 0x23, // 35
no_facility = 0x23, // 35
// Where is 36???
req_declined = 0x25, // 37
invalid_param = 0x26, // 38
......@@ -265,7 +265,7 @@ enum _ReasonCode{
#define IEEE_WPAX_USEGROUP 0
#define IEEE_WPAX_WEP40 1
#define IEEE_WPAX_TKIP 2
#define IEEE_WPAX_WRAP 3
#define IEEE_WPAX_WRAP 3
#define IEEE_WPAX_CCMP 4
#define IEEE_WPAX_WEP104 5
......@@ -289,12 +289,12 @@ enum _ReasonCode{
#define MAX_IE_LEN 0xff
// added for kernel conflict
#define ieee80211_crypt_deinit_entries ieee80211_crypt_deinit_entries_rsl
#define ieee80211_crypt_deinit_handler ieee80211_crypt_deinit_handler_rsl
#define ieee80211_crypt_delayed_deinit ieee80211_crypt_delayed_deinit_rsl
#define ieee80211_register_crypto_ops ieee80211_register_crypto_ops_rsl
#define ieee80211_crypt_deinit_entries ieee80211_crypt_deinit_entries_rsl
#define ieee80211_crypt_deinit_handler ieee80211_crypt_deinit_handler_rsl
#define ieee80211_crypt_delayed_deinit ieee80211_crypt_delayed_deinit_rsl
#define ieee80211_register_crypto_ops ieee80211_register_crypto_ops_rsl
#define ieee80211_unregister_crypto_ops ieee80211_unregister_crypto_ops_rsl
#define ieee80211_get_crypto_ops ieee80211_get_crypto_ops_rsl
#define ieee80211_get_crypto_ops ieee80211_get_crypto_ops_rsl
#define ieee80211_ccmp_null ieee80211_ccmp_null_rsl
......@@ -302,10 +302,10 @@ enum _ReasonCode{
#define ieee80211_wep_null ieee80211_wep_null_rsl
#define free_ieee80211 free_ieee80211_rsl
#define alloc_ieee80211 alloc_ieee80211_rsl
#define free_ieee80211 free_ieee80211_rsl
#define alloc_ieee80211 alloc_ieee80211_rsl
#define ieee80211_rx ieee80211_rx_rsl
#define ieee80211_rx ieee80211_rx_rsl
#define ieee80211_rx_mgt ieee80211_rx_mgt_rsl
#define ieee80211_get_beacon ieee80211_get_beacon_rsl
......@@ -450,7 +450,7 @@ typedef struct ieee_param {
/* management */
#define IEEE80211_STYPE_ASSOC_REQ 0x0000
#define IEEE80211_STYPE_ASSOC_RESP 0x0010
#define IEEE80211_STYPE_ASSOC_RESP 0x0010
#define IEEE80211_STYPE_REASSOC_REQ 0x0020
#define IEEE80211_STYPE_REASSOC_RESP 0x0030
#define IEEE80211_STYPE_PROBE_REQ 0x0040
......@@ -536,7 +536,7 @@ do { if (ieee80211_debug_level & (level)) \
//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
#define IEEE80211_DEBUG_DATA(level, data, datalen) \
do{ if ((ieee80211_debug_level & (level)) == (level)) \
{ \
{ \
int i; \
u8* pdata = (u8*) data; \
printk(KERN_DEBUG "ieee80211: %s()\n", __FUNCTION__); \
......@@ -623,20 +623,20 @@ do { if (ieee80211_debug_level & (level)) \
#define MAX_STR_LEN 64
/* I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.*/
#define PRINTABLE(_ch) (_ch>'!' && _ch<'~')
#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) \
if((_Comp) & level) \
#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) \
if((_Comp) & level) \
{ \
int __i; \
u8 buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
memset(buffer, 0, MAX_STR_LEN); \
memcpy(buffer, (u8 *)_Ptr, length ); \
u8 buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
memset(buffer, 0, MAX_STR_LEN); \
memcpy(buffer, (u8 *)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
printk("Rtl819x: "); \
printk("Rtl819x: "); \
printk(_TitleString); \
printk(": %d, <%s>\n", _Len, buffer); \
}
......@@ -785,12 +785,12 @@ enum ieee80211_reasoncode {
#define IEEE80211_24GHZ_BAND (1<<0)
#define IEEE80211_52GHZ_BAND (1<<1)
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_CCK_RATE_1MB 0x02
#define IEEE80211_CCK_RATE_2MB 0x04
#define IEEE80211_CCK_RATE_5MB 0x0B
#define IEEE80211_CCK_RATE_11MB 0x16
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_6MB 0x0C
#define IEEE80211_OFDM_RATE_9MB 0x12
#define IEEE80211_OFDM_RATE_12MB 0x18
......@@ -919,10 +919,10 @@ struct ieee80211_rx_stats {
u16 fraglength; // FragLength should equal to PacketLength in non-fragment case
u16 fragoffset; // Data offset for this fragment
u16 ntotalfrag;
bool bisrxaggrsubframe;
bool bisrxaggrsubframe;
bool bPacketBeacon; //cosa add for rssi
bool bToSelfBA; //cosa add for rssi
char cck_adc_pwdb[4]; //cosa add for rx path selection
char cck_adc_pwdb[4]; //cosa add for rx path selection
u16 Seq_Num;
};
......@@ -992,7 +992,7 @@ struct ieee80211_device;
#define SEC_ALG_TKIP 2
#define SEC_ALG_CCMP 3
#define WEP_KEYS 4
#define WEP_KEYS 4
#define WEP_KEY_LEN 13
#define SCM_KEY_LEN 32
#define SCM_TEMPORAL_KEY_LENGTH 16
......@@ -1205,7 +1205,7 @@ struct ieee80211_drv_agg_txb {
struct sk_buff *tx_agg_frames[MAX_TX_AGG_COUNT];
}__attribute__((packed));
#define MAX_SUBFRAME_COUNT 64
#define MAX_SUBFRAME_COUNT 64
struct ieee80211_rxb {
u8 nr_subframes;
struct sk_buff *subframes[MAX_SUBFRAME_COUNT];
......@@ -1534,7 +1534,7 @@ struct ieee80211_network {
bool bWithAironetIE;
bool bCkipSupported;
bool bCcxRmEnable;
u16 CcxRmState[2];
u16 CcxRmState[2];
// CCXv4 S59, MBSSID.
bool bMBssidValid;
u8 MBssidMask;
......@@ -1726,7 +1726,7 @@ typedef struct _RT_POWER_SAVE_CONTROL
bool bIPSModeBackup;
bool bSwRfProcessing;
RT_RF_POWER_STATE eInactivePowerState;
struct work_struct InactivePsWorkItem;
struct work_struct InactivePsWorkItem;
struct timer_list InactivePsTimer;
// Return point for join action
......@@ -1837,11 +1837,11 @@ struct ieee80211_device {
u8 HTHighestOperaRate;
//wb added for rate operation mode to firmware
u8 bTxDisableRateFallBack;
u8 bTxUseDriverAssingedRate;
u8 bTxUseDriverAssingedRate;
atomic_t atm_chnlop;
atomic_t atm_swbw;
// u8 HTHighestOperaRate;
// u8 HTCurrentOperaRate;
// u8 HTCurrentOperaRate;
// 802.11e and WMM Traffic Stream Info (TX)
struct list_head Tx_TS_Admit_List;
......@@ -2055,9 +2055,9 @@ struct ieee80211_device {
bool bdynamic_txpower_enable;
bool bCTSToSelfEnable;
u8 CTSToSelfTH;
u8 CTSToSelfTH;
u32 fsync_time_interval;
u32 fsync_time_interval;
u32 fsync_rate_bitmap;
u8 fsync_rssi_threshold;
bool bfsync_enable;
......@@ -2214,7 +2214,7 @@ struct ieee80211_device {
#define IEEE_A (1<<0)
#define IEEE_B (1<<1)
#define IEEE_G (1<<2)
#define IEEE_N_24G (1<<4)
#define IEEE_N_24G (1<<4)
#define IEEE_N_5G (1<<5)
#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G)
......
......@@ -233,9 +233,9 @@ static int debug = \
// IEEE80211_DL_TX |
// IEEE80211_DL_RX |
//IEEE80211_DL_QOS |
// IEEE80211_DL_HT |
// IEEE80211_DL_HT |
// IEEE80211_DL_TS |
// IEEE80211_DL_BA |
// IEEE80211_DL_BA |
// IEEE80211_DL_REORDER|
// IEEE80211_DL_TRACE |
//IEEE80211_DL_DATA |
......
......@@ -608,7 +608,7 @@ void RxReorderIndicatePacket( struct ieee80211_device *ieee,
u16 SeqNum)
{
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
PRX_REORDER_ENTRY pReorderEntry = NULL;
PRX_REORDER_ENTRY pReorderEntry = NULL;
struct ieee80211_rxb* prxbIndicateArray[REORDER_WIN_SIZE];
u8 WinSize = pHTInfo->RxReorderWinSize;
u16 WinEnd = (pTS->RxIndicateSeq + WinSize -1)%4096;
......@@ -1043,7 +1043,7 @@ int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
{
// IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): pRxTS->RxLastFragNum is %d,frag is %d,pRxTS->RxLastSeqNum is %d,seq is %d\n",__FUNCTION__,pRxTS->RxLastFragNum,frag,pRxTS->RxLastSeqNum,WLAN_GET_SEQ_SEQ(sc));
if( (fc & (1<<11)) &&
if( (fc & (1<<11)) &&
(frag == pRxTS->RxLastFragNum) &&
(WLAN_GET_SEQ_SEQ(sc) == pRxTS->RxLastSeqNum) )
{
......@@ -1839,12 +1839,12 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee,
info_element->data[3] == 0x033){
tmp_htcap_len = min(info_element->len,(u8)MAX_IE_LEN);
if(tmp_htcap_len != 0){
network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC;
if(tmp_htcap_len != 0){
network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC;
network->bssht.bdHTCapLen = tmp_htcap_len > sizeof(network->bssht.bdHTCapBuf)?\
sizeof(network->bssht.bdHTCapBuf):tmp_htcap_len;
memcpy(network->bssht.bdHTCapBuf,info_element->data,network->bssht.bdHTCapLen);
}
}
}
if(tmp_htcap_len != 0)
network->bssht.bdSupportHT = true;
......@@ -1856,9 +1856,9 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee,
if(tmp_htinfo_len == 0){
if(info_element->len >= 4 &&
info_element->data[0] == 0x00 &&
info_element->data[1] == 0x90 &&
info_element->data[2] == 0x4c &&
info_element->data[3] == 0x034){
info_element->data[1] == 0x90 &&
info_element->data[2] == 0x4c &&
info_element->data[3] == 0x034){
tmp_htinfo_len = min(info_element->len,(u8)MAX_IE_LEN);
if(tmp_htinfo_len != 0){
......@@ -2060,7 +2060,7 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee,
if( (info_element->data[IE_CISCO_FLAG_POSITION]&SUPPORT_CKIP_MIC) ||
(info_element->data[IE_CISCO_FLAG_POSITION]&SUPPORT_CKIP_PK) )
{
network->bCkipSupported = true;
network->bCkipSupported = true;
}
else
{
......@@ -2070,7 +2070,7 @@ int ieee80211_parse_info_param(struct ieee80211_device *ieee,
else
{
network->bWithAironetIE = false;
network->bCkipSupported = false;
network->bCkipSupported = false;
}
break;
case MFIE_TYPE_QOS_PARAMETER:
......@@ -2230,8 +2230,8 @@ static inline int ieee80211_network_init(
} else
network->flags |= NETWORK_HAS_CCK;
network->wpa_ie_len = 0;
network->rsn_ie_len = 0;
network->wpa_ie_len = 0;
network->rsn_ie_len = 0;
if (ieee80211_parse_info_param
(ieee,beacon->info_element, stats->len - sizeof(*beacon), network, stats))
......
......@@ -3124,7 +3124,7 @@ inline struct sk_buff *ieee80211_disassociate_skb(
void
SendDisassociation(
struct ieee80211_device *ieee,
u8* asSta,
u8* asSta,
u8 asRsn
)
{
......
......@@ -395,7 +395,7 @@ ieee80211_query_HTCapShortGI(struct ieee80211_device *ieee, cb_desc *tcb_desc)
{
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
tcb_desc->bUseShortGI = false;
tcb_desc->bUseShortGI = false;
if(!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT)
return;
......@@ -514,7 +514,7 @@ void ieee80211_query_protectionmode(struct ieee80211_device* ieee, cb_desc* tcb_
if(pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF)
{
tcb_desc->bCTSEnable = true;
tcb_desc->rts_rate = MGN_24M;
tcb_desc->rts_rate = MGN_24M;
tcb_desc->bRTSEnable = true;
break;
}
......@@ -527,7 +527,7 @@ void ieee80211_query_protectionmode(struct ieee80211_device* ieee, cb_desc* tcb_
{
tcb_desc->bCTSEnable = true;
tcb_desc->rts_rate = MGN_24M;
tcb_desc->bRTSEnable = true;
tcb_desc->bRTSEnable = true;
}
if (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
tcb_desc->bUseShortPreamble = true;
......@@ -833,7 +833,7 @@ int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev)
else
ieee->seq_ctrl[UP2AC(skb->priority) + 1]++;
} else {
if (ieee->seq_ctrl[0] == 0xFFF)
if (ieee->seq_ctrl[0] == 0xFFF)
ieee->seq_ctrl[0] = 0;
else
ieee->seq_ctrl[0]++;
......
......@@ -79,4 +79,3 @@ void crypto_exit_cipher_ops(struct crypto_tfm *tfm);
void crypto_exit_compress_ops(struct crypto_tfm *tfm);
#endif /* _CRYPTO_INTERNAL_H */
#ifndef _BATYPE_H_
#define _BATYPE_H_
#define TOTAL_TXBA_NUM 16
#define TOTAL_TXBA_NUM 16
#define TOTAL_RXBA_NUM 16
#define BA_SETUP_TIMEOUT 200
......@@ -66,4 +66,3 @@ typedef struct _BA_RECORD {
} BA_RECORD, *PBA_RECORD;
#endif //end _BATYPE_H_
......@@ -121,7 +121,7 @@ typedef union _HT_CAPABILITY_MACPARA{
typedef enum _HT_ACTION{
ACT_RECOMMAND_WIDTH = 0,
ACT_MIMO_PWR_SAVE = 1,
ACT_MIMO_PWR_SAVE = 1,
ACT_PSMP = 2,
ACT_SET_PCO_PHASE = 3,
ACT_MIMO_CHL_MEASURE = 4,
......@@ -398,9 +398,9 @@ typedef struct _BSS_HT{
typedef struct _MIMO_RSSI{
u32 EnableAntenna;
u32 AntennaA;
u32 AntennaB;
u32 AntennaC;
u32 AntennaD;
u32 AntennaB;
u32 AntennaC;
u32 AntennaD;
u32 Average;
}MIMO_RSSI, *PMIMO_RSSI;
......@@ -436,11 +436,11 @@ extern u8 MCS_FILTER_1SS[16];
// MCS Bw 40 {1~7, 12~15,32}
#define RATE_ADPT_1SS_MASK 0xFF
#define RATE_ADPT_1SS_MASK 0xFF
#define RATE_ADPT_2SS_MASK 0xF0 //Skip MCS8~11 because mcs7 > mcs6, 9, 10, 11. 2007.01.16 by Emily
#define RATE_ADPT_MCS32_MASK 0x01
#define IS_11N_MCS_RATE(rate) (rate&0x80)
#define IS_11N_MCS_RATE(rate) (rate&0x80)
typedef enum _HT_AGGRE_SIZE{
HT_AGG_SIZE_8K = 0,
......@@ -478,4 +478,3 @@ typedef enum _HT_IOT_ACTION{
}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
#endif //_RTL819XU_HTTYPE_H_
......@@ -412,14 +412,14 @@ typedef union _QOS_TCLAS{
struct _TYPE_GENERAL{
u8 Priority;
u8 ClassifierType;
u8 Mask;
u8 ClassifierType;
u8 Mask;
} TYPE_GENERAL;
struct _TYPE0_ETH{
u8 Priority;
u8 ClassifierType;
u8 Mask;
u8 ClassifierType;
u8 Mask;
u8 SrcAddr[6];
u8 DstAddr[6];
u16 Type;
......@@ -427,9 +427,9 @@ typedef union _QOS_TCLAS{
struct _TYPE1_IPV4{
u8 Priority;
u8 ClassifierType;
u8 Mask;
u8 Version;
u8 ClassifierType;
u8 Mask;
u8 Version;
u8 SrcIP[4];
u8 DstIP[4];
u16 SrcPort;
......@@ -441,9 +441,9 @@ typedef union _QOS_TCLAS{
struct _TYPE1_IPV6{
u8 Priority;
u8 ClassifierType;
u8 Mask;
u8 Version;
u8 ClassifierType;
u8 Mask;
u8 Version;
u8 SrcIP[16];
u8 DstIP[16];
u16 SrcPort;
......@@ -453,8 +453,8 @@ typedef union _QOS_TCLAS{
struct _TYPE2_8021Q{
u8 Priority;
u8 ClassifierType;
u8 Mask;
u8 ClassifierType;
u8 Mask;
u16 TagType;
} TYPE2_8021Q;
} QOS_TCLAS, *PQOS_TCLAS;
......@@ -481,7 +481,7 @@ typedef struct _QOS_TSTREAM{
// "Qos control field" and "Qos info field"
//typedef struct _QOS_UAPSD{
// u8 bTriggerEnable[4];
// u8 MaxSPLength;
// u8 MaxSPLength;
// u8 HighestBufAC;
//} QOS_UAPSD, *PQOS_APSD;
......@@ -489,7 +489,7 @@ typedef struct _QOS_TSTREAM{
// 802.11 Management frame Status Code field
//----------------------------------------------------------------------------
typedef struct _OCTET_STRING{
u8 *Octet;
u8 *Octet;
u16 Length;
}OCTET_STRING, *POCTET_STRING;
......@@ -512,7 +512,7 @@ typedef struct _STA_QOS{
AC_UAPSD Curr4acUapsd;
u8 bInServicePeriod;
u8 MaxSPLength;
int NumBcnBeforeTrigger;
int NumBcnBeforeTrigger;
// Part 2. EDCA Parameter (perAC)
u8 * pWMMInfoEle;
......@@ -523,7 +523,7 @@ typedef struct _STA_QOS{
//2 ToDo: remove the Qos Info Field and replace it by the above WMM Info element.
// By Bruce, 2008-01-30.
// Part 2. EDCA Parameter (perAC)
QOS_INFO_FIELD QosInfoField_STA; // Maintained by STA
QOS_INFO_FIELD QosInfoField_STA; // Maintained by STA
QOS_INFO_FIELD QosInfoField_AP; // Retrieved from AP
AC_PARAM CurAcParameters[4];
......
......@@ -28,7 +28,7 @@ typedef struct _TS_COMMON_INFO{
typedef struct _TX_TS_RECORD{
TS_COMMON_INFO TsCommonInfo;
u16 TxCurSeq;
BA_RECORD TxPendingBARecord; // For BA Originator
BA_RECORD TxPendingBARecord; // For BA Originator
BA_RECORD TxAdmittedBARecord; // For BA Originator
// QOS_DL_RECORD DLRecord;
u8 bAddBaReqInProgress;
......@@ -53,4 +53,3 @@ typedef struct _RX_TS_RECORD {
#endif
......@@ -27,7 +27,7 @@ void RxPktPendingTimeout(unsigned long data)
PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)data;
struct ieee80211_device *ieee = container_of(pRxTs, struct ieee80211_device, RxTsRecord[pRxTs->num]);
PRX_REORDER_ENTRY pReorderEntry = NULL;
PRX_REORDER_ENTRY pReorderEntry = NULL;
//u32 flags = 0;
unsigned long flags = 0;
......@@ -236,8 +236,8 @@ void AdmitTS(struct ieee80211_device *ieee, PTS_COMMON_INFO pTsCommonInfo, u32 I
PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8 TID, TR_SELECT TxRxSelect)
{
//DIRECTION_VALUE dir;
u8 dir;
//DIRECTION_VALUE dir;
u8 dir;
bool search_dir[4] = {0, 0, 0, 0};
struct list_head* psearch_list; //FIXME
PTS_COMMON_INFO pRet = NULL;
......@@ -250,14 +250,14 @@ PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8
}
else
{
search_dir[DIR_UP] = true;
search_dir[DIR_UP] = true;
search_dir[DIR_BI_DIR]= true;
}
}
else if(ieee->iw_mode == IW_MODE_ADHOC)
{
if(TxRxSelect == TX_DIR)
search_dir[DIR_UP] = true;
search_dir[DIR_UP] = true;
else
search_dir[DIR_DOWN] = true;
}
......@@ -265,7 +265,7 @@ PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8
{
if(TxRxSelect == TX_DIR)
{
search_dir[DIR_UP] = true;
search_dir[DIR_UP] = true;
search_dir[DIR_BI_DIR]= true;
search_dir[DIR_DIRECT]= true;
}
......@@ -450,8 +450,8 @@ bool GetTs(
pTSInfo->field.ucTSID = UP; // TSID
pTSInfo->field.ucDirection = Dir; // Direction: if there is DirectLink, this need additional consideration.
pTSInfo->field.ucAccessPolicy = 1; // Access policy
pTSInfo->field.ucAggregation = 0; // Aggregation
pTSInfo->field.ucPSB = 0; // Aggregation
pTSInfo->field.ucAggregation = 0; // Aggregation
pTSInfo->field.ucPSB = 0; // Aggregation
pTSInfo->field.ucUP = UP; // User priority
pTSInfo->field.ucTSInfoAckPolicy = 0; // Ack policy
pTSInfo->field.ucSchedule = 0; // Schedule
......@@ -488,7 +488,7 @@ void RemoveTsEntry(
{
//#ifdef TO_DO_LIST
PRX_REORDER_ENTRY pRxReorderEntry;
PRX_TS_RECORD pRxTS = (PRX_TS_RECORD)pTs;
PRX_TS_RECORD pRxTS = (PRX_TS_RECORD)pTs;
if(timer_pending(&pRxTS->RxPktPendingTimer))
del_timer_sync(&pRxTS->RxPktPendingTimer);
......
......@@ -52,10 +52,10 @@
#define CRYPTO_TFM_REQ_WEAK_KEY 0x00000100
#define CRYPTO_TFM_RES_WEAK_KEY 0x00100000
#define CRYPTO_TFM_RES_BAD_KEY_LEN 0x00200000
#define CRYPTO_TFM_RES_BAD_KEY_SCHED 0x00400000
#define CRYPTO_TFM_RES_BAD_BLOCK_LEN 0x00800000
#define CRYPTO_TFM_RES_BAD_FLAGS 0x01000000
#define CRYPTO_TFM_RES_BAD_KEY_LEN 0x00200000
#define CRYPTO_TFM_RES_BAD_KEY_SCHED 0x00400000
#define CRYPTO_TFM_RES_BAD_BLOCK_LEN 0x00800000
#define CRYPTO_TFM_RES_BAD_FLAGS 0x01000000
/*
* Miscellaneous stuff.
......@@ -396,4 +396,3 @@ void crypto_hmac(struct crypto_tfm *tfm, u8 *key, unsigned int *keylen,
#endif /* CONFIG_CRYPTO_HMAC */
#endif /* _LINUX_CRYPTO_H */
......@@ -16,9 +16,9 @@
#include "r8190_rtl8256.h"
/*--------------------------------------------------------------------------
* Overview: set RF band width (20M or 40M)
* Overview: set RF band width (20M or 40M)
* Input: struct net_device* dev
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
* Output: NONE
* Return: NONE
* Note: 8226 support both 20M and 40 MHz
......@@ -106,16 +106,16 @@ void PHY_RF8256_Config(struct net_device* dev)
*---------------------------------------------------------------------------*/
void phy_RF8256_Config_ParaFile(struct net_device* dev)
{
u32 u4RegValue = 0;
u32 u4RegValue = 0;
//static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A;
//static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B;
//static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C;
//static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D;
u8 eRFPath;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
struct r8192_priv *priv = ieee80211_priv(dev);
u32 RegOffSetToBeCheck = 0x3;
u32 RegValueToBeCheck = 0x7f1;
u32 RegValueToBeCheck = 0x7f1;
u32 RF3_Final_Value = 0;
u8 ConstRetryTimes = 5, RetryTimes = 5;
u8 ret = 0;
......@@ -152,7 +152,7 @@ void phy_RF8256_Config_ParaFile(struct net_device* dev)
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
/* Set bit number of Address and Data for RF register */
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
......@@ -309,4 +309,3 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
return;
}
......@@ -110,7 +110,7 @@ do { if(rt_global_debug_component & component) \
#define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
#define COMP_RM BIT13 // For Radio Measurement.
#define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
#define COMP_PHY BIT15
#define COMP_PHY BIT15
#define COMP_CH BIT16 //channel setting debug
#define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
#define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
......@@ -209,7 +209,7 @@ do { if(rt_global_debug_component & component) \
#define IEEE80211_WATCH_DOG_TIME 2000
#define PHY_Beacon_RSSI_SLID_WIN_MAX 10
//for txpowertracking by amy
#define OFDM_Table_Length 19
#define OFDM_Table_Length 19
#define CCK_Table_length 12
/* for rtl819x */
......@@ -298,7 +298,7 @@ typedef struct _tx_desc_cmd_819x_usb {
u8 Reserved4;
//DOWRD 2
u16 TxBufferSize;
u16 TxBufferSize;
u16 Reserved5;
//DWORD 3,4,5
......@@ -391,7 +391,7 @@ typedef struct _rx_desc_819x_usb_aggr_subframe{
//DWORD 2
//u4Byte Reserved3;
//DWORD 3
//u4Byte BufferAddress;
//u4Byte BufferAddress;
}rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
#endif
......@@ -424,7 +424,7 @@ typedef struct rx_drvinfo_819x_usb{
#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
#define ENCRYPTION_MAX_OVERHEAD 128
#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
#define MAX_FRAGMENT_COUNT 8
#ifdef RTL8192U
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
......@@ -433,7 +433,7 @@ typedef struct rx_drvinfo_819x_usb{
#define MAX_TRANSMIT_BUFFER_SIZE 8000
#endif
#else
#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
#endif
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
#define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
......@@ -711,7 +711,7 @@ typedef struct Stats
//+by amy 080507
typedef struct ChnlAccessSetting {
typedef struct ChnlAccessSetting {
u16 SIFS_Timer;
u16 DIFS_Timer;
u16 SlotTimeTimer;
......@@ -721,23 +721,23 @@ typedef struct ChnlAccessSetting {
}*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef enum _RT_RF_TYPE_819xU{
......@@ -1006,7 +1006,7 @@ typedef struct r8192_priv
u8 retry_rts;
u16 rts;
struct ChnlAccessSetting ChannelAccessSetting;
struct ChnlAccessSetting ChannelAccessSetting;
struct work_struct reset_wq;
/**********************************************************/
......@@ -1014,7 +1014,7 @@ typedef struct r8192_priv
u16 basic_rate;
u8 short_preamble;
u8 slot_time;
bool bDcut;
bool bDcut;
bool bCurrentRxAggrEnable;
u8 Rf_Mode; //add for Firmware RF -R/W switch
prt_firmware pFirmware;
......@@ -1050,7 +1050,7 @@ typedef struct r8192_priv
//for set channel
u8 SwChnlInProgress;
u8 SwChnlStage;
u8 SwChnlStage;
u8 SwChnlStep;
u8 SetBWModeInProgress;
HT_CHANNEL_WIDTH CurrentChannelBW;
......@@ -1062,8 +1062,8 @@ typedef struct r8192_priv
// We save RF reg0 in this variable to reduce RF reading.
//
u32 RfReg0Value[4];
u8 NumTotalRFPath;
bool brfpath_rxenable[4];
u8 NumTotalRFPath;
bool brfpath_rxenable[4];
//RF set related
bool SetRFPowerStateInProgress;
//+by amy 080507
......@@ -1104,7 +1104,7 @@ typedef struct r8192_priv
bool btxpower_tracking;
bool bcck_in_ch14;
bool btxpowerdata_readfromEEPORM;
u16 TSSI_13dBm;
u16 TSSI_13dBm;
//For Backup Initial Gain
init_gain initgain_backup;
u8 DefaultInitialGain[4];
......@@ -1114,17 +1114,17 @@ typedef struct r8192_priv
bool bis_cur_rdlstate;
struct timer_list fsync_timer;
bool bfsync_processing; // 500ms Fsync timer is active or not
u32 rate_record;
u32 rateCountDiffRecord;
u32 rate_record;
u32 rateCountDiffRecord;
u32 ContinueDiffCount;
bool bswitch_fsync;
u8 framesync;
u32 framesyncC34;
u8 framesyncMonitor;
//Added by amy 080516 for RX related
u16 nrxAMPDU_size;
u8 nrxAMPDU_aggr_num;
u32 framesyncC34;
u8 framesyncMonitor;
//Added by amy 080516 for RX related
u16 nrxAMPDU_size;
u8 nrxAMPDU_aggr_num;
//by amy for gpio
bool bHwRadioOff;
......@@ -1204,7 +1204,7 @@ typedef enum{
#ifdef JOHN_HWSEC
struct ssid_thread {
struct net_device *dev;
u8 name[IW_ESSID_MAX_SIZE + 1];
u8 name[IW_ESSID_MAX_SIZE + 1];
};
#endif
......
......@@ -80,9 +80,9 @@ double __extendsfdf2(float a) {return a;}
#include "dot11d.h"
//set here to open your trace code. //WB
u32 rt_global_debug_component = \
// COMP_INIT |
// COMP_INIT |
// COMP_DBG |
// COMP_EPROM |
// COMP_EPROM |
// COMP_PHY |
// COMP_RF |
// COMP_FIRMWARE |
......@@ -159,7 +159,7 @@ static struct usb_driver rtl8192_usb_driver = {
.resume = rtl8192_resume, /* PM resume fn */
#else
.suspend = NULL, /* PM suspend fn */
.resume = NULL, /* PM resume fn */
.resume = NULL, /* PM resume fn */
#endif
};
......@@ -171,11 +171,11 @@ typedef struct _CHANNEL_LIST
}CHANNEL_LIST, *PCHANNEL_LIST;
static CHANNEL_LIST ChannelPlan[] = {
{{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC
{{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
{{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
{{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC
{{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
{{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
{{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Spain. Change to ETSI.
{{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI.
{{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI.
{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, //MKK //MKK
{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22},//MKK1
{{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Israel.
......@@ -240,7 +240,7 @@ static void rtl819x_set_channel_map(u8 channel_plan, struct r8192_priv* priv)
}
#define rx_hal_is_cck_rate(_pdrvinfo)\
#define rx_hal_is_cck_rate(_pdrvinfo)\
(_pdrvinfo->RxRate == DESC90_RATE1M ||\
_pdrvinfo->RxRate == DESC90_RATE2M ||\
_pdrvinfo->RxRate == DESC90_RATE5_5M ||\
......@@ -1272,8 +1272,8 @@ struct sk_buff *DrvAggr_Aggregation(struct net_device *dev, struct ieee80211_drv
{
struct ieee80211_device *ieee = netdev_priv(dev);
struct r8192_priv *priv = ieee80211_priv(dev);
cb_desc *tcb_desc = NULL;
u8 i;
cb_desc *tcb_desc = NULL;
u8 i;
u32 TotalLength;
struct sk_buff *skb;
struct sk_buff *agg_skb;
......@@ -1444,7 +1444,7 @@ u8 DrvAggr_GetAggregatibleList(struct net_device *dev, struct sk_buff *skb,
struct ieee80211_device *ieee = netdev_priv(dev);
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
u16 nMaxAggrNum = pHTInfo->UsbTxAggrNum;
cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
u8 QueueID = tcb_desc->queue_index;
do {
......@@ -1812,7 +1812,7 @@ short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb)
int status;
struct urb *tx_urb;
//int urb_buf_len;
unsigned int idx_pipe;
unsigned int idx_pipe;
tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data;
cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE);
u8 queue_index = tcb_desc->queue_index;
......@@ -2346,7 +2346,7 @@ void rtl8192_update_beacon(struct work_struct * work)
{
struct r8192_priv *priv = container_of(work, struct r8192_priv, update_beacon_wq.work);
struct net_device *dev = priv->ieee80211->dev;
struct ieee80211_device* ieee = priv->ieee80211;
struct ieee80211_device* ieee = priv->ieee80211;
struct ieee80211_network* net = &ieee->current_network;
if (ieee->pHTInfo->bCurrentHTSupport)
......@@ -2717,7 +2717,7 @@ static void rtl8192_init_priv_variable(struct net_device* dev)
priv->bDisableNormalResetCheck = false;
priv->force_reset = false;
priv->ieee80211->FwRWRF = 0; //we don't use FW read/write RF until stable firmware is available.
priv->ieee80211->FwRWRF = 0; //we don't use FW read/write RF until stable firmware is available.
priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
priv->ieee80211->iw_mode = IW_MODE_INFRA;
priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
......@@ -2778,11 +2778,11 @@ static void rtl8192_init_priv_variable(struct net_device* dev)
#ifdef TO_DO_LIST
if(Adapter->bInHctTest)
pHalData->ReceiveConfig = pHalData->CSMethod |
RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data
//guangan200710
RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
(pHalData->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold.
(pHalData->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0);
......@@ -2793,7 +2793,7 @@ static void rtl8192_init_priv_variable(struct net_device* dev)
RCR_AMF | RCR_ADF | //accept management/data
RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC
//RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
//RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet
((u32)7<<RCR_MXDMA_OFFSET)| // Max DMA Burst Size per Rx DMA Burst, 7: unlimited.
(priv->EarlyRxThreshold<<RX_FIFO_THRESHOLD_SHIFT) | // Rx FIFO Threshold, 7: No Rx threshold.
(priv->EarlyRxThreshold == 7 ? RCR_ONLYERLPKT:0);
......@@ -3549,7 +3549,7 @@ HalTxCheckStuck819xUsb(
)
{
struct r8192_priv *priv = ieee80211_priv(dev);
u16 RegTxCounter = read_nic_word(dev, 0x128);
u16 RegTxCounter = read_nic_word(dev, 0x128);
bool bStuck = FALSE;
RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter);
if(priv->TxCounter==RegTxCounter)
......@@ -3583,14 +3583,14 @@ TxCheckStuck(struct net_device *dev)
// spin_lock_irqsave(&priv->ieee80211->lock,flags);
for (QueueID = 0; QueueID<=BEACON_QUEUE;QueueID ++)
{
if(QueueID == TXCMD_QUEUE)
if(QueueID == TXCMD_QUEUE)
continue;
#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_drv_aggQ[QueueID]) == 0))
#else
if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0))
if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0))
#endif
continue;
continue;
bCheckFwTxCnt = true;
}
......@@ -3611,7 +3611,7 @@ TxCheckStuck(struct net_device *dev)
bool
HalRxCheckStuck819xUsb(struct net_device *dev)
{
u16 RegRxCounter = read_nic_word(dev, 0x130);
u16 RegRxCounter = read_nic_word(dev, 0x130);
struct r8192_priv *priv = ieee80211_priv(dev);
bool bStuck = FALSE;
static u8 rx_chk_cnt = 0;
......@@ -3718,7 +3718,7 @@ rtl819x_ifcheck_resetornot(struct net_device *dev)
struct r8192_priv *priv = ieee80211_priv(dev);
RESET_TYPE TxResetType = RESET_TYPE_NORESET;
RESET_TYPE RxResetType = RESET_TYPE_NORESET;
RT_RF_POWER_STATE rfState;
RT_RF_POWER_STATE rfState;
rfState = priv->ieee80211->eRFPowerState;
......@@ -4006,18 +4006,18 @@ rtl819x_ifsilentreset(struct net_device *dev)
void CAM_read_entry(
struct net_device *dev,
u32 iIndex
u32 iIndex
)
{
u32 target_command=0;
u32 target_command=0;
u32 target_content=0;
u8 entry_i=0;
u32 ulStatus;
s32 i=100;
// printk("=======>start read CAM\n");
for(entry_i=0;entry_i<CAM_CONTENT_COUNT;entry_i++)
{
// polling bit, and No Write enable, and address
for(entry_i=0;entry_i<CAM_CONTENT_COUNT;entry_i++)
{
// polling bit, and No Write enable, and address
target_command= entry_i+CAM_CONTENT_COUNT*iIndex;
target_command= target_command | BIT31;
......@@ -4049,7 +4049,7 @@ void rtl819x_update_rxcounts(
u32* TotalRxDataNum
)
{
u16 SlotIndex;
u16 SlotIndex;
u8 i;
*TotalRxBcnNum = 0;
......@@ -4122,7 +4122,7 @@ extern void rtl819x_watchdog_wqcallback(struct work_struct *work)
//check if reset the driver
if(check_reset_cnt++ >= 3)
{
ResetType = rtl819x_ifcheck_resetornot(dev);
ResetType = rtl819x_ifcheck_resetornot(dev);
check_reset_cnt = 3;
//DbgPrint("Start to check silent reset\n");
}
......@@ -4418,10 +4418,10 @@ int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
setKey( dev,
ipw->u.crypt.idx,
ipw->u.crypt.idx, //KeyIndex
ieee->group_key_type, //KeyType
broadcast_addr, //MacAddr
ieee->group_key_type, //KeyType
broadcast_addr, //MacAddr
0, //DefaultKey
key); //KeyContent
key); //KeyContent
}
}
}
......@@ -4819,7 +4819,7 @@ rtl819x_evm_dbtopercentage(
}
//
// Description:
// We want good-looking for signal strength/quality
// We want good-looking for signal strength/quality
// 2007/7/19 01:09, by cosa.
//
long
......@@ -5203,7 +5203,7 @@ void TranslateRxSignalStuff819xUsb(struct sk_buff *skb,
* Overview: Record the received data rate
*
* Input:
* struct net_device *dev
* struct net_device *dev
* struct ieee80211_rx_stats *stats
*
* Output:
......@@ -5581,7 +5581,7 @@ rtl819xusb_process_received_packet(
)
{
// bool bfreerfd=false, bqueued=false;
u8* frame;
u8* frame;
u16 frame_len=0;
struct r8192_priv *priv = ieee80211_priv(dev);
// u8 index = 0;
......@@ -6007,7 +6007,7 @@ void setKey( struct net_device *dev,
// printk("setkey cam =%8x\n", read_cam(dev, i+6*EntryNo));
}
else if(i==1){//MAC
TargetContent = (u32)(*(MacAddr+2)) |
TargetContent = (u32)(*(MacAddr+2)) |
(u32)(*(MacAddr+3)) << 8|
(u32)(*(MacAddr+4)) << 16|
(u32)(*(MacAddr+5)) << 24;
......
This diff is collapsed.
......@@ -13,7 +13,7 @@
*
* History:
* Data Who Remark
* 10/04/2007 MHC Create initial version.
* 10/04/2007 MHC Create initial version.
*
*****************************************************************************/
/* Check to see if the file has been included already. */
......@@ -55,12 +55,12 @@
#define TX_POWER_NEAR_FIELD_THRESH_LOW 62
//added by amy for atheros AP
#define TX_POWER_ATHEROAP_THRESH_HIGH 78
#define TX_POWER_ATHEROAP_THRESH_LOW 72
#define TX_POWER_ATHEROAP_THRESH_LOW 72
//defined by vivi, for showing on UI
#define Current_Tx_Rate_Reg 0x1b8
#define Initial_Tx_Rate_Reg 0x1b9
#define Tx_Retry_Count_Reg 0x1ac
#define Current_Tx_Rate_Reg 0x1b8
#define Initial_Tx_Rate_Reg 0x1b9
#define Tx_Retry_Count_Reg 0x1ac
#define RegC38_TH 20
/*--------------------------Define Parameters-------------------------------*/
......@@ -132,8 +132,8 @@ typedef enum tag_dynamic_init_gain_operation_type_definition
DIG_TYPE_PWDB_FACTOR = 8,
DIG_TYPE_RX_GAIN_MIN = 9,
DIG_TYPE_RX_GAIN_MAX = 10,
DIG_TYPE_ENABLE = 20,
DIG_TYPE_DISABLE = 30,
DIG_TYPE_ENABLE = 20,
DIG_TYPE_DISABLE = 30,
DIG_OP_TYPE_MAX
}dm_dig_op_e;
......@@ -251,4 +251,3 @@ extern void dm_initialize_txpower_tracking(struct net_device *dev);
/* End of r8192U_dm.h */
......@@ -122,7 +122,7 @@ enum _RTL8192Usb_HW {
SIFS = 0x03E, // SIFS register
TCR = 0x040, // Transmit Configuration Register
#define TCR_MXDMA_2048 7
#define TCR_MXDMA_2048 7
#define TCR_LRL_OFFSET 0
#define TCR_SRL_OFFSET 8
#define TCR_MXDMA_OFFSET 21
......@@ -379,7 +379,7 @@ enum _RTL8192Usb_HW {
// IMR_POLL = 0x360,
MacBlkCtrl = 0x403, // Mac block on/off control register
EPROM_CMD = 0xfe58,
EPROM_CMD = 0xfe58,
#define Cmd9346CR_9356SEL (1<<4)
#define EPROM_CMD_RESERVED_MASK (1<<5)
#define EPROM_CMD_OPERATING_MODE_SHIFT 6
......@@ -392,12 +392,12 @@ enum _RTL8192Usb_HW {
#define EPROM_CK_SHIFT 2
#define EPROM_W_SHIFT 1
#define EPROM_R_SHIFT 0
MAC0 = 0x000,
MAC1 = 0x001,
MAC2 = 0x002,
MAC3 = 0x003,
MAC4 = 0x004,
MAC5 = 0x005,
MAC0 = 0x000,
MAC1 = 0x001,
MAC2 = 0x002,
MAC3 = 0x003,
MAC4 = 0x004,
MAC5 = 0x005,
};
//----------------------------------------------------------------------------
......
......@@ -1021,7 +1021,7 @@ static int dummy(struct net_device *dev, struct iw_request_info *a,
static iw_handler r8192_wx_handlers[] =
{
NULL, /* SIOCSIWCOMMIT */
r8192_wx_get_name, /* SIOCGIWNAME */
r8192_wx_get_name, /* SIOCGIWNAME */
dummy, /* SIOCSIWNWID */
dummy, /* SIOCGIWNWID */
r8192_wx_set_freq, /* SIOCSIWFREQ */
......@@ -1040,7 +1040,7 @@ static iw_handler r8192_wx_handlers[] =
dummy, /* SIOCGIWSPY */
NULL, /* SIOCGIWTHRSPY */
NULL, /* SIOCWIWTHRSPY */
r8192_wx_set_wap, /* SIOCSIWAP */
r8192_wx_set_wap, /* SIOCSIWAP */
r8192_wx_get_wap, /* SIOCGIWAP */
#if (WIRELESS_EXT >= 18)
r8192_wx_set_mlme, /* MLME-- */
......@@ -1071,23 +1071,23 @@ static iw_handler r8192_wx_handlers[] =
r8192_wx_set_power, /* SIOCSIWPOWER */
r8192_wx_get_power, /* SIOCGIWPOWER */
NULL, /*---hole---*/
NULL, /*---hole---*/
r8192_wx_set_gen_ie,//NULL, /* SIOCSIWGENIE */
NULL, /* SIOCSIWGENIE */
NULL, /*---hole---*/
r8192_wx_set_gen_ie,//NULL, /* SIOCSIWGENIE */
NULL, /* SIOCSIWGENIE */
#if (WIRELESS_EXT >= 18)
r8192_wx_set_auth,//NULL, /* SIOCSIWAUTH */
NULL,//r8192_wx_get_auth,//NULL, /* SIOCSIWAUTH */
r8192_wx_set_enc_ext, /* SIOCSIWENCODEEXT */
NULL,//r8192_wx_get_enc_ext,//NULL, /* SIOCSIWENCODEEXT */
r8192_wx_set_auth,//NULL, /* SIOCSIWAUTH */
NULL,//r8192_wx_get_auth,//NULL, /* SIOCSIWAUTH */
r8192_wx_set_enc_ext, /* SIOCSIWENCODEEXT */
NULL,//r8192_wx_get_enc_ext,//NULL, /* SIOCSIWENCODEEXT */
#else
NULL,
NULL,
NULL,
NULL,
#endif
NULL, /* SIOCSIWPMKSA */
NULL, /*---hole---*/
NULL, /* SIOCSIWPMKSA */
NULL, /*---hole---*/
};
......
......@@ -10,4 +10,3 @@ typedef enum _HT_IOT_ACTION{
HT_IOT_ACT_CDD_FSYNC = 0x00000020,
HT_IOT_ACT_PURE_N_MODE = 0x00000040,
}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
......@@ -89,7 +89,7 @@ typedef enum _CHNLOP{
typedef enum _HT_ACTION{
ACT_RECOMMAND_WIDTH = 0,
ACT_MIMO_PWR_SAVE = 1,
ACT_MIMO_PWR_SAVE = 1,
ACT_PSMP = 2,
ACT_SET_PCO_PHASE = 3,
ACT_MIMO_CHL_MEASURE = 4,
......@@ -367,9 +367,9 @@ typedef struct _BSS_HT{
typedef struct _MIMO_RSSI{
u32 EnableAntenna;
u32 AntennaA;
u32 AntennaB;
u32 AntennaC;
u32 AntennaD;
u32 AntennaB;
u32 AntennaC;
u32 AntennaD;
u32 Average;
}MIMO_RSSI, *PMIMO_RSSI;
......@@ -388,4 +388,3 @@ typedef struct _FALSE_ALARM_STATISTICS{
#endif //__INC_HTTYPE_H
......@@ -18,7 +18,7 @@
History:
Data Who Remark
05/06/2008 amy Create initial version porting from windows driver.
05/06/2008 amy Create initial version porting from windows driver.
******************************************************************************/
#include "r8192U.h"
......@@ -41,7 +41,7 @@
rt_status
SendTxCommandPacket(
struct net_device *dev,
void* pData,
void* pData,
u32 DataLen
)
{
......@@ -106,7 +106,7 @@ SendTxCommandPacket(
u32 buffer_len)
{
bool rt_status = true;
bool rt_status = true;
#ifdef RTL8192U
return rt_status;
#else
......@@ -188,7 +188,7 @@ SendTxCommandPacket(
*
* Overview:
*
* Input: PADAPTER pAdapter - .
* Input: PADAPTER pAdapter - .
* CMPK_TXFB_T *psTx_FB - .
*
* Output: NONE
......@@ -197,7 +197,7 @@ SendTxCommandPacket(
*
* Revised History:
* When Who Remark
* 05/12/2008 amy Create Version 0 porting from windows code.
* 05/12/2008 amy Create Version 0 porting from windows code.
*
*---------------------------------------------------------------------------*/
static void
......@@ -289,7 +289,7 @@ cmpk_count_txstatistic(
* in the command packet.
*
* Input: struct net_device * dev
* u8 * pmsg - Msg Ptr of the command packet.
* u8 * pmsg - Msg Ptr of the command packet.
*
* Output: NONE
*
......@@ -369,7 +369,7 @@ cmdpkt_beacontimerinterrupt_819xusb(
* Overview: The function is responsible for extract the message from
* firmware. It will contain dedicated info in
* ws-07-0063-v06-rtl819x-command-packet-specification-070315.doc.
* Please refer to chapter "Interrupt Status Element".
* Please refer to chapter "Interrupt Status Element".
*
* Input: struct net_device *dev,
* u8* pmsg - Message Pointer of the command packet.
......@@ -400,8 +400,8 @@ cmpk_handle_interrupt_status(
/* It seems that FW use big endian(MIPS) and DRV use little endian in
windows OS. So we have to read the content byte by byte or transfer
endian type before copy the message copy. */
//rx_bcn_state.Element_ID = pMsg[0];
//rx_bcn_state.Length = pMsg[1];
//rx_bcn_state.Element_ID = pMsg[0];
//rx_bcn_state.Length = pMsg[1];
rx_intr_status.length = pmsg[1];
if (rx_intr_status.length != (sizeof(cmpk_intr_sta_t) - 2))
{
......@@ -478,16 +478,16 @@ cmpk_handle_query_config_rx(
/* It seems that FW use big endian(MIPS) and DRV use little endian in
windows OS. So we have to read the content byte by byte or transfer
endian type before copy the message copy. */
//rx_query_cfg.Element_ID = pMsg[0];
//rx_query_cfg.Length = pMsg[1];
rx_query_cfg.cfg_action = (pmsg[4] & 0x80000000)>>31;
rx_query_cfg.cfg_type = (pmsg[4] & 0x60) >> 5;
rx_query_cfg.cfg_size = (pmsg[4] & 0x18) >> 3;
rx_query_cfg.cfg_page = (pmsg[6] & 0x0F) >> 0;
rx_query_cfg.cfg_offset = pmsg[7];
rx_query_cfg.value = (pmsg[8] << 24) | (pmsg[9] << 16) |
//rx_query_cfg.Element_ID = pMsg[0];
//rx_query_cfg.Length = pMsg[1];
rx_query_cfg.cfg_action = (pmsg[4] & 0x80000000)>>31;
rx_query_cfg.cfg_type = (pmsg[4] & 0x60) >> 5;
rx_query_cfg.cfg_size = (pmsg[4] & 0x18) >> 3;
rx_query_cfg.cfg_page = (pmsg[6] & 0x0F) >> 0;
rx_query_cfg.cfg_offset = pmsg[7];
rx_query_cfg.value = (pmsg[8] << 24) | (pmsg[9] << 16) |
(pmsg[10] << 8) | (pmsg[11] << 0);
rx_query_cfg.mask = (pmsg[12] << 24) | (pmsg[13] << 16) |
rx_query_cfg.mask = (pmsg[12] << 24) | (pmsg[13] << 16) |
(pmsg[14] << 8) | (pmsg[15] << 0);
} /* cmpk_Handle_Query_Config_Rx */
......@@ -511,7 +511,7 @@ cmpk_handle_query_config_rx(
*
*---------------------------------------------------------------------------*/
static void cmpk_count_tx_status( struct net_device *dev,
cmpk_tx_status_t *pstx_status)
cmpk_tx_status_t *pstx_status)
{
struct r8192_priv *priv = ieee80211_priv(dev);
......
......@@ -72,7 +72,7 @@ typedef struct tag_cmd_pkt_set_configuration
u8 element_id; /* Command packet type. */
u8 length; /* Command packet length. */
u16 reserve1; /* */
u8 cfg_reserve1:3;
u8 cfg_reserve1:3;
u8 cfg_size:2; /* Configuration info. */
u8 cfg_type:2; /* Configuration info. */
u8 cfg_action:1; /* Configuration info. */
......@@ -94,20 +94,20 @@ typedef struct tag_tx_stats_feedback // PJ quick rxcmd 09042007
// For endian transfer --> Driver will not the same as firmware structure.
// DW 0
u16 reserve1;
u8 length; // Command packet length
u8 element_id; // Command packet type
u8 length; // Command packet length
u8 element_id; // Command packet type
// DW 1
u16 txfail; // Tx Fail count
u16 txok; // Tx ok count
u16 txok; // Tx ok count
// DW 2
u16 txmcok; // tx multicast
u16 txretry; // Tx Retry count
u16 txmcok; // tx multicast
u16 txretry; // Tx Retry count
// DW 3
u16 txucok; // tx unicast
u16 txbcok; // tx broadcast
u16 txbcok; // tx broadcast
// DW 4
u16 txbcfail; //
......@@ -135,8 +135,8 @@ typedef struct tag_rx_debug_message_feedback
// For endian transfer --> for driver
// DW 0
u16 reserve1;
u8 length; // Command packet length
u8 element_id; // Command packet type
u8 length; // Command packet length
u8 element_id; // Command packet type
// DW 1-??
// Variable debug message.
......@@ -148,15 +148,15 @@ typedef struct tag_tx_rate_history
{
// For endian transfer --> for driver
// DW 0
u8 element_id; // Command packet type
u8 length; // Command packet length
u8 element_id; // Command packet type
u8 length; // Command packet length
u16 reserved1;
// DW 1-2 CCK rate counter
u16 cck[4];
u16 cck[4];
// DW 3-6
u16 ofdm[8];
u16 ofdm[8];
// DW 7-14
//UINT16 MCS_BW0_SG0[16];
......
......@@ -2,7 +2,7 @@
* Procedure: Init boot code/firmware code/data session
*
* Description: This routine will initialize firmware. If any error occurs during the initialization
* process, the routine shall terminate immediately and return fail.
* process, the routine shall terminate immediately and return fail.
* NIC driver should call NdisOpenFile only from MiniportInitialize.
*
* Arguments: The pointer of the adapter
......@@ -19,7 +19,7 @@
#include <linux/firmware.h>
void firmware_init_param(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
struct r8192_priv *priv = ieee80211_priv(dev);
rt_firmware *pfirmware = priv->pFirmware;
pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE);
......@@ -32,7 +32,7 @@ void firmware_init_param(struct net_device *dev)
bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len)
{
struct r8192_priv *priv = ieee80211_priv(dev);
bool rt_status = true;
bool rt_status = true;
u16 frag_threshold;
u16 frag_length, frag_offset = 0;
//u16 total_size;
......@@ -241,17 +241,17 @@ bool CPUcheck_firmware_ready(struct net_device *dev)
bool init_firmware(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
struct r8192_priv *priv = ieee80211_priv(dev);
bool rt_status = TRUE;
u32 file_length = 0;
u8 *mapped_file = NULL;
u32 init_step = 0;
opt_rst_type_e rst_opt = OPT_SYSTEM_RESET;
firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT;
firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT;
rt_firmware *pfirmware = priv->pFirmware;
const struct firmware *fw_entry;
const struct firmware *fw_entry;
const char *fw_name[3] = { "RTL8192U/boot.img",
"RTL8192U/main.img",
"RTL8192U/data.img"};
......@@ -402,4 +402,3 @@ bool init_firmware(struct net_device *dev)
MODULE_FIRMWARE("RTL8192U/boot.img");
MODULE_FIRMWARE("RTL8192U/main.img");
MODULE_FIRMWARE("RTL8192U/data.img");
......@@ -24,4 +24,3 @@ typedef enum _opt_rst_type{
}opt_rst_type_e;
#endif
......@@ -124,10 +124,10 @@ static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E
/******************************************************************************
*function: This function read register from RF chip
* input: net_device dev
* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
* u32 Offset //target address to be read
* output: none
* return: u32 readback value
* return: u32 readback value
* notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
* ****************************************************************************/
u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
......@@ -201,7 +201,7 @@ u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath,
/******************************************************************************
*function: This function write data to RF register
* input: net_device dev
* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
* u32 Offset //target address to be written
* u32 Data //The new register data to be written
* output: none
......@@ -283,7 +283,7 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath
/******************************************************************************
*function: This function set specific bits to RF register
* input: net_device dev
* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
* u32 RegAddr //target addr to be modified
* u32 BitMask //taget bit pos in the addr to be modified
* u32 Data //value to be write
......@@ -684,8 +684,8 @@ void rtl8192_InitBBRFRegDef(struct net_device* dev)
/******************************************************************************
*function: This function is to write register and then readback to make sure whether BB and RF is OK
* input: net_device dev
* HW90_BLOCK_E CheckBlock
* RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
* HW90_BLOCK_E CheckBlock
* RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
* output: none
* return: return whether BB and RF is ok(0:OK; 1:Fail)
* notice: This function may be removed in the ASIC
......@@ -1015,7 +1015,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E
/******************************************************************************
*function: This function set Tx Power of the channel
* input: struct net_device *dev
* u8 channel
* u8 channel
* output: none
* return: none
* Note:
......@@ -1052,7 +1052,7 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
/******************************************************************************
*function: This function set RF state on or off
* input: struct net_device *dev
* RT_RF_POWER_STATE eRFPowerState //Power State to set
* RT_RF_POWER_STATE eRFPowerState //Power State to set
* output: none
* return: none
* Note:
......@@ -1183,10 +1183,10 @@ bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerS
/****************************************************************************************
*function: This function set command table variable(struct SwChnlCmd).
* input: SwChnlCmd* CmdTable //table to be set.
* u32 CmdTableIdx //variable index in table to be set
* u32 CmdTableSz //table size.
* SwChnlCmdID CmdID //command ID to set.
* input: SwChnlCmd* CmdTable //table to be set.
* u32 CmdTableIdx //variable index in table to be set
* u32 CmdTableSz //table size.
* SwChnlCmdID CmdID //command ID to set.
* u32 Para1
* u32 Para2
* u32 msDelay
......@@ -1229,10 +1229,10 @@ u8 rtl8192_phy_SetSwChnlCmdArray(
/******************************************************************************
*function: This function set channel step by step
* input: struct net_device *dev
* u8 channel
* u8* stage //3 stages
* u8* step //
* u32* delay //whether need to delay
* u8 channel
* u8* stage //3 stages
* u8* step //
* u32* delay //whether need to delay
* output: store new stage, step and delay for next step(combine with function above)
* return: true if finished, false otherwise
* Note: Wait for simpler function to replace it //wb
......@@ -1386,7 +1386,7 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u
/******************************************************************************
*function: This function does actually set channel work
* input: struct net_device *dev
* u8 channel
* u8 channel
* output: none
* return: noin
* Note: We should not call this function directly
......@@ -1427,7 +1427,7 @@ void rtl8192_SwChnl_WorkItem(struct net_device *dev)
/******************************************************************************
*function: This function scheduled actual work item to set channel
* input: net_device dev
* u8 channel //channel to set
* u8 channel //channel to set
* output: none
* return: return code show if workitem is scheduled(1:pass, 0:fail)
* Note: Delay may be required for RF configuration
......@@ -1501,12 +1501,12 @@ if (0) //to test current channel from RF reg 0x7.
/******************************************************************************
*function: Callback routine of the work item for set bandwidth mode.
* input: struct net_device *dev
* HT_CHANNEL_WIDTH Bandwidth //20M or 40M
* HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
* HT_CHANNEL_WIDTH Bandwidth //20M or 40M
* HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
* output: none
* return: none
* Note: I doubt whether SetBWModeInProgress flag is necessary as we can
* test whether current work in the queue or not.//do I?
* test whether current work in the queue or not.//do I?
* ***************************************************************************/
void rtl8192_SetBWModeWorkItem(struct net_device *dev)
{
......@@ -1649,12 +1649,12 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
/******************************************************************************
*function: This function schedules bandwidth switch work.
* input: struct net_device *dev
* HT_CHANNEL_WIDTH Bandwidth //20M or 40M
* HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
* HT_CHANNEL_WIDTH Bandwidth //20M or 40M
* HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
* output: none
* return: none
* Note: I doubt whether SetBWModeInProgress flag is necessary as we can
* test whether current work in the queue or not.//do I?
* test whether current work in the queue or not.//do I?
* ***************************************************************************/
void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
{
......@@ -1770,4 +1770,3 @@ extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
break;
}
}
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