Commit 367571e4 authored by Ofer Heifetz's avatar Ofer Heifetz Committed by Herbert Xu

crypto: inside-secure - add multiple processing engine support

So far a single processing engine (PE) was configured and used in the
Inside Secure SafeXcel cryptographic engine driver. Some versions have
more than a single PE. This patch rework the driver's initialization to
take this into account and to allow configuring more than one PE.
Signed-off-by: default avatarOfer Heifetz <oferh@marvell.com>
[Antoine: some reworks and commit message.]
Signed-off-by: default avatarAntoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 18e0e95b
This diff is collapsed.
......@@ -95,13 +95,13 @@
#define EIP197_HIA_xDR_STAT 0x003c
/* register offsets */
#define EIP197_HIA_DFE_CFG 0x0000
#define EIP197_HIA_DFE_THR_CTRL 0x0000
#define EIP197_HIA_DFE_THR_STAT 0x0004
#define EIP197_HIA_DSE_CFG 0x0000
#define EIP197_HIA_DSE_THR_CTRL 0x0000
#define EIP197_HIA_DSE_THR_STAT 0x0004
#define EIP197_HIA_RA_PE_CTRL 0x0010
#define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
#define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
#define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
#define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
#define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
#define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
#define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
#define EIP197_HIA_RA_PE_STAT 0x0014
#define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
#define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
......@@ -114,18 +114,18 @@
#define EIP197_HIA_MST_CTRL 0xfff4
#define EIP197_HIA_OPTIONS 0xfff8
#define EIP197_HIA_VERSION 0xfffc
#define EIP197_PE_IN_DBUF_THRES 0x0000
#define EIP197_PE_IN_TBUF_THRES 0x0100
#define EIP197_PE_ICE_SCRATCH_RAM 0x0800
#define EIP197_PE_ICE_PUE_CTRL 0x0c80
#define EIP197_PE_ICE_SCRATCH_CTRL 0x0d04
#define EIP197_PE_ICE_FPP_CTRL 0x0d80
#define EIP197_PE_ICE_RAM_CTRL 0x0ff0
#define EIP197_PE_EIP96_FUNCTION_EN 0x1004
#define EIP197_PE_EIP96_CONTEXT_CTRL 0x1008
#define EIP197_PE_EIP96_CONTEXT_STAT 0x100c
#define EIP197_PE_OUT_DBUF_THRES 0x1c00
#define EIP197_PE_OUT_TBUF_THRES 0x1d00
#define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
#define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
#define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
#define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
#define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
#define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
#define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
#define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
#define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
#define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
#define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
#define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
#define EIP197_MST_CTRL 0xfff4
/* EIP197-specific registers, no indirection */
......@@ -184,6 +184,11 @@
#define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
#define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
/* EIP197_HIA_OPTIONS */
#define EIP197_N_PES_OFFSET 4
#define EIP197_N_PES_MASK GENMASK(4, 0)
#define EIP97_N_PES_MASK GENMASK(2, 0)
/* EIP197_HIA_AIC_R_ENABLE_CTRL */
#define EIP197_CDR_IRQ(n) BIT((n) * 2)
#define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
......@@ -513,6 +518,7 @@ struct safexcel_request {
};
struct safexcel_config {
u32 pes;
u32 rings;
u32 cd_size;
......
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