Commit 368400e2 authored by Christoffer Dall's avatar Christoffer Dall Committed by Sudeep Holla

ARM: dts: vexpress: Support GICC_DIR operations

The GICv2 CPU interface registers span across 8K, not 4K as indicated in
the DT.  Only the GICC_DIR register is located after the initial 4K
boundary, leaving a functional system but without support for separately
EOI'ing and deactivating interrupts.

After this change the system supports split priority drop and interrupt
deactivation.
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
[sudeep.holla@arm.com: included same fix for tc1 platform too]
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 7ce7d89f
...@@ -81,7 +81,7 @@ gic: interrupt-controller@2c001000 { ...@@ -81,7 +81,7 @@ gic: interrupt-controller@2c001000 {
#address-cells = <0>; #address-cells = <0>;
interrupt-controller; interrupt-controller;
reg = <0 0x2c001000 0 0x1000>, reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x1000>, <0 0x2c002000 0 0x2000>,
<0 0x2c004000 0 0x2000>, <0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>; <0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>; interrupts = <1 9 0xf04>;
......
...@@ -131,7 +131,7 @@ gic: interrupt-controller@2c001000 { ...@@ -131,7 +131,7 @@ gic: interrupt-controller@2c001000 {
#address-cells = <0>; #address-cells = <0>;
interrupt-controller; interrupt-controller;
reg = <0 0x2c001000 0 0x1000>, reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x1000>, <0 0x2c002000 0 0x2000>,
<0 0x2c004000 0 0x2000>, <0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>; <0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>; interrupts = <1 9 0xf04>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment