Commit 377cfdc6 authored by Dan Carpenter's avatar Dan Carpenter Committed by Ben Skeggs

drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800

We care about the upper 32 bits here so we have to use 1ULL instead of 1
to avoid a shift wrapping bug.
Signed-off-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 35c33670
...@@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) ...@@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
} while (!tpcnr[gpc]); } while (!tpcnr[gpc]);
tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
tpc_set |= 1 << ((gpc * 8) + tpc); tpc_set |= 1ULL << ((gpc * 8) + tpc);
} }
nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
......
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