Commit 3831abe1 authored by Miquel Raynal's avatar Miquel Raynal Committed by Lee Jones

mfd: ti_am335x_tscadc: Fix header spacing

Harmonize the spacing within macro definitions.
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211015081506.933180-25-miquel.raynal@bootlin.com
parent 36782dab
...@@ -41,7 +41,7 @@ ...@@ -41,7 +41,7 @@
/* Step Enable */ /* Step Enable */
#define STEPENB_MASK (0x1FFFF << 0) #define STEPENB_MASK (0x1FFFF << 0)
#define STEPENB(val) ((val) << 0) #define STEPENB(val) ((val) << 0)
#define ENB(val) (1 << (val)) #define ENB(val) (1 << (val))
#define STPENB_STEPENB STEPENB(0x1FFFF) #define STPENB_STEPENB STEPENB(0x1FFFF)
#define STPENB_STEPENB_TC STEPENB(0x1FFF) #define STPENB_STEPENB_TC STEPENB(0x1FFF)
...@@ -122,15 +122,15 @@ ...@@ -122,15 +122,15 @@
#define CNTRLREG_TSCENB BIT(7) #define CNTRLREG_TSCENB BIT(7)
/* FIFO READ Register */ /* FIFO READ Register */
#define FIFOREAD_DATA_MASK (0xfff << 0) #define FIFOREAD_DATA_MASK (0xfff << 0)
#define FIFOREAD_CHNLID_MASK (0xf << 16) #define FIFOREAD_CHNLID_MASK (0xf << 16)
/* DMA ENABLE/CLEAR Register */ /* DMA ENABLE/CLEAR Register */
#define DMA_FIFO0 BIT(0) #define DMA_FIFO0 BIT(0)
#define DMA_FIFO1 BIT(1) #define DMA_FIFO1 BIT(1)
/* Sequencer Status */ /* Sequencer Status */
#define SEQ_STATUS BIT(5) #define SEQ_STATUS BIT(5)
#define CHARGE_STEP 0x11 #define CHARGE_STEP 0x11
#define ADC_CLK 3000000 #define ADC_CLK 3000000
...@@ -150,7 +150,7 @@ ...@@ -150,7 +150,7 @@
* *
* max processing time: 266431 * 308ns = 83ms(approx) * max processing time: 266431 * 308ns = 83ms(approx)
*/ */
#define IDLE_TIMEOUT 83 /* milliseconds */ #define IDLE_TIMEOUT 83 /* milliseconds */
#define TSCADC_CELLS 2 #define TSCADC_CELLS 2
......
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