Commit 38beb96e authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-v4.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 - Driver fixes for Freescale i.MX7D, Intel, Broadcom 2835
 - One MAINTAINERS entry

* tag 'pinctrl-v4.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  MAINTAINERS: pinctrl: Add maintainers for pinctrl-single
  pinctrl: bcm2835: Fix initial value for direction_output
  pinctrl: intel: fix offset calculation issue of register PAD_OWN
  pinctrl: intel: fix bug of register offset calculation
  pinctrl: freescale: add ZERO_OFFSET_VALID flag for vf610 pinctrl
parents d7d3d841 13cbd906
...@@ -8380,6 +8380,14 @@ L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) ...@@ -8380,6 +8380,14 @@ L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
S: Maintained S: Maintained
F: drivers/pinctrl/samsung/ F: drivers/pinctrl/samsung/
PIN CONTROLLER - SINGLE
M: Tony Lindgren <tony@atomide.com>
M: Haojian Zhuang <haojian.zhuang@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-omap@vger.kernel.org
S: Maintained
F: drivers/pinctrl/pinctrl-single.c
PIN CONTROLLER - ST SPEAR PIN CONTROLLER - ST SPEAR
M: Viresh Kumar <vireshk@kernel.org> M: Viresh Kumar <vireshk@kernel.org>
L: spear-devel@list.st.com L: spear-devel@list.st.com
......
...@@ -342,12 +342,6 @@ static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) ...@@ -342,12 +342,6 @@ static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
return bcm2835_gpio_get_bit(pc, GPLEV0, offset); return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
} }
static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
return pinctrl_gpio_direction_output(chip->base + offset);
}
static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{ {
struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
...@@ -355,6 +349,13 @@ static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) ...@@ -355,6 +349,13 @@ static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
} }
static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
bcm2835_gpio_set(chip, offset, value);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset) static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{ {
struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
......
...@@ -299,7 +299,7 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = { ...@@ -299,7 +299,7 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info vf610_pinctrl_info = { static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
.pins = vf610_pinctrl_pads, .pins = vf610_pinctrl_pads,
.npins = ARRAY_SIZE(vf610_pinctrl_pads), .npins = ARRAY_SIZE(vf610_pinctrl_pads),
.flags = SHARE_MUX_CONF_REG, .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
}; };
static const struct of_device_id vf610_pinctrl_of_match[] = { static const struct of_device_id vf610_pinctrl_of_match[] = {
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
.padcfglock_offset = BXT_PADCFGLOCK, \ .padcfglock_offset = BXT_PADCFGLOCK, \
.hostown_offset = BXT_HOSTSW_OWN, \ .hostown_offset = BXT_HOSTSW_OWN, \
.ie_offset = BXT_GPI_IE, \ .ie_offset = BXT_GPI_IE, \
.gpp_size = 32, \
.pin_base = (s), \ .pin_base = (s), \
.npins = ((e) - (s) + 1), \ .npins = ((e) - (s) + 1), \
} }
......
...@@ -25,9 +25,6 @@ ...@@ -25,9 +25,6 @@
#include "pinctrl-intel.h" #include "pinctrl-intel.h"
/* Maximum number of pads in each group */
#define NPADS_IN_GPP 24
/* Offset from regs */ /* Offset from regs */
#define PADBAR 0x00c #define PADBAR 0x00c
#define GPI_IS 0x100 #define GPI_IS 0x100
...@@ -37,6 +34,7 @@ ...@@ -37,6 +34,7 @@
#define PADOWN_BITS 4 #define PADOWN_BITS 4
#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
#define PADOWN_GPP(p) ((p) / 8)
/* Offset from pad_regs */ /* Offset from pad_regs */
#define PADCFG0 0x000 #define PADCFG0 0x000
...@@ -142,7 +140,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, ...@@ -142,7 +140,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
{ {
const struct intel_community *community; const struct intel_community *community;
unsigned padno, gpp, gpp_offset, offset; unsigned padno, gpp, offset, group;
void __iomem *padown; void __iomem *padown;
community = intel_get_community(pctrl, pin); community = intel_get_community(pctrl, pin);
...@@ -152,9 +150,9 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) ...@@ -152,9 +150,9 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
return true; return true;
padno = pin_to_padno(community, pin); padno = pin_to_padno(community, pin);
gpp = padno / NPADS_IN_GPP; group = padno / community->gpp_size;
gpp_offset = padno % NPADS_IN_GPP; gpp = PADOWN_GPP(padno % community->gpp_size);
offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4; offset = community->padown_offset + 0x10 * group + gpp * 4;
padown = community->regs + offset; padown = community->regs + offset;
return !(readl(padown) & PADOWN_MASK(padno)); return !(readl(padown) & PADOWN_MASK(padno));
...@@ -173,11 +171,11 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) ...@@ -173,11 +171,11 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
return false; return false;
padno = pin_to_padno(community, pin); padno = pin_to_padno(community, pin);
gpp = padno / NPADS_IN_GPP; gpp = padno / community->gpp_size;
offset = community->hostown_offset + gpp * 4; offset = community->hostown_offset + gpp * 4;
hostown = community->regs + offset; hostown = community->regs + offset;
return !(readl(hostown) & BIT(padno % NPADS_IN_GPP)); return !(readl(hostown) & BIT(padno % community->gpp_size));
} }
static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
...@@ -193,7 +191,7 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) ...@@ -193,7 +191,7 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
return false; return false;
padno = pin_to_padno(community, pin); padno = pin_to_padno(community, pin);
gpp = padno / NPADS_IN_GPP; gpp = padno / community->gpp_size;
/* /*
* If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
...@@ -202,12 +200,12 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) ...@@ -202,12 +200,12 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
*/ */
offset = community->padcfglock_offset + gpp * 8; offset = community->padcfglock_offset + gpp * 8;
value = readl(community->regs + offset); value = readl(community->regs + offset);
if (value & BIT(pin % NPADS_IN_GPP)) if (value & BIT(pin % community->gpp_size))
return true; return true;
offset = community->padcfglock_offset + 4 + gpp * 8; offset = community->padcfglock_offset + 4 + gpp * 8;
value = readl(community->regs + offset); value = readl(community->regs + offset);
if (value & BIT(pin % NPADS_IN_GPP)) if (value & BIT(pin % community->gpp_size))
return true; return true;
return false; return false;
...@@ -663,8 +661,8 @@ static void intel_gpio_irq_ack(struct irq_data *d) ...@@ -663,8 +661,8 @@ static void intel_gpio_irq_ack(struct irq_data *d)
community = intel_get_community(pctrl, pin); community = intel_get_community(pctrl, pin);
if (community) { if (community) {
unsigned padno = pin_to_padno(community, pin); unsigned padno = pin_to_padno(community, pin);
unsigned gpp_offset = padno % NPADS_IN_GPP; unsigned gpp_offset = padno % community->gpp_size;
unsigned gpp = padno / NPADS_IN_GPP; unsigned gpp = padno / community->gpp_size;
writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
} }
...@@ -685,8 +683,8 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) ...@@ -685,8 +683,8 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
community = intel_get_community(pctrl, pin); community = intel_get_community(pctrl, pin);
if (community) { if (community) {
unsigned padno = pin_to_padno(community, pin); unsigned padno = pin_to_padno(community, pin);
unsigned gpp_offset = padno % NPADS_IN_GPP; unsigned gpp_offset = padno % community->gpp_size;
unsigned gpp = padno / NPADS_IN_GPP; unsigned gpp = padno / community->gpp_size;
void __iomem *reg; void __iomem *reg;
u32 value; u32 value;
...@@ -780,8 +778,8 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) ...@@ -780,8 +778,8 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
return -EINVAL; return -EINVAL;
padno = pin_to_padno(community, pin); padno = pin_to_padno(community, pin);
gpp = padno / NPADS_IN_GPP; gpp = padno / community->gpp_size;
gpp_offset = padno % NPADS_IN_GPP; gpp_offset = padno % community->gpp_size;
/* Clear the existing wake status */ /* Clear the existing wake status */
writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
...@@ -819,14 +817,14 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, ...@@ -819,14 +817,14 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
/* Only interrupts that are enabled */ /* Only interrupts that are enabled */
pending &= enabled; pending &= enabled;
for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) { for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
unsigned padno, irq; unsigned padno, irq;
/* /*
* The last group in community can have less pins * The last group in community can have less pins
* than NPADS_IN_GPP. * than NPADS_IN_GPP.
*/ */
padno = gpp_offset + gpp * NPADS_IN_GPP; padno = gpp_offset + gpp * community->gpp_size;
if (padno >= community->npins) if (padno >= community->npins)
break; break;
...@@ -1002,7 +1000,8 @@ int intel_pinctrl_probe(struct platform_device *pdev, ...@@ -1002,7 +1000,8 @@ int intel_pinctrl_probe(struct platform_device *pdev,
community->regs = regs; community->regs = regs;
community->pad_regs = regs + padbar; community->pad_regs = regs + padbar;
community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP); community->ngpps = DIV_ROUND_UP(community->npins,
community->gpp_size);
} }
irq = platform_get_irq(pdev, 0); irq = platform_get_irq(pdev, 0);
......
...@@ -55,6 +55,8 @@ struct intel_function { ...@@ -55,6 +55,8 @@ struct intel_function {
* ACPI). * ACPI).
* @ie_offset: Register offset of GPI_IE from @regs. * @ie_offset: Register offset of GPI_IE from @regs.
* @pin_base: Starting pin of pins in this community * @pin_base: Starting pin of pins in this community
* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
* HOSTSW_OWN, GPI_IS, GPI_IE, etc.
* @npins: Number of pins in this community * @npins: Number of pins in this community
* @regs: Community specific common registers (reserved for core driver) * @regs: Community specific common registers (reserved for core driver)
* @pad_regs: Community specific pad registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver)
...@@ -68,6 +70,7 @@ struct intel_community { ...@@ -68,6 +70,7 @@ struct intel_community {
unsigned hostown_offset; unsigned hostown_offset;
unsigned ie_offset; unsigned ie_offset;
unsigned pin_base; unsigned pin_base;
unsigned gpp_size;
size_t npins; size_t npins;
void __iomem *regs; void __iomem *regs;
void __iomem *pad_regs; void __iomem *pad_regs;
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
.padcfglock_offset = SPT_PADCFGLOCK, \ .padcfglock_offset = SPT_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \ .hostown_offset = SPT_HOSTSW_OWN, \
.ie_offset = SPT_GPI_IE, \ .ie_offset = SPT_GPI_IE, \
.gpp_size = 24, \
.pin_base = (s), \ .pin_base = (s), \
.npins = ((e) - (s) + 1), \ .npins = ((e) - (s) + 1), \
} }
......
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