Commit 39921e5f authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
parent fdbec9ff
......@@ -1350,7 +1350,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
*/
#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
#define HAS_GT_UC(dev_priv) (GRAPHICS_VER(dev_priv) >= 9)
#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
......
......@@ -2008,7 +2008,7 @@ __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 du
return ERR_PTR(-ENOMEM);
}
if (HAS_GT_UC(i915)) {
if (INTEL_INFO(i915)->has_gt_uc) {
error->gt->uc = gt_record_uc(error->gt, compress);
if (error->gt->uc) {
if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
......
......@@ -644,6 +644,7 @@ static const struct intel_device_info chv_info = {
GEN(9), \
GEN9_DEFAULT_PAGE_SIZES, \
.display.has_dmc = 1, \
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
.display.has_psr = 1, \
......@@ -704,6 +705,7 @@ static const struct intel_device_info skl_gt4_info = {
.has_rps = true, \
.display.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.has_gt_uc = 1, \
.dma_mask_size = 39, \
.ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
......@@ -1006,6 +1008,7 @@ static const struct intel_device_info adl_p_info = {
.has_64bit_reloc = 1, \
.has_flat_ccs = 1, \
.has_global_mocs = 1, \
.has_gt_uc = 1, \
.has_llc = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
......
......@@ -141,6 +141,7 @@ enum intel_ppgtt_type {
func(has_4tile); \
func(has_flat_ccs); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
......
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