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Commit 39eda2ab authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull powerpc updates from Ben Herrenschmidt:
 "Here's the powerpc batch for this merge window.  Some of the
  highlights are:

   - A bunch of endian fixes ! We don't have full LE support yet in that
     release but this contains a lot of fixes all over arch/powerpc to
     use the proper accessors, call the firmware with the right endian
     mode, etc...

   - A few updates to our "powernv" platform (non-virtualized, the one
     to run KVM on), among other, support for bridging the P8 LPC bus
     for UARTs, support and some EEH fixes.

   - Some mpc51xx clock API cleanups in preparation for a clock API
     overhaul

   - A pile of cleanups of our old math emulation code, including better
     support for using it to emulate optional FP instructions on
     embedded chips that otherwise have a HW FPU.

   - Some infrastructure in selftest, for powerpc now, but could be
     generalized, initially used by some tests for our perf instruction
     counting code.

   - A pile of fixes for hotplug on pseries (that was seriously
     bitrotting)

   - The usual slew of freescale embedded updates, new boards, 64-bit
     hiberation support, e6500 core PMU support, etc..."

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (146 commits)
  powerpc: Correct FSCR bit definitions
  powerpc/xmon: Fix printing of set of CPUs in xmon
  powerpc/pseries: Move lparcfg.c to platforms/pseries
  powerpc/powernv: Return secondary CPUs to firmware on kexec
  powerpc/btext: Fix CONFIG_PPC_EARLY_DEBUG_BOOTX on ppc32
  powerpc: Cleanup handling of the DSCR bit in the FSCR register
  powerpc/pseries: Child nodes are not detached by dlpar_detach_node
  powerpc/pseries: Add mising of_node_put in delete_dt_node
  powerpc/pseries: Make dlpar_configure_connector parent node aware
  powerpc/pseries: Do all node initialization in dlpar_parse_cc_node
  powerpc/pseries: Fix parsing of initial node path in update_dt_node
  powerpc/pseries: Pack update_props_workarea to map correctly to rtas buffer header
  powerpc/pseries: Fix over writing of rtas return code in update_dt_node
  powerpc/pseries: Fix creation of loop in device node property list
  powerpc: Skip emulating & leave interrupts off for kernel program checks
  powerpc: Add more exception trampolines for hypervisor exceptions
  powerpc: Fix location and rename exception trampolines
  powerpc: Add more trap names to xmon
  powerpc/pseries: Add a warning in the case of cross-cpu VPA registration
  powerpc: Update the 00-Index in Documentation/powerpc
  ...
parents 2e515bf0 9f24b0c9
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Documentation/devicetree/bindings/crypto/fsl-sec6.txt 0 → 100644
View file @ 39eda2ab
SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
Currently Freescale powerpc chip C29X is embeded with SEC 6.
SEC 6 device tree binding include:
-SEC 6 Node
-Job Ring Node
-Full Example
=====================================================================
SEC 6 Node
Description
Node defines the base address of the SEC 6 block.
This block specifies the address range of all global
configuration registers for the SEC 6 block.
For example, In C293, we could see three SEC 6 node.
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v6.0".
- fsl,sec-era
Usage: optional
Value type: <u32>
Definition: A standard property. Define the 'ERA' of the SEC
device.
- #address-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing physical addresses in child nodes.
- #size-cells
Usage: required
Value type: <u32>
Definition: A standard property. Defines the number of cells
for representing the size of physical addresses in
child nodes.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical
address and length of the SEC 6 configuration registers.
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the physical address
range of the SEC 6.0 register space (-SNVS not included). A
triplet that includes the child address, parent address, &
length.
Note: All other standard properties (see the ePAPR) are allowed
but are optional.
EXAMPLE
crypto@a0000 {
compatible = "fsl,sec-v6.0";
fsl,sec-era = <6>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0xa0000 0x20000>;
ranges = <0 0xa0000 0x20000>;
};
=====================================================================
Job Ring (JR) Node
Child of the crypto node defines data processing interface to SEC 6
across the peripheral bus for purposes of processing
cryptographic descriptors. The specified address
range can be made visible to one (or more) cores.
The interrupt defined for this node is controlled within
the address range of this node.
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v6.0-job-ring".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies a two JR parameters: an offset from
the parent physical address and the length the JR registers.
- interrupts
Usage: required
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
consists of one interrupt specifier. The format
of the specifier is defined by the binding document
describing the node's interrupt parent.
EXAMPLE
jr@1000 {
compatible = "fsl,sec-v6.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <49 2 0 0>;
};
===================================================================
Full Example
Since some chips may contain more than one SEC, the dtsi contains
only the node contents, not the node itself. A chip using the SEC
should include the dtsi inside each SEC node. Example:
In qoriq-sec6.0.dtsi:
compatible = "fsl,sec-v6.0";
fsl,sec-era = <6>;
#address-cells = <1>;
#size-cells = <1>;
jr@1000 {
compatible = "fsl,sec-v6.0-job-ring",
"fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.4-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
};
jr@2000 {
compatible = "fsl,sec-v6.0-job-ring",
"fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.4-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
};
In the C293 device tree, we add the include of public property:
crypto@a0000 {
/include/ "qoriq-sec6.0.dtsi"
}
crypto@a0000 {
reg = <0xa0000 0x20000>;
ranges = <0 0xa0000 0x20000>;
jr@1000 {
interrupts = <49 2 0 0>;
};
jr@2000 {
interrupts = <50 2 0 0>;
};
};
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
View file @ 39eda2ab
* Freescale MSI interrupt controller
Required properties:
- compatible : compatible list, contains 2 entries,
first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
the parent type.
- compatible : compatible list, may contain one or two entries
The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
"fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
should be used. The first entry is optional; the second entry is
required.
- reg : It may contain one or two regions. The first region should contain
the address and the length of the shared message interrupt register set.
The second region should contain the address of aliased MSIIR register for
platforms that have such an alias.
- msi-available-ranges: use <start count> style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
optional, without this, all the 256 MSI interrupts can be used.
Each available range must begin and end on a multiple of 32 (i.e.
no splitting an individual MSI register or the associated PIC interrupt).
The second region should contain the address of aliased MSIIR or MSIIR1
register for platforms that have such an alias, if using MSIIR1, the second
region must be added because different MSI group has different MSIIR1 offset.
- interrupts : each one of the interrupts here is one entry per 32 MSIs,
and routed to the host interrupt controller. the interrupts should
......@@ -28,6 +27,14 @@ Required properties:
to MPIC.
Optional properties:
- msi-available-ranges: use <start count> style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
optional, without this, all the MSI interrupts can be used.
Each available range must begin and end on a multiple of 32 (i.e.
no splitting an individual MSI register or the associated PIC interrupt).
MPIC v4.3 does not support this property because the 32 interrupts of an
individual register are not continuous when using MSIIR1.
- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
is used for MSI messaging. The address of MSIIR in PCI address space is
the MSI message address.
......@@ -54,6 +61,28 @@ Example:
interrupt-parent = <&mpic>;
};
msi@41600 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41600 0x200 0x44148 4>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0
0xe4 0 0 0
0xe5 0 0 0
0xe6 0 0 0
0xe7 0 0 0
0x100 0 0 0
0x101 0 0 0
0x102 0 0 0
0x103 0 0 0
0x104 0 0 0
0x105 0 0 0
0x106 0 0 0
0x107 0 0 0>;
};
The Freescale hypervisor and msi-address-64
-------------------------------------------
Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
......
Documentation/powerpc/00-INDEX
View file @ 39eda2ab
......@@ -5,13 +5,20 @@ please mail me.
00-INDEX
- this file
bootwrapper.txt
- Information on how the powerpc kernel is wrapped for boot on various
different platforms.
cpu_features.txt
- info on how we support a variety of CPUs with minimal compile-time
options.
eeh-pci-error-recovery.txt
- info on PCI Bus EEH Error Recovery
firmware-assisted-dump.txt
- Documentation on the firmware assisted dump mechanism "fadump".
hvcs.txt
- IBM "Hypervisor Virtual Console Server" Installation Guide
kvm_440.txt
- Various notes on the implementation of KVM for PowerPC 440.
mpc52xx.txt
- Linux 2.6.x on MPC52xx family
pmu-ebb.txt
......@@ -19,3 +26,7 @@ pmu-ebb.txt
qe_firmware.txt
- describes the layout of firmware binaries for the Freescale QUICC
Engine and the code that parses and uploads the microcode therein.
ptrace.txt
- Information on the ptrace interfaces for hardware debug registers.
transactional_memory.txt
- Overview of the Power8 transactional memory support.
arch/powerpc/Kconfig
View file @ 39eda2ab
......@@ -312,6 +312,26 @@ config MATH_EMULATION
such as fsqrt on cores that do have an FPU but do not implement
them (such as Freescale BookE).
choice
prompt "Math emulation options"
default MATH_EMULATION_FULL
depends on MATH_EMULATION
config MATH_EMULATION_FULL
bool "Emulate all the floating point instructions"
---help---
Select this option will enable the kernel to support to emulate
all the floating point instructions. If your SoC doesn't have
a FPU, you should select this.
config MATH_EMULATION_HW_UNIMPLEMENTED
bool "Just emulate the FPU unimplemented instructions"
---help---
Select this if you know there does have a hardware FPU on your
SoC, but some floating point instructions are not implemented by that.
endchoice
config PPC_TRANSACTIONAL_MEM
bool "Transactional Memory support for POWERPC"
depends on PPC_BOOK3S_64
......
arch/powerpc/Makefile
View file @ 39eda2ab
......@@ -88,13 +88,30 @@ CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,-mminimal-toc)
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mno-pointers-to-nested-functions)
CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple
ifeq ($(CONFIG_PPC_BOOK3S_64),y)
CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power7,-mtune=power4)
else
CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=powerpc64
endif
CFLAGS-$(CONFIG_CELL_CPU) += $(call cc-option,-mcpu=cell)
CFLAGS-$(CONFIG_POWER4_CPU) += $(call cc-option,-mcpu=power4)
CFLAGS-$(CONFIG_POWER5_CPU) += $(call cc-option,-mcpu=power5)
CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6)
CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)
E5500_CPU := $(call cc-option,-mcpu=e500mc64,-mcpu=powerpc64)
CFLAGS-$(CONFIG_E5500_CPU) += $(E5500_CPU)
CFLAGS-$(CONFIG_E6500_CPU) += $(call cc-option,-mcpu=e6500,$(E5500_CPU))
ifeq ($(CONFIG_PPC32),y)
ifeq ($(CONFIG_PPC_E500MC),y)
CFLAGS-y += $(call cc-option,-mcpu=e500mc,-mcpu=powerpc)
else
CFLAGS-$(CONFIG_E500) += $(call cc-option,-mcpu=8540 -msoft-float,-mcpu=powerpc)
endif
endif
CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell)
KBUILD_CPPFLAGS += -Iarch/$(ARCH)
......@@ -139,7 +156,6 @@ endif
cpu-as-$(CONFIG_4xx) += -Wa,-m405
cpu-as-$(CONFIG_ALTIVEC) += -Wa,-maltivec
cpu-as-$(CONFIG_E500) += -Wa,-me500
cpu-as-$(CONFIG_E200) += -Wa,-me200
KBUILD_AFLAGS += $(cpu-as-y)
......
arch/powerpc/boot/.gitignore
View file @ 39eda2ab
......@@ -22,6 +22,7 @@ zImage.initrd
zImage.bin.*
zImage.chrp
zImage.coff
zImage.epapr
zImage.holly
zImage.*lds
zImage.miboot
......
arch/powerpc/boot/dts/ac14xx.dts
View file @ 39eda2ab
......@@ -10,7 +10,7 @@
*/
/include/ "mpc5121.dtsi"
#include <mpc5121.dtsi>
/ {
model = "ac14xx";
......
arch/powerpc/boot/dts/b4420qds.dts
View file @ 39eda2ab
......@@ -33,7 +33,7 @@
*/
/include/ "fsl/b4420si-pre.dtsi"
/include/ "b4qds.dts"
/include/ "b4qds.dtsi"
/ {
model = "fsl,B4420QDS";
......
arch/powerpc/boot/dts/b4860qds.dts
View file @ 39eda2ab
......@@ -33,7 +33,7 @@
*/
/include/ "fsl/b4860si-pre.dtsi"
/include/ "b4qds.dts"
/include/ "b4qds.dtsi"
/ {
model = "fsl,B4860QDS";
......
arch/powerpc/boot/dts/c293pcie.dts 0 → 100644
View file @ 39eda2ab
/*
* C293 PCIE Device Tree Source
*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/c293si-pre.dtsi"
/ {
model = "fsl,C293PCIE";
compatible = "fsl,C293PCIE";
memory {
device_type = "memory";
};
ifc: ifc@fffe1e000 {
reg = <0xf 0xffe1e000 0 0x2000>;
ranges = <0x0 0x0 0xf 0xec000000 0x04000000
0x2 0x0 0xf 0xffdf0000 0x00010000>;
};
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci0: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
&ifc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 1MB for DTB Image */
reg = <0x0 0x00100000>;
label = "NOR DTB Image";
};
partition@100000 {
/* 8 MB for Linux Kernel Image */
reg = <0x00100000 0x00800000>;
label = "NOR Linux Kernel Image";
};
partition@900000 {
/* 53MB for rootfs */
reg = <0x00900000 0x03500000>;
label = "NOR Rootfs Image";
};
partition@3e00000 {
/* 1MB for blob encrypted key */
reg = <0x03e00000 0x00100000>;
label = "NOR blob encrypted key";
};
partition@3f00000 {
/* 512KB for u-boot Bootloader Image and evn */
reg = <0x03f00000 0x00100000>;
label = "NOR U-Boot Image";
read-only;
};
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
partition@100000 {
/* 1MB for DTB Image */
reg = <0x00100000 0x00100000>;
label = "NAND DTB Image";
};
partition@200000 {
/* 16MB for Linux Kernel Image */
reg = <0x00200000 0x01000000>;
label = "NAND Linux Kernel Image";
};
partition@1200000 {
/* 4078MB for Root file System Image */
reg = <0x00600000 0xfee00000>;
label = "NAND RFS Image";
};
};
cpld@2,0 {
compatible = "fsl,c293pcie-cpld";
reg = <0x2 0x0 0x20>;
};
};
&soc {
i2c@3000 {
eeprom@50 {
compatible = "st,24c1024";
reg = <0x50>;
};
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <50000000>;
partition@0 {
/* 1MB for u-boot Bootloader Image */
/* 1MB for Environment */
reg = <0x0 0x00100000>;
label = "SPI Flash U-Boot Image";
read-only;
};
partition@100000 {
/* 512KB for DTB Image */
reg = <0x00100000 0x00080000>;
label = "SPI Flash DTB Image";
};
partition@180000 {
/* 4MB for Linux Kernel Image */
reg = <0x00180000 0x00400000>;
label = "SPI Flash Linux Kernel Image";
};
partition@580000 {
/* 10.5MB for RFS Image */
reg = <0x00580000 0x00a80000>;
label = "SPI Flash RFS Image";
};
};
};
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <2 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x2>;
};
};
enet0: ethernet@b0000 {
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};
/include/ "fsl/c293si-post.dtsi"
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
View file @ 39eda2ab
......@@ -204,7 +204,7 @@ pamu3: pamu@3000 {
};
};
/include/ "qoriq-mpic.dtsi"
/include/ "qoriq-mpic4.3.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,b4-device-config";
......
arch/powerpc/boot/dts/fsl/c293si-post.dtsi 0 → 100644
View file @ 39eda2ab
/*
* C293 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&ifc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,ifc", "simple-bus";
interrupts = <19 2 0 0>;
};
/* controller at 0xa000 */
&pci0 {
compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0 255>;
clock-frequency = <33333333>;
interrupts = <16 2 0 0>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <16 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,c293-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2 0 0>;
};
memory-controller@2000 {
compatible = "fsl,c293-memory-controller";
reg = <0x2000 0x1000>;
interrupts = <16 2 0 0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"
/include/ "pq3-espi-0.dtsi"
spi0: spi@7000 {
fsl,espi-num-chipselects = <1>;
};
/include/ "pq3-gpio-0.dtsi"
L2: l2-cache-controller@20000 {
compatible = "fsl,c293-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2,512K
interrupts = <16 2 0 0>;
};
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
compatible = "fsl,c293-esdhc", "fsl,esdhc";
sdhci,auto-cmd12;
};
crypto@80000 {
/include/ "qoriq-sec6.0-0.dtsi"
};
crypto@80000 {
reg = <0x80000 0x20000>;
ranges = <0x0 0x80000 0x20000>;
jr@1000{
interrupts = <45 2 0 0>;
};
jr@2000{
interrupts = <57 2 0 0>;
};
};
crypto@a0000 {
/include/ "qoriq-sec6.0-0.dtsi"
};
crypto@a0000 {
reg = <0xa0000 0x20000>;
ranges = <0x0 0xa0000 0x20000>;
jr@1000{
interrupts = <49 2 0 0>;
};
jr@2000{
interrupts = <50 2 0 0>;
};
};
crypto@c0000 {
/include/ "qoriq-sec6.0-0.dtsi"
};
crypto@c0000 {
reg = <0xc0000 0x20000>;
ranges = <0x0 0xc0000 0x20000>;
jr@1000{
interrupts = <55 2 0 0>;
};
jr@2000{
interrupts = <56 2 0 0>;
};
};
/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"
/include/ "pq3-etsec2-0.dtsi"
enet0: ethernet@b0000 {
queue-group@b0000 {
reg = <0x10000 0x1000>;
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
};
};
/include/ "pq3-etsec2-1.dtsi"
enet1: ethernet@b1000 {
queue-group@b1000 {
reg = <0x11000 0x1000>;
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
};
};
global-utilities@e0000 {
compatible = "fsl,c293-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
arch/powerpc/boot/dts/fsl/c293si-pre.dtsi 0 → 100644
View file @ 39eda2ab
/*
* C293 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,C293";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
serial0 = &serial0;
serial1 = &serial1;
ethernet0 = &enet0;
ethernet1 = &enet1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,e500v2@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi 0 → 100644
View file @ 39eda2ab
/*
* QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
timer@41100 {
compatible = "fsl,mpic-global-timer";
reg = <0x41100 0x100 0x41300 4>;
interrupts = <0 0 3 0
1 0 3 0
2 0 3 0
3 0 3 0>;
};
msi0: msi@41600 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41600 0x200 0x44148 4>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0
0xe4 0 0 0
0xe5 0 0 0
0xe6 0 0 0
0xe7 0 0 0
0x100 0 0 0
0x101 0 0 0
0x102 0 0 0
0x103 0 0 0
0x104 0 0 0
0x105 0 0 0
0x106 0 0 0
0x107 0 0 0>;
};
msi1: msi@41800 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41800 0x200 0x45148 4>;
interrupts = <
0xe8 0 0 0
0xe9 0 0 0
0xea 0 0 0
0xeb 0 0 0
0xec 0 0 0
0xed 0 0 0
0xee 0 0 0
0xef 0 0 0
0x108 0 0 0
0x109 0 0 0
0x10a 0 0 0
0x10b 0 0 0
0x10c 0 0 0
0x10d 0 0 0
0x10e 0 0 0
0x10f 0 0 0>;
};
msi2: msi@41a00 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41a00 0x200 0x46148 4>;
interrupts = <
0xf0 0 0 0
0xf1 0 0 0
0xf2 0 0 0
0xf3 0 0 0
0xf4 0 0 0
0xf5 0 0 0
0xf6 0 0 0
0xf7 0 0 0
0x110 0 0 0
0x111 0 0 0
0x112 0 0 0
0x113 0 0 0
0x114 0 0 0
0x115 0 0 0
0x116 0 0 0
0x117 0 0 0>;
};
msi3: msi@41c00 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41c00 0x200 0x47148 4>;
interrupts = <
0xf8 0 0 0
0xf9 0 0 0
0xfa 0 0 0
0xfb 0 0 0
0xfc 0 0 0
0xfd 0 0 0
0xfe 0 0 0
0xff 0 0 0
0x118 0 0 0
0x119 0 0 0
0x11a 0 0 0
0x11b 0 0 0
0x11c 0 0 0
0x11d 0 0 0
0x11e 0 0 0
0x11f 0 0 0>;
};
timer@42100 {
compatible = "fsl,mpic-global-timer";
reg = <0x42100 0x100 0x42300 4>;
interrupts = <4 0 3 0
5 0 3 0
6 0 3 0
7 0 3 0>;
};
arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi 0 → 100644
View file @ 39eda2ab
/*
* QorIQ Sec/Crypto 6.0 device tree stub
*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
compatible = "fsl,sec-v6.0";
fsl,sec-era = <6>;
#address-cells = <1>;
#size-cells = <1>;
jr@1000 {
compatible = "fsl,sec-v6.0-job-ring",
"fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.4-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
};
jr@2000 {
compatible = "fsl,sec-v6.0-job-ring",
"fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.4-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
};
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
View file @ 39eda2ab
......@@ -358,7 +358,7 @@ iommu@20000 {
16 2 1 30>;
};
/include/ "qoriq-mpic.dtsi"
/include/ "qoriq-mpic4.3.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
......
arch/powerpc/boot/dts/include/dt-bindings 0 → 120000
View file @ 39eda2ab
../../../../../include/dt-bindings
\ No newline at end of file
arch/powerpc/boot/dts/mpc5121ads.dts
View file @ 39eda2ab
......@@ -9,7 +9,7 @@
* option) any later version.
*/
/include/ "mpc5121.dtsi"
#include <mpc5121.dtsi>
/ {
model = "mpc5121ads";
......
arch/powerpc/boot/dts/p1020rdb-pd.dts 0 → 100644
View file @ 39eda2ab
/*
* P1020 RDB-PD Device Tree Source (32-bit address map)
*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1020si-pre.dtsi"
/ {
model = "fsl,P1020RDB-PD";
compatible = "fsl,P1020RDB-PD";
memory {
device_type = "memory";
};
lbc: localbus@ffe05000 {
reg = <0x0 0xffe05000 0x0 0x1000>;
/* NOR, NAND flash, L2 switch and CPLD */
ranges = <0x0 0x0 0x0 0xec000000 0x04000000
0x1 0x0 0x0 0xff800000 0x00040000
0x2 0x0 0x0 0xffa00000 0x00020000
0x3 0x0 0x0 0xffb00000 0x00020000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 128KB for DTB Image */
reg = <0x0 0x00020000>;
label = "NOR DTB Image";
};
partition@20000 {
/* 3.875 MB for Linux Kernel Image */
reg = <0x00020000 0x003e0000>;
label = "NOR Linux Kernel Image";
};
partition@400000 {
/* 58MB for Root file System */
reg = <0x00400000 0x03a00000>;
label = "NOR Root File System";
};
partition@3e00000 {
/* This location must not be altered */
/* 1M for Vitesse 7385 Switch firmware */
reg = <0x3e00000 0x00100000>;
label = "NOR Vitesse-7385 Firmware";
read-only;
};
partition@3f00000 {
/* This location must not be altered */
/* 512KB for u-boot Bootloader Image */
/* 512KB for u-boot Environment Variables */
reg = <0x03f00000 0x00100000>;
label = "NOR U-Boot Image";
read-only;
};
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1020-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x40000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
partition@100000 {
/* 1MB for DTB Image */
reg = <0x00100000 0x00100000>;
label = "NAND DTB Image";
};
partition@200000 {
/* 4MB for Linux Kernel Image */
reg = <0x00200000 0x00400000>;
label = "NAND Linux Kernel Image";
};
partition@600000 {
/* 122MB for File System Image */
reg = <0x00600000 0x07a00000>;
label = "NAND File System Image";
};
};
cpld@2,0 {
compatible = "fsl,p1020rdb-pd-cpld";
reg = <0x2 0x0 0x20000>;
};
L2switch@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "vitesse-7385";
reg = <0x3 0x0 0x20000>;
};
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
i2c@3000 {
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
/* input clock */
spi-max-frequency = <40000000>;
partition@0 {
/* 512KB for u-boot Bootloader Image */
reg = <0x0 0x00080000>;
label = "SPI U-Boot Image";
read-only;
};
partition@80000 {
/* 512KB for DTB Image*/
reg = <0x00080000 0x00080000>;
label = "SPI DTB Image";
};
partition@100000 {
/* 4MB for Linux Kernel Image */
reg = <0x00100000 0x00400000>;
label = "SPI Linux Kernel Image";
};
partition@500000 {
/* 11MB for FS System Image */
reg = <0x00500000 0x00b00000>;
label = "SPI File System Image";
};
};
slic@0 {
compatible = "zarlink,le88266";
reg = <1>;
spi-max-frequency = <8000000>;
};
slic@1 {
compatible = "zarlink,le88266";
reg = <2>;
spi-max-frequency = <8000000>;
};
};
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x1>;
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
usb@22000 {
phy_type = "ulpi";
};
};
pci0: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "fsl/p1020si-post.dtsi"
arch/powerpc/boot/dts/p1023rdb.dts 0 → 100644
View file @ 39eda2ab
/*
* P1023 RDB Device Tree Source
*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Author: Chunhe Lan <Chunhe.Lan@freescale.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1023si-pre.dtsi"
/ {
model = "fsl,P1023";
compatible = "fsl,P1023RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
memory {
device_type = "memory";
};
soc: soc@ff600000 {
ranges = <0x0 0x0 0xff600000 0x200000>;
i2c@3000 {
eeprom@53 {
compatible = "at24,24c04";
reg = <0x53>;
};
rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
};
};
usb@22000 {
dr_mode = "host";
phy_type = "ulpi";
};
};
lbc: localbus@ff605000 {
reg = <0 0xff605000 0 0x1000>;
/* NOR, NAND Flashes */
ranges = <0x0 0x0 0x0 0xec000000 0x04000000
0x1 0x0 0x0 0xffa00000 0x08000000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x04000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 48MB for Root File System */
reg = <0x00000000 0x03000000>;
label = "NOR Root File System";
};
partition@3000000 {
/* 1MB for DTB Image */
reg = <0x03000000 0x00100000>;
label = "NOR DTB Image";
};
partition@3100000 {
/* 14MB for Linux Kernel Image */
reg = <0x03100000 0x00e00000>;
label = "NOR Linux Kernel Image";
};
partition@3f00000 {
/* This location must not be altered */
/* 512KB for u-boot Bootloader Image */
/* 512KB for u-boot Environment Variables */
reg = <0x03f00000 0x00100000>;
label = "NOR U-Boot Image";
read-only;
};
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x40000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
partition@100000 {
/* 1MB for DTB Image */
reg = <0x00100000 0x00100000>;
label = "NAND DTB Image";
};
partition@200000 {
/* 14MB for Linux Kernel Image */
reg = <0x00200000 0x00e00000>;
label = "NAND Linux Kernel Image";
};
partition@1000000 {
/* 96MB for Root File System Image */
reg = <0x01000000 0x06000000>;
label = "NAND Root File System";
};
partition@7000000 {
/* 16MB for User Writable Area */
reg = <0x07000000 0x01000000>;
label = "NAND Writable User area";
};
};
};
pci0: pcie@ff60a000 {
reg = <0 0xff60a000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
pcie@0 {
/* IRQ[0:3] are pulled up on board, set to active-low */
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1 0 0
0000 0 0 2 &mpic 1 1 0 0
0000 0 0 3 &mpic 2 1 0 0
0000 0 0 4 &mpic 3 1 0 0
>;
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
board_pci1: pci1: pcie@ff609000 {
reg = <0 0xff609000 0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
pcie@0 {
/*
* IRQ[4:6] only for PCIe, set to active-high,
* IRQ[7] is pulled up on board, set to active-low
*/
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 2 0 0
0000 0 0 2 &mpic 5 2 0 0
0000 0 0 3 &mpic 6 2 0 0
0000 0 0 4 &mpic 7 1 0 0
>;
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci2: pcie@ff60b000 {
reg = <0 0xff60b000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
pcie@0 {
/*
* IRQ[8:10] are pulled up on board, set to active-low
* IRQ[11] only for PCIe, set to active-high,
*/
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 8 1 0 0
0000 0 0 2 &mpic 9 1 0 0
0000 0 0 3 &mpic 10 1 0 0
0000 0 0 4 &mpic 11 2 0 0
>;
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "fsl/p1023si-post.dtsi"
arch/powerpc/boot/dts/pdm360ng.dts
View file @ 39eda2ab
......@@ -13,7 +13,7 @@
* option) any later version.
*/
/include/ "mpc5121.dtsi"
#include <mpc5121.dtsi>
/ {
model = "pdm360ng";
......
arch/powerpc/boot/ppc_asm.h
View file @ 39eda2ab
......@@ -59,4 +59,7 @@
#define r30 30
#define r31 31
#define SPRN_TBRL 268
#define SPRN_TBRU 269
#endif /* _PPC64_PPC_ASM_H */
arch/powerpc/boot/util.S
View file @ 39eda2ab
......@@ -71,18 +71,18 @@ udelay:
add r4,r4,r5
addi r4,r4,-1
divw r4,r4,r5 /* BUS ticks */
1: mftbu r5
mftb r6
mftbu r7
1: mfspr r5, SPRN_TBRU
mfspr r6, SPRN_TBRL
mfspr r7, SPRN_TBRU
cmpw 0,r5,r7
bne 1b /* Get [synced] base time */
addc r9,r6,r4 /* Compute end time */
addze r8,r5
2: mftbu r5
2: mfspr r5, SPRN_TBRU
cmpw 0,r5,r8
blt 2b
bgt 3f
mftb r6
mfspr r6, SPRN_TBRL
cmpw 0,r6,r9
blt 2b
3: blr
arch/powerpc/configs/85xx/p1023rds_defconfig → arch/powerpc/configs/85xx/p1023_defconfig
View file @ 39eda2ab
CONFIG_PPC_85xx=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_AUDIT=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
......@@ -22,6 +21,8 @@ CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
CONFIG_PHYSICAL_START=0x00000000
CONFIG_P1023_RDB=y
CONFIG_P1023_RDS=y
CONFIG_QUICC_ENGINE=y
CONFIG_QE_GPIO=y
......@@ -63,10 +64,21 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_LEGACY=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
......@@ -82,6 +94,8 @@ CONFIG_DUMMY=y
CONFIG_FS_ENET=y
CONFIG_FSL_PQ_MDIO=y
CONFIG_E1000E=y
CONFIG_PHYLIB=y
CONFIG_AT803X_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_DAVICOM_PHY=y
CONFIG_CICADA_PHY=y
......@@ -96,12 +110,15 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_QE=m
CONFIG_HW_RANDOM=y
CONFIG_NVRAM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_CPM=m
CONFIG_I2C_MPC=y
CONFIG_GPIO_MPC8XXX=y
......@@ -121,6 +138,7 @@ CONFIG_USB_STORAGE=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_DMADEVICES=y
CONFIG_FSL_DMA=y
......@@ -161,6 +179,7 @@ CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
CONFIG_STRICT_DEVMEM=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
......
arch/powerpc/configs/corenet32_smp_defconfig
View file @ 39eda2ab
......@@ -70,6 +70,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
......
arch/powerpc/configs/corenet64_smp_defconfig
View file @ 39eda2ab
......@@ -27,6 +27,8 @@ CONFIG_P5040_DS=y
CONFIG_T4240_QDS=y
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
CONFIG_BINFMT_MISC=m
CONFIG_MATH_EMULATION=y
CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y
CONFIG_FSL_IFC=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_MSI=y
......@@ -59,6 +61,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_OF_PARTS=y
......
arch/powerpc/configs/mpc83xx_defconfig
View file @ 39eda2ab
......@@ -42,6 +42,7 @@ CONFIG_INET_ESP=y
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_CHAR=y
......
arch/powerpc/configs/mpc85xx_defconfig
View file @ 39eda2ab
......@@ -27,6 +27,7 @@ CONFIG_MPC85xx_MDS=y
CONFIG_MPC8536_DS=y
CONFIG_MPC85xx_DS=y
CONFIG_MPC85xx_RDB=y
CONFIG_C293_PCIE=y
CONFIG_P1010_RDB=y
CONFIG_P1022_DS=y
CONFIG_P1022_RDK=y
......@@ -78,6 +79,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_OF_PARTS=y
......
arch/powerpc/configs/mpc85xx_smp_defconfig
View file @ 39eda2ab
......@@ -30,6 +30,7 @@ CONFIG_MPC85xx_MDS=y
CONFIG_MPC8536_DS=y
CONFIG_MPC85xx_DS=y
CONFIG_MPC85xx_RDB=y
CONFIG_C293_PCIE=y
CONFIG_P1010_RDB=y
CONFIG_P1022_DS=y
CONFIG_P1022_RDK=y
......@@ -81,6 +82,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_OF_PARTS=y
......
arch/powerpc/include/asm/asm-compat.h
View file @ 39eda2ab
......@@ -32,6 +32,15 @@
#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)
#define PPC_LR_STKOFF 16
#define PPC_MIN_STKFRM 112
#ifdef __BIG_ENDIAN__
#define LDX_BE stringify_in_c(ldx)
#define STDX_BE stringify_in_c(stdx)
#else
#define LDX_BE stringify_in_c(ldbrx)
#define STDX_BE stringify_in_c(stdbrx)
#endif
#else /* 32-bit */
/* operations for longs and pointers */
......
arch/powerpc/include/asm/btext.h
View file @ 39eda2ab
......@@ -13,6 +13,7 @@ extern void btext_update_display(unsigned long phys, int width, int height,
extern void btext_setup_display(int width, int height, int depth, int pitch,
unsigned long address);
extern void btext_prepare_BAT(void);
extern void btext_map(void);
extern void btext_unmap(void);
extern void btext_drawchar(char c);
......
arch/powerpc/include/asm/cacheflush.h
View file @ 39eda2ab
......@@ -32,13 +32,7 @@ extern void flush_dcache_page(struct page *page);
extern void __flush_disable_L1(void);
extern void __flush_icache_range(unsigned long, unsigned long);
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
__flush_icache_range(start, stop);
}
extern void flush_icache_range(unsigned long, unsigned long);
extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr,
int len);
......
arch/powerpc/include/asm/cputable.h
View file @ 39eda2ab
......@@ -371,14 +371,19 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
/*
* e5500/e6500 erratum A-006958 is a timebase bug that can use the
* same workaround as CPU_FTR_CELL_TB_BUG.
*/
#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_CELL_TB_BUG)
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
/* 64-bit CPUs */
......
arch/powerpc/include/asm/emulated_ops.h
View file @ 39eda2ab
......@@ -46,8 +46,6 @@ extern struct ppc_emulated {
struct ppc_emulated_entry unaligned;
#ifdef CONFIG_MATH_EMULATION
struct ppc_emulated_entry math;
#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
struct ppc_emulated_entry 8xx;
#endif
#ifdef CONFIG_VSX
struct ppc_emulated_entry vsx;
......
arch/powerpc/include/asm/epapr_hcalls.h
View file @ 39eda2ab
......@@ -105,6 +105,12 @@
extern bool epapr_paravirt_enabled;
extern u32 epapr_hypercall_start[];
#ifdef CONFIG_EPAPR_PARAVIRT
int __init epapr_paravirt_early_init(void);
#else
static inline int epapr_paravirt_early_init(void) { return 0; }
#endif
/*
* We use "uintptr_t" to define a register because it's guaranteed to be a
* 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
......
arch/powerpc/include/asm/exception-64s.h
View file @ 39eda2ab
......@@ -48,17 +48,18 @@
#define EX_LR 72
#define EX_CFAR 80
#define EX_PPR 88 /* SMT thread status register (priority) */
#define EX_CTR 96
#ifdef CONFIG_RELOCATABLE
#define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
ld r12,PACAKBASE(r13); /* get high part of &label */ \
mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
LOAD_HANDLER(r12,label); \
mtlr r12; \
mtctr r12; \
mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
li r10,MSR_RI; \
mtmsrd r10,1; /* Set RI (EE=0) */ \
blr;
bctr;
#else
/* If not relocatable, we can jump directly -- and save messing with LR */
#define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
......@@ -97,18 +98,18 @@
#if defined(CONFIG_RELOCATABLE)
/*
* If we support interrupts with relocation on AND we're a relocatable
* kernel, we need to use LR to get to the 2nd level handler. So, save/restore
* it when required.
* If we support interrupts with relocation on AND we're a relocatable kernel,
* we need to use CTR to get to the 2nd level handler. So, save/restore it
* when required.
*/
#define SAVE_LR(reg, area) mflr reg ; std reg,area+EX_LR(r13)
#define GET_LR(reg, area) ld reg,area+EX_LR(r13)
#define RESTORE_LR(reg, area) ld reg,area+EX_LR(r13) ; mtlr reg
#define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
#define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
#define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
#else
/* ...else LR is unused and in register. */
#define SAVE_LR(reg, area)
#define GET_LR(reg, area) mflr reg
#define RESTORE_LR(reg, area)
/* ...else CTR is unused and in register. */
#define SAVE_CTR(reg, area)
#define GET_CTR(reg, area) mfctr reg
#define RESTORE_CTR(reg, area)
#endif
/*
......@@ -164,7 +165,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
#define __EXCEPTION_PROLOG_1(area, extra, vec) \
OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \
SAVE_LR(r10, area); \
SAVE_CTR(r10, area); \
mfcr r9; \
extra(vec); \
std r11,area+EX_R11(r13); \
......@@ -270,7 +271,7 @@ do_kvm_##n: \
sth r1,PACA_TRAP_SAVE(r13); \
std r3,area+EX_R3(r13); \
addi r3,r13,area; /* r3 -> where regs are saved*/ \
RESTORE_LR(r1, area); \
RESTORE_CTR(r1, area); \
b bad_stack; \
3: std r9,_CCR(r1); /* save CR in stackframe */ \
std r11,_NIP(r1); /* save SRR0 in stackframe */ \
......@@ -298,10 +299,10 @@ do_kvm_##n: \
ld r10,area+EX_CFAR(r13); \
std r10,ORIG_GPR3(r1); \
END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
GET_LR(r9,area); /* Get LR, later save to stack */ \
mflr r9; /* Get LR, later save to stack */ \
ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
std r9,_LINK(r1); \
mfctr r10; /* save CTR in stackframe */ \
GET_CTR(r10, area); \
std r10,_CTR(r1); \
lbz r10,PACASOFTIRQEN(r13); \
mfspr r11,SPRN_XER; /* save XER in stackframe */ \
......@@ -479,7 +480,7 @@ label##_relon_hv: \
*/
/* Exception addition: Hard disable interrupts */
#define DISABLE_INTS SOFT_DISABLE_INTS(r10,r11)
#define DISABLE_INTS RECONCILE_IRQ_STATE(r10,r11)
#define ADD_NVGPRS \
bl .save_nvgprs
......
arch/powerpc/include/asm/io.h
View file @ 39eda2ab
......@@ -69,8 +69,18 @@ extern unsigned long pci_dram_offset;
extern resource_size_t isa_mem_base;
#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
/* Boolean set by platform if PIO accesses are suppored while _IO_BASE
* is not set or addresses cannot be translated to MMIO. This is typically
* set when the platform supports "special" PIO accesses via a non memory
* mapped mechanism, and allows things like the early udbg UART code to
* function.
*/
extern bool isa_io_special;
#ifdef CONFIG_PPC32
#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
#error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
#endif
#endif
/*
......@@ -222,9 +232,9 @@ extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
* for PowerPC is as close as possible to the x86 version of these, and thus
* provides fairly heavy weight barriers for the non-raw versions
*
* In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
* allowing the platform to provide its own implementation of some or all
* of the accessors.
* In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
* or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
* own implementation of some or all of the accessors.
*/
/*
......@@ -240,8 +250,8 @@ extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
/* Indirect IO address tokens:
*
* When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
* on all IOs. (Note that this is all 64 bits only for now)
* When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
* on all MMIOs. (Note that this is all 64 bits only for now)
*
* To help platforms who may need to differenciate MMIO addresses in
* their hooks, a bitfield is reserved for use by the platform near the
......@@ -263,11 +273,14 @@ extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
*
* The direct IO mapping operations will then mask off those bits
* before doing the actual access, though that only happen when
* CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
* CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
* mechanism
*
* For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
* all PIO functions call through a hook.
*/
#ifdef CONFIG_PPC_INDIRECT_IO
#ifdef CONFIG_PPC_INDIRECT_MMIO
#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
#define PCI_IO_IND_TOKEN_SHIFT 48
#define PCI_FIX_ADDR(addr) \
......@@ -672,7 +685,7 @@ extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
extern void __iounmap_at(void *ea, unsigned long size);
/*
* When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
* When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
* which needs some additional definitions here. They basically allow PIO
* space overall to be 1GB. This will work as long as we never try to use
* iomap to map MMIO below 1GB which should be fine on ppc64
......
arch/powerpc/include/asm/irqflags.h
View file @ 39eda2ab
......@@ -40,9 +40,10 @@
#define TRACE_DISABLE_INTS TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off)
/*
* This is used by assembly code to soft-disable interrupts
* This is used by assembly code to soft-disable interrupts first and
* reconcile irq state.
*/
#define SOFT_DISABLE_INTS(__rA, __rB) \
#define RECONCILE_IRQ_STATE(__rA, __rB) \
lbz __rA,PACASOFTIRQEN(r13); \
lbz __rB,PACAIRQHAPPENED(r13); \
cmpwi cr0,__rA,0; \
......@@ -58,7 +59,7 @@
#define TRACE_ENABLE_INTS
#define TRACE_DISABLE_INTS
#define SOFT_DISABLE_INTS(__rA, __rB) \
#define RECONCILE_IRQ_STATE(__rA, __rB) \
lbz __rA,PACAIRQHAPPENED(r13); \
li __rB,0; \
ori __rA,__rA,PACA_IRQ_HARD_DIS; \
......
arch/powerpc/include/asm/lppaca.h
View file @ 39eda2ab
......@@ -48,15 +48,13 @@
struct lppaca {
/* cacheline 1 contains read-only data */
u32 desc; /* Eye catcher 0xD397D781 */
u16 size; /* Size of this struct */
u16 reserved1;
u16 reserved2:14;
u8 shared_proc:1; /* Shared processor indicator */
u8 secondary_thread:1; /* Secondary thread indicator */
__be32 desc; /* Eye catcher 0xD397D781 */
__be16 size; /* Size of this struct */
u8 reserved1[3];
u8 __old_status; /* Old status, including shared proc */
u8 reserved3[14];
volatile u32 dyn_hw_node_id; /* Dynamic hardware node id */
volatile u32 dyn_hw_proc_id; /* Dynamic hardware proc id */
volatile __be32 dyn_hw_node_id; /* Dynamic hardware node id */
volatile __be32 dyn_hw_proc_id; /* Dynamic hardware proc id */
u8 reserved4[56];
volatile u8 vphn_assoc_counts[8]; /* Virtual processor home node */
/* associativity change counters */
......@@ -73,9 +71,9 @@ struct lppaca {
u8 fpregs_in_use;
u8 pmcregs_in_use;
u8 reserved8[28];
u64 wait_state_cycles; /* Wait cycles for this proc */
__be64 wait_state_cycles; /* Wait cycles for this proc */
u8 reserved9[28];
u16 slb_count; /* # of SLBs to maintain */
__be16 slb_count; /* # of SLBs to maintain */
u8 idle; /* Indicate OS is idle */
u8 vmxregs_in_use;
......@@ -89,17 +87,17 @@ struct lppaca {
* NOTE: This value will ALWAYS be zero for dedicated processors and
* will NEVER be zero for shared processors (ie, initialized to a 1).
*/
volatile u32 yield_count;
volatile u32 dispersion_count; /* dispatch changed physical cpu */
volatile u64 cmo_faults; /* CMO page fault count */
volatile u64 cmo_fault_time; /* CMO page fault time */
volatile __be32 yield_count;
volatile __be32 dispersion_count; /* dispatch changed physical cpu */
volatile __be64 cmo_faults; /* CMO page fault count */
volatile __be64 cmo_fault_time; /* CMO page fault time */
u8 reserved10[104];
/* cacheline 4-5 */
u32 page_ins; /* CMO Hint - # page ins by OS */
__be32 page_ins; /* CMO Hint - # page ins by OS */
u8 reserved11[148];
volatile u64 dtl_idx; /* Dispatch Trace Log head index */
volatile __be64 dtl_idx; /* Dispatch Trace Log head index */
u8 reserved12[96];
} __attribute__((__aligned__(0x400)));
......@@ -107,18 +105,30 @@ extern struct lppaca lppaca[];
#define lppaca_of(cpu) (*paca[cpu].lppaca_ptr)
/*
* Old kernels used a reserved bit in the VPA to determine if it was running
* in shared processor mode. New kernels look for a non zero yield count
* but KVM still needs to set the bit to keep the old stuff happy.
*/
#define LPPACA_OLD_SHARED_PROC 2
static inline bool lppaca_shared_proc(struct lppaca *l)
{
return l->yield_count != 0;
}
/*
* SLB shadow buffer structure as defined in the PAPR. The save_area
* contains adjacent ESID and VSID pairs for each shadowed SLB. The
* ESID is stored in the lower 64bits, then the VSID.
*/
struct slb_shadow {
u32 persistent; /* Number of persistent SLBs */
u32 buffer_length; /* Total shadow buffer length */
u64 reserved;
__be32 persistent; /* Number of persistent SLBs */
__be32 buffer_length; /* Total shadow buffer length */
__be64 reserved;
struct {
u64 esid;
u64 vsid;
__be64 esid;
__be64 vsid;
} save_area[SLB_NUM_BOLTED];
} ____cacheline_aligned;
......@@ -130,14 +140,14 @@ extern struct slb_shadow slb_shadow[];
struct dtl_entry {
u8 dispatch_reason;
u8 preempt_reason;
u16 processor_id;
u32 enqueue_to_dispatch_time;
u32 ready_to_enqueue_time;
u32 waiting_to_ready_time;
u64 timebase;
u64 fault_addr;
u64 srr0;
u64 srr1;
__be16 processor_id;
__be32 enqueue_to_dispatch_time;
__be32 ready_to_enqueue_time;
__be32 waiting_to_ready_time;
__be64 timebase;
__be64 fault_addr;
__be64 srr0;
__be64 srr1;
};
#define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */
......
arch/powerpc/include/asm/mpc5121.h
View file @ 39eda2ab
......@@ -32,25 +32,11 @@ struct mpc512x_ccm {
u32 scfr2; /* System Clock Frequency Register 2 */
u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
u32 bcr; /* Bread Crumb Register */
u32 p0ccr; /* PSC0 Clock Control Register */
u32 p1ccr; /* PSC1 CCR */
u32 p2ccr; /* PSC2 CCR */
u32 p3ccr; /* PSC3 CCR */
u32 p4ccr; /* PSC4 CCR */
u32 p5ccr; /* PSC5 CCR */
u32 p6ccr; /* PSC6 CCR */
u32 p7ccr; /* PSC7 CCR */
u32 p8ccr; /* PSC8 CCR */
u32 p9ccr; /* PSC9 CCR */
u32 p10ccr; /* PSC10 CCR */
u32 p11ccr; /* PSC11 CCR */
u32 psc_ccr[12]; /* PSC Clock Control Registers */
u32 spccr; /* SPDIF Clock Control Register */
u32 cccr; /* CFM Clock Control Register */
u32 dccr; /* DIU Clock Control Register */
u32 m1ccr; /* MSCAN1 CCR */
u32 m2ccr; /* MSCAN2 CCR */
u32 m3ccr; /* MSCAN3 CCR */
u32 m4ccr; /* MSCAN4 CCR */
u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
u8 res[0x98]; /* Reserved */
};
......
arch/powerpc/include/asm/mpc85xx.h 0 → 100644
View file @ 39eda2ab
/*
* MPC85xx cpu type detection
*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __ASM_PPC_MPC85XX_H
#define __ASM_PPC_MPC85XX_H
#define SVR_REV(svr) ((svr) & 0xFF) /* SOC design resision */
#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
/* Some parts define SVR[0:23] as the SOC version */
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC Version fields */
#define SVR_8533 0x803400
#define SVR_8535 0x803701
#define SVR_8536 0x803700
#define SVR_8540 0x803000
#define SVR_8541 0x807200
#define SVR_8543 0x803200
#define SVR_8544 0x803401
#define SVR_8545 0x803102
#define SVR_8547 0x803101
#define SVR_8548 0x803100
#define SVR_8555 0x807100
#define SVR_8560 0x807000
#define SVR_8567 0x807501
#define SVR_8568 0x807500
#define SVR_8569 0x808000
#define SVR_8572 0x80E000
#define SVR_P1010 0x80F100
#define SVR_P1011 0x80E500
#define SVR_P1012 0x80E501
#define SVR_P1013 0x80E700
#define SVR_P1014 0x80F101
#define SVR_P1017 0x80F700
#define SVR_P1020 0x80E400
#define SVR_P1021 0x80E401
#define SVR_P1022 0x80E600
#define SVR_P1023 0x80F600
#define SVR_P1024 0x80E402
#define SVR_P1025 0x80E403
#define SVR_P2010 0x80E300
#define SVR_P2020 0x80E200
#define SVR_P2040 0x821000
#define SVR_P2041 0x821001
#define SVR_P3041 0x821103
#define SVR_P4040 0x820100
#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
#define SVR_P5020 0x822000
#define SVR_P5021 0X820500
#define SVR_P5040 0x820400
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
#define SVR_C291 0x850000
#define SVR_C292 0x850020
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
#define SVR_B4420 0x868102
#define SVR_B4220 0x868103
#define SVR_T1040 0x852000
#define SVR_T1041 0x852001
#define SVR_T1042 0x852002
#define SVR_T1020 0x852100
#define SVR_T1021 0x852101
#define SVR_T1022 0x852102
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
#define SVR_8641D 0x809001
#define SVR_9130 0x860001
#define SVR_9131 0x860000
#define SVR_9132 0x861000
#define SVR_9232 0x861400
#define SVR_Unknown 0xFFFFFF
#endif
arch/powerpc/include/asm/mpic.h
View file @ 39eda2ab
......@@ -396,7 +396,14 @@ extern struct bus_type mpic_subsys;
#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
/* Get the version of primary MPIC */
#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
#else
static inline u32 fsl_mpic_primary_get_version(void)
{
return 0;
}
#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
......
arch/powerpc/include/asm/opal.h
View file @ 39eda2ab
......@@ -124,6 +124,11 @@ extern int opal_enter_rtas(struct rtas_args *args,
#define OPAL_PCI_POLL 62
#define OPAL_PCI_MSI_EOI 63
#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
#define OPAL_XSCOM_READ 65
#define OPAL_XSCOM_WRITE 66
#define OPAL_LPC_READ 67
#define OPAL_LPC_WRITE 68
#define OPAL_RETURN_CPU 69
#ifndef __ASSEMBLY__
......@@ -337,6 +342,17 @@ enum OpalEpowStatus {
OPAL_EPOW_OVER_INTERNAL_TEMP = 3
};
/*
* Address cycle types for LPC accesses. These also correspond
* to the content of the first cell of the "reg" property for
* device nodes on the LPC bus
*/
enum OpalLPCAddressType {
OPAL_LPC_MEM = 0,
OPAL_LPC_IO = 1,
OPAL_LPC_FW = 2,
};
struct opal_machine_check_event {
enum OpalMCE_Version version:8; /* 0x00 */
uint8_t in_use; /* 0x01 */
......@@ -631,6 +647,15 @@ int64_t opal_set_system_attention_led(uint8_t led_action);
int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
uint16_t *pci_error_type, uint16_t *severity);
int64_t opal_pci_poll(uint64_t phb_id);
int64_t opal_return_cpu(void);
int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val);
int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val);
int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
uint32_t addr, uint32_t data, uint32_t sz);
int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
uint32_t addr, uint32_t *data, uint32_t sz);
/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
......@@ -664,6 +689,8 @@ extern int opal_machine_check(struct pt_regs *regs);
extern void opal_shutdown(void);
extern void opal_lpc_init(void);
#endif /* __ASSEMBLY__ */
#endif /* __OPAL_H */
arch/powerpc/include/asm/paca.h
View file @ 39eda2ab
......@@ -68,8 +68,13 @@ struct paca_struct {
* instruction. They must travel together and be properly
* aligned.
*/
#ifdef __BIG_ENDIAN__
u16 lock_token; /* Constant 0x8000, used in locks */
u16 paca_index; /* Logical processor number */
#else
u16 paca_index; /* Logical processor number */
u16 lock_token; /* Constant 0x8000, used in locks */
#endif
u64 kernel_toc; /* Kernel TOC address */
u64 kernelbase; /* Base address of kernel */
......@@ -93,9 +98,9 @@ struct paca_struct {
* Now, starting in cacheline 2, the exception save areas
*/
/* used for most interrupts/exceptions */
u64 exgen[12] __attribute__((aligned(0x80)));
u64 exmc[12]; /* used for machine checks */
u64 exslb[12]; /* used for SLB/segment table misses
u64 exgen[13] __attribute__((aligned(0x80)));
u64 exmc[13]; /* used for machine checks */
u64 exslb[13]; /* used for SLB/segment table misses
* on the linear mapping */
/* SLB related definitions */
u16 vmalloc_sllp;
......
arch/powerpc/include/asm/pci-bridge.h
View file @ 39eda2ab
......@@ -159,7 +159,7 @@ struct pci_dn {
int pci_ext_config_space; /* for pci devices */
int force_32bit_msi:1;
bool force_32bit_msi;
struct pci_dev *pcidev; /* back-pointer to the pci device */
#ifdef CONFIG_EEH
......
arch/powerpc/include/asm/perf_event_fsl_emb.h
View file @ 39eda2ab
......@@ -13,7 +13,7 @@
#include <linux/types.h>
#include <asm/hw_irq.h>
#define MAX_HWEVENTS 4
#define MAX_HWEVENTS 6
/* event flags */
#define FSL_EMB_EVENT_VALID 1
......
arch/powerpc/platforms/pseries/plpar_wrappers.h → arch/powerpc/include/asm/plpar_wrappers.h
View file @ 39eda2ab
#ifndef _PSERIES_PLPAR_WRAPPERS_H
#define _PSERIES_PLPAR_WRAPPERS_H
#ifndef _ASM_POWERPC_PLPAR_WRAPPERS_H
#define _ASM_POWERPC_PLPAR_WRAPPERS_H
#include <linux/string.h>
#include <linux/irqflags.h>
......@@ -256,30 +256,6 @@ static inline long plpar_tce_stuff(unsigned long liobn, unsigned long ioba,
return plpar_hcall_norets(H_STUFF_TCE, liobn, ioba, tceval, count);
}
static inline long plpar_get_term_char(unsigned long termno,
unsigned long *len_ret, char *buf_ret)
{
long rc;
unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
unsigned long *lbuf = (unsigned long *)buf_ret; /* TODO: alignment? */
rc = plpar_hcall(H_GET_TERM_CHAR, retbuf, termno);
*len_ret = retbuf[0];
lbuf[0] = retbuf[1];
lbuf[1] = retbuf[2];
return rc;
}
static inline long plpar_put_term_char(unsigned long termno, unsigned long len,
const char *buffer)
{
unsigned long *lbuf = (unsigned long *)buffer; /* TODO: alignment? */
return plpar_hcall_norets(H_PUT_TERM_CHAR, termno, len, lbuf[0],
lbuf[1]);
}
/* Set various resource mode parameters */
static inline long plpar_set_mode(unsigned long mflags, unsigned long resource,
unsigned long value1, unsigned long value2)
......@@ -321,4 +297,4 @@ static inline long plapr_set_watchpoint0(unsigned long dawr0, unsigned long dawr
return plpar_set_mode(0, 2, dawr0, dawrx0);
}
#endif /* _PSERIES_PLPAR_WRAPPERS_H */
#endif /* _ASM_POWERPC_PLPAR_WRAPPERS_H */
arch/powerpc/include/asm/ppc-opcode.h
View file @ 39eda2ab
......@@ -81,6 +81,53 @@
#define __REGA0_R30 30
#define __REGA0_R31 31
/* opcode and xopcode for instructions */
#define OP_TRAP 3
#define OP_TRAP_64 2
#define OP_31_XOP_TRAP 4
#define OP_31_XOP_LWZX 23
#define OP_31_XOP_DCBST 54
#define OP_31_XOP_LWZUX 55
#define OP_31_XOP_TRAP_64 68
#define OP_31_XOP_DCBF 86
#define OP_31_XOP_LBZX 87
#define OP_31_XOP_STWX 151
#define OP_31_XOP_STBX 215
#define OP_31_XOP_LBZUX 119
#define OP_31_XOP_STBUX 247
#define OP_31_XOP_LHZX 279
#define OP_31_XOP_LHZUX 311
#define OP_31_XOP_MFSPR 339
#define OP_31_XOP_LHAX 343
#define OP_31_XOP_LHAUX 375
#define OP_31_XOP_STHX 407
#define OP_31_XOP_STHUX 439
#define OP_31_XOP_MTSPR 467
#define OP_31_XOP_DCBI 470
#define OP_31_XOP_LWBRX 534
#define OP_31_XOP_TLBSYNC 566
#define OP_31_XOP_STWBRX 662
#define OP_31_XOP_LHBRX 790
#define OP_31_XOP_STHBRX 918
#define OP_LWZ 32
#define OP_LD 58
#define OP_LWZU 33
#define OP_LBZ 34
#define OP_LBZU 35
#define OP_STW 36
#define OP_STWU 37
#define OP_STD 62
#define OP_STB 38
#define OP_STBU 39
#define OP_LHZ 40
#define OP_LHZU 41
#define OP_LHA 42
#define OP_LHAU 43
#define OP_STH 44
#define OP_STHU 45
/* sorted alphabetically */
#define PPC_INST_BHRBE 0x7c00025c
#define PPC_INST_CLRBHRB 0x7c00035c
......
arch/powerpc/include/asm/ppc_asm.h
View file @ 39eda2ab
......@@ -54,7 +54,8 @@ BEGIN_FW_FTR_SECTION; \
/* from user - see if there are any DTL entries to process */ \
ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \
addi r10,r10,LPPACA_DTLIDX; \
LDX_BE r10,0,r10; /* get log write index */ \
cmpd cr1,r11,r10; \
beq+ cr1,33f; \
bl .accumulate_stolen_time; \
......@@ -219,19 +220,6 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b)
#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b)
#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
/*
* b = base register for addressing, o = base offset from register of 1st EVR
......@@ -443,15 +431,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
#define ISYNC_601
#endif
#ifdef CONFIG_PPC_CELL
#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
#define MFTB(dest) \
90: mftb dest; \
90: mfspr dest, SPRN_TBRL; \
BEGIN_FTR_SECTION_NESTED(96); \
cmpwi dest,0; \
beq- 90b; \
END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
#else
#define MFTB(dest) mftb dest
#define MFTB(dest) mfspr dest, SPRN_TBRL
#endif
#ifndef CONFIG_SMP
......
arch/powerpc/include/asm/prom.h
View file @ 39eda2ab
......@@ -38,8 +38,9 @@ extern unsigned long pci_address_to_pio(phys_addr_t address);
/* Parse the ibm,dma-window property of an OF node into the busno, phys and
* size parameters.
*/
void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
unsigned long *busno, unsigned long *phys, unsigned long *size);
void of_parse_dma_window(struct device_node *dn, const __be32 *dma_window,
unsigned long *busno, unsigned long *phys,
unsigned long *size);
extern void kdump_move_device_tree(void);
......@@ -55,6 +56,8 @@ static inline int of_node_to_nid(struct device_node *device) { return 0; }
extern void of_instantiate_rtc(void);
extern int of_get_ibm_chip_id(struct device_node *np);
/* The of_drconf_cell struct defines the layout of the LMB array
* specified in the device tree property
* ibm,dynamic-reconfiguration-memory/ibm,dynamic-memory
......
arch/powerpc/include/asm/reg.h
View file @ 39eda2ab
......@@ -115,10 +115,10 @@
#define MSR_64BIT MSR_SF
/* Server variant */
#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
#define MSR_KERNEL MSR_ | MSR_64BIT
#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
#define MSR_USER64 MSR_USER32 | MSR_64BIT
#define MSR_ (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
#define MSR_KERNEL (MSR_ | MSR_64BIT)
#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
/* Default MSR for kernel mode. */
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
......@@ -258,8 +258,8 @@
#define FSCR_TAR_LG 8 /* Enable Target Address Register */
#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
#define FSCR_TM_LG 5 /* Enable Transactional Memory */
#define FSCR_PM_LG 4 /* Enable prob/priv access to PMU SPRs */
#define FSCR_BHRB_LG 3 /* Enable Branch History Rolling Buffer*/
#define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/
#define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */
#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */
#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
#define FSCR_FP_LG 0 /* Enable Floating Point */
......@@ -1126,10 +1126,10 @@
: "memory")
#ifdef __powerpc64__
#ifdef CONFIG_PPC_CELL
#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
#define mftb() ({unsigned long rval; \
asm volatile( \
"90: mftb %0;\n" \
"90: mfspr %0, %2;\n" \
"97: cmpwi %0,0;\n" \
" beq- 90b;\n" \
"99:\n" \
......@@ -1143,18 +1143,23 @@
" .llong 0\n" \
" .llong 0\n" \
".previous" \
: "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
: "=r" (rval) \
: "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL)); \
rval;})
#else
#define mftb() ({unsigned long rval; \
asm volatile("mftb %0" : "=r" (rval)); rval;})
asm volatile("mfspr %0, %1" : \
"=r" (rval) : "i" (SPRN_TBRL)); rval;})
#endif /* !CONFIG_PPC_CELL */
#else /* __powerpc64__ */
#define mftbl() ({unsigned long rval; \
asm volatile("mftbl %0" : "=r" (rval)); rval;})
asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRL)); rval;})
#define mftbu() ({unsigned long rval; \
asm volatile("mftbu %0" : "=r" (rval)); rval;})
asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRU)); rval;})
#endif /* !__powerpc64__ */
#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
......
arch/powerpc/include/asm/reg_booke.h
View file @ 39eda2ab
......@@ -29,10 +29,10 @@
#if defined(CONFIG_PPC_BOOK3E_64)
#define MSR_64BIT MSR_CM
#define MSR_ MSR_ME | MSR_CE
#define MSR_KERNEL MSR_ | MSR_64BIT
#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
#define MSR_USER64 MSR_USER32 | MSR_64BIT
#define MSR_ (MSR_ME | MSR_CE)
#define MSR_KERNEL (MSR_ | MSR_64BIT)
#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
#elif defined (CONFIG_40x)
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
......
arch/powerpc/include/asm/reg_fsl_emb.h
View file @ 39eda2ab
......@@ -17,12 +17,16 @@
/* Freescale Book E Performance Monitor APU Registers */
#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
#define PMRN_PMC2 0x012 /* Performance Monitor Counter 2 */
#define PMRN_PMC3 0x013 /* Performance Monitor Counter 3 */
#define PMRN_PMC4 0x014 /* Performance Monitor Counter 4 */
#define PMRN_PMC5 0x015 /* Performance Monitor Counter 5 */
#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
#define PMRN_PMLCA4 0x094 /* PM Local Control A4 */
#define PMRN_PMLCA5 0x095 /* PM Local Control A5 */
#define PMLCA_FC 0x80000000 /* Freeze Counter */
#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
......@@ -30,14 +34,18 @@
#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
#define PMLCA_CE 0x04000000 /* Condition Enable */
#define PMLCA_FGCS1 0x00000002 /* Freeze in guest state */
#define PMLCA_FGCS0 0x00000001 /* Freeze in hypervisor state */
#define PMLCA_EVENT_MASK 0x00ff0000 /* Event field */
#define PMLCA_EVENT_MASK 0x01ff0000 /* Event field */
#define PMLCA_EVENT_SHIFT 16
#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
#define PMRN_PMLCB4 0x114 /* PM Local Control B4 */
#define PMRN_PMLCB5 0x115 /* PM Local Control B5 */
#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshold Multiple Field */
#define PMLCB_THRESHMUL_SHIFT 8
......@@ -55,16 +63,22 @@
#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 2 */
#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 3 */
#define PMRN_UPMC4 0x004 /* User Performance Monitor Counter 4 */
#define PMRN_UPMC5 0x005 /* User Performance Monitor Counter 5 */
#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
#define PMRN_UPMLCA4 0x084 /* User PM Local Control A4 */
#define PMRN_UPMLCA5 0x085 /* User PM Local Control A5 */
#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
#define PMRN_UPMLCB4 0x104 /* User PM Local Control B4 */
#define PMRN_UPMLCB5 0x105 /* User PM Local Control B5 */
#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
......
arch/powerpc/include/asm/rtas.h
View file @ 39eda2ab
......@@ -44,12 +44,12 @@
*
*/
typedef u32 rtas_arg_t;
typedef __be32 rtas_arg_t;
struct rtas_args {
u32 token;
u32 nargs;
u32 nret;
__be32 token;
__be32 nargs;
__be32 nret;
rtas_arg_t args[16];
rtas_arg_t *rets; /* Pointer to return values in args[]. */
};
......
arch/powerpc/include/asm/smp.h
View file @ 39eda2ab
......@@ -112,6 +112,7 @@ static inline struct cpumask *cpu_core_mask(int cpu)
}
extern int cpu_to_core_id(int cpu);
extern int cpu_to_chip_id(int cpu);
/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
*
......@@ -186,6 +187,8 @@ extern int smt_enabled_at_boot;
extern int smp_mpic_probe(void);
extern void smp_mpic_setup_cpu(int cpu);
extern int smp_generic_kick_cpu(int nr);
extern int smp_generic_cpu_bootable(unsigned int nr);
extern void smp_generic_give_timebase(void);
extern void smp_generic_take_timebase(void);
......
arch/powerpc/include/asm/spinlock.h
View file @ 39eda2ab
......@@ -32,8 +32,12 @@
#ifdef CONFIG_PPC64
/* use 0x800000yy when locked, where yy == CPU number */
#ifdef __BIG_ENDIAN__
#define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
#else
#define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index))
#endif
#else
#define LOCK_TOKEN 1
#endif
......@@ -96,7 +100,7 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
#if defined(CONFIG_PPC_SPLPAR)
/* We only yield to the hypervisor if we are in shared processor mode */
#define SHARED_PROCESSOR (local_paca->lppaca_ptr->shared_proc)
#define SHARED_PROCESSOR (lppaca_shared_proc(local_paca->lppaca_ptr))
extern void __spin_yield(arch_spinlock_t *lock);
extern void __rw_yield(arch_rwlock_t *lock);
#else /* SPLPAR */
......
arch/powerpc/include/asm/switch_to.h
View file @ 39eda2ab
......@@ -25,11 +25,8 @@ static inline void save_tar(struct thread_struct *prev)
static inline void save_tar(struct thread_struct *prev) {}
#endif
extern void giveup_fpu(struct task_struct *);
extern void load_up_fpu(void);
extern void disable_kernel_fp(void);
extern void enable_kernel_fp(void);
extern void flush_fp_to_thread(struct task_struct *);
extern void enable_kernel_altivec(void);
extern void load_up_altivec(struct task_struct *);
extern int emulate_altivec(struct pt_regs *);
......@@ -47,6 +44,14 @@ static inline void discard_lazy_cpu_state(void)
}
#endif
#ifdef CONFIG_PPC_FPU
extern void flush_fp_to_thread(struct task_struct *);
extern void giveup_fpu(struct task_struct *);
#else
static inline void flush_fp_to_thread(struct task_struct *t) { }
static inline void giveup_fpu(struct task_struct *t) { }
#endif
#ifdef CONFIG_ALTIVEC
extern void flush_altivec_to_thread(struct task_struct *);
extern void giveup_altivec(struct task_struct *);
......
arch/powerpc/include/asm/timex.h
View file @ 39eda2ab
......@@ -29,7 +29,7 @@ static inline cycles_t get_cycles(void)
ret = 0;
__asm__ __volatile__(
"97: mftb %0\n"
"97: mfspr %0, %2\n"
"99:\n"
".section __ftr_fixup,\"a\"\n"
".align 2\n"
......@@ -41,7 +41,7 @@ static inline cycles_t get_cycles(void)
" .long 0\n"
" .long 0\n"
".previous"
: "=r" (ret) : "i" (CPU_FTR_601));
: "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
return ret;
#endif
}
......
arch/powerpc/include/asm/topology.h
View file @ 39eda2ab
......@@ -96,6 +96,7 @@ static inline int prrn_is_enabled(void)
#ifdef CONFIG_PPC64
#include <asm/smp.h>
#define topology_physical_package_id(cpu) (cpu_to_chip_id(cpu))
#define topology_thread_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu))
#define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu))
#define topology_core_id(cpu) (cpu_to_core_id(cpu))
......
arch/powerpc/include/asm/udbg.h
View file @ 39eda2ab
......@@ -27,10 +27,11 @@ extern void udbg_printf(const char *fmt, ...)
__attribute__ ((format (printf, 1, 2)));
extern void udbg_progress(char *s, unsigned short hex);
extern void udbg_init_uart(void __iomem *comport, unsigned int speed,
unsigned int clock);
extern unsigned int udbg_probe_uart_speed(void __iomem *comport,
unsigned int clock);
extern void udbg_uart_init_mmio(void __iomem *addr, unsigned int stride);
extern void udbg_uart_init_pio(unsigned long port, unsigned int stride);
extern void udbg_uart_setup(unsigned int speed, unsigned int clock);
extern unsigned int udbg_probe_uart_speed(unsigned int clock);
struct device_node;
extern void udbg_scc_init(int force_scc);
......
arch/powerpc/include/uapi/asm/elf.h
View file @ 39eda2ab
......@@ -107,26 +107,25 @@ typedef elf_gregset_t32 compat_elf_gregset_t;
# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
# define ELF_GREG_TYPE elf_greg_t64
# define ELF_ARCH EM_PPC64
# define ELF_CLASS ELFCLASS64
typedef elf_greg_t64 elf_greg_t;
typedef elf_gregset_t64 elf_gregset_t;
#else
# define ELF_NEVRREG 34 /* includes acc (as 2) */
# define ELF_NVRREG 33 /* includes vscr */
# define ELF_GREG_TYPE elf_greg_t32
# define ELF_ARCH EM_PPC
# define ELF_CLASS ELFCLASS32
# define ELF_DATA ELFDATA2MSB
typedef elf_greg_t32 elf_greg_t;
typedef elf_gregset_t32 elf_gregset_t;
#endif /* __powerpc64__ */
#ifndef ELF_ARCH
# define ELF_ARCH EM_PPC64
# define ELF_CLASS ELFCLASS64
# define ELF_DATA ELFDATA2MSB
typedef elf_greg_t64 elf_greg_t;
typedef elf_gregset_t64 elf_gregset_t;
#ifdef __BIG_ENDIAN__
#define ELF_DATA ELFDATA2MSB
#else
/* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
typedef elf_greg_t32 elf_greg_t;
typedef elf_gregset_t32 elf_gregset_t;
#endif /* ELF_ARCH */
#define ELF_DATA ELFDATA2LSB
#endif
/* Floating point registers */
typedef double elf_fpreg_t;
......
arch/powerpc/kernel/Makefile
View file @ 39eda2ab
......@@ -55,7 +55,6 @@ obj-$(CONFIG_PPC_RTAS) += rtas.o rtas-rtc.o $(rtaspci-y-y)
obj-$(CONFIG_PPC_RTAS_DAEMON) += rtasd.o
obj-$(CONFIG_RTAS_FLASH) += rtas_flash.o
obj-$(CONFIG_RTAS_PROC) += rtas-proc.o
obj-$(CONFIG_LPARCFG) += lparcfg.o
obj-$(CONFIG_IBMVIO) += vio.o
obj-$(CONFIG_IBMEBUS) += ibmebus.o
obj-$(CONFIG_EEH) += eeh.o eeh_pe.o eeh_dev.o eeh_cache.o \
......@@ -117,9 +116,7 @@ obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
ifneq ($(CONFIG_PPC_INDIRECT_PIO),y)
obj-y += iomap.o
endif
......
arch/powerpc/kernel/align.c
View file @ 39eda2ab
......@@ -651,6 +651,10 @@ static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
int sw = 0;
int i, j;
/* userland only */
if (unlikely(!user_mode(regs)))
return 0;
flush_vsx_to_thread(current);
if (reg < 32)
......@@ -764,6 +768,16 @@ int fix_alignment(struct pt_regs *regs)
nb = aligninfo[instr].len;
flags = aligninfo[instr].flags;
/* ldbrx/stdbrx overlap lfs/stfs in the DSISR unfortunately */
if (IS_XFORM(instruction) && ((instruction >> 1) & 0x3ff) == 532) {
nb = 8;
flags = LD+SW;
} else if (IS_XFORM(instruction) &&
((instruction >> 1) & 0x3ff) == 660) {
nb = 8;
flags = ST+SW;
}
/* Byteswap little endian loads and stores */
swiz = 0;
if (regs->msr & MSR_LE) {
......
arch/powerpc/kernel/btext.c
View file @ 39eda2ab
......@@ -25,11 +25,6 @@
static void scrollscreen(void);
#endif
static void draw_byte(unsigned char c, long locX, long locY);
static void draw_byte_32(unsigned char *bits, unsigned int *base, int rb);
static void draw_byte_16(unsigned char *bits, unsigned int *base, int rb);
static void draw_byte_8(unsigned char *bits, unsigned int *base, int rb);
#define __force_data __attribute__((__section__(".data")))
static int g_loc_X __force_data;
......@@ -52,6 +47,26 @@ static unsigned char vga_font[cmapsz];
int boot_text_mapped __force_data = 0;
int force_printk_to_btext = 0;
extern void rmci_on(void);
extern void rmci_off(void);
static inline void rmci_maybe_on(void)
{
#if defined(CONFIG_PPC_EARLY_DEBUG_BOOTX) && defined(CONFIG_PPC64)
if (!(mfmsr() & MSR_DR))
rmci_on();
#endif
}
static inline void rmci_maybe_off(void)
{
#if defined(CONFIG_PPC_EARLY_DEBUG_BOOTX) && defined(CONFIG_PPC64)
if (!(mfmsr() & MSR_DR))
rmci_off();
#endif
}
#ifdef CONFIG_PPC32
/* Calc BAT values for mapping the display and store them
* in disp_BAT. Those values are then used from head.S to map
......@@ -134,7 +149,7 @@ void __init btext_unmap(void)
* changes.
*/
static void map_boot_text(void)
void btext_map(void)
{
unsigned long base, offset, size;
unsigned char *vbase;
......@@ -209,7 +224,7 @@ int btext_initialize(struct device_node *np)
dispDeviceRect[2] = width;
dispDeviceRect[3] = height;
map_boot_text();
btext_map();
return 0;
}
......@@ -283,7 +298,7 @@ void btext_update_display(unsigned long phys, int width, int height,
iounmap(logicalDisplayBase);
boot_text_mapped = 0;
}
map_boot_text();
btext_map();
g_loc_X = 0;
g_loc_Y = 0;
g_max_loc_X = width / 8;
......@@ -298,6 +313,7 @@ void btext_clearscreen(void)
(dispDeviceDepth >> 3)) >> 2;
int i,j;
rmci_maybe_on();
for (i=0; i<(dispDeviceRect[3] - dispDeviceRect[1]); i++)
{
unsigned int *ptr = base;
......@@ -305,6 +321,7 @@ void btext_clearscreen(void)
*(ptr++) = 0;
base += (dispDeviceRowBytes >> 2);
}
rmci_maybe_off();
}
void btext_flushscreen(void)
......@@ -355,6 +372,8 @@ static void scrollscreen(void)
(dispDeviceDepth >> 3)) >> 2;
int i,j;
rmci_maybe_on();
for (i=0; i<(dispDeviceRect[3] - dispDeviceRect[1] - 16); i++)
{
unsigned int *src_ptr = src;
......@@ -371,9 +390,116 @@ static void scrollscreen(void)
*(dst_ptr++) = 0;
dst += (dispDeviceRowBytes >> 2);
}
rmci_maybe_off();
}
#endif /* ndef NO_SCROLL */
static unsigned int expand_bits_8[16] = {
0x00000000,
0x000000ff,
0x0000ff00,
0x0000ffff,
0x00ff0000,
0x00ff00ff,
0x00ffff00,
0x00ffffff,
0xff000000,
0xff0000ff,
0xff00ff00,
0xff00ffff,
0xffff0000,
0xffff00ff,
0xffffff00,
0xffffffff
};
static unsigned int expand_bits_16[4] = {
0x00000000,
0x0000ffff,
0xffff0000,
0xffffffff
};
static void draw_byte_32(unsigned char *font, unsigned int *base, int rb)
{
int l, bits;
int fg = 0xFFFFFFFFUL;
int bg = 0x00000000UL;
for (l = 0; l < 16; ++l)
{
bits = *font++;
base[0] = (-(bits >> 7) & fg) ^ bg;
base[1] = (-((bits >> 6) & 1) & fg) ^ bg;
base[2] = (-((bits >> 5) & 1) & fg) ^ bg;
base[3] = (-((bits >> 4) & 1) & fg) ^ bg;
base[4] = (-((bits >> 3) & 1) & fg) ^ bg;
base[5] = (-((bits >> 2) & 1) & fg) ^ bg;
base[6] = (-((bits >> 1) & 1) & fg) ^ bg;
base[7] = (-(bits & 1) & fg) ^ bg;
base = (unsigned int *) ((char *)base + rb);
}
}
static inline void draw_byte_16(unsigned char *font, unsigned int *base, int rb)
{
int l, bits;
int fg = 0xFFFFFFFFUL;
int bg = 0x00000000UL;
unsigned int *eb = (int *)expand_bits_16;
for (l = 0; l < 16; ++l)
{
bits = *font++;
base[0] = (eb[bits >> 6] & fg) ^ bg;
base[1] = (eb[(bits >> 4) & 3] & fg) ^ bg;
base[2] = (eb[(bits >> 2) & 3] & fg) ^ bg;
base[3] = (eb[bits & 3] & fg) ^ bg;
base = (unsigned int *) ((char *)base + rb);
}
}
static inline void draw_byte_8(unsigned char *font, unsigned int *base, int rb)
{
int l, bits;
int fg = 0x0F0F0F0FUL;
int bg = 0x00000000UL;
unsigned int *eb = (int *)expand_bits_8;
for (l = 0; l < 16; ++l)
{
bits = *font++;
base[0] = (eb[bits >> 4] & fg) ^ bg;
base[1] = (eb[bits & 0xf] & fg) ^ bg;
base = (unsigned int *) ((char *)base + rb);
}
}
static noinline void draw_byte(unsigned char c, long locX, long locY)
{
unsigned char *base = calc_base(locX << 3, locY << 4);
unsigned char *font = &vga_font[((unsigned int)c) * 16];
int rb = dispDeviceRowBytes;
rmci_maybe_on();
switch(dispDeviceDepth) {
case 24:
case 32:
draw_byte_32(font, (unsigned int *)base, rb);
break;
case 15:
case 16:
draw_byte_16(font, (unsigned int *)base, rb);
break;
case 8:
draw_byte_8(font, (unsigned int *)base, rb);
break;
}
rmci_maybe_off();
}
void btext_drawchar(char c)
{
int cline = 0;
......@@ -465,107 +591,12 @@ void btext_drawhex(unsigned long v)
btext_drawchar(' ');
}
static void draw_byte(unsigned char c, long locX, long locY)
{
unsigned char *base = calc_base(locX << 3, locY << 4);
unsigned char *font = &vga_font[((unsigned int)c) * 16];
int rb = dispDeviceRowBytes;
switch(dispDeviceDepth) {
case 24:
case 32:
draw_byte_32(font, (unsigned int *)base, rb);
break;
case 15:
case 16:
draw_byte_16(font, (unsigned int *)base, rb);
break;
case 8:
draw_byte_8(font, (unsigned int *)base, rb);
break;
}
}
static unsigned int expand_bits_8[16] = {
0x00000000,
0x000000ff,
0x0000ff00,
0x0000ffff,
0x00ff0000,
0x00ff00ff,
0x00ffff00,
0x00ffffff,
0xff000000,
0xff0000ff,
0xff00ff00,
0xff00ffff,
0xffff0000,
0xffff00ff,
0xffffff00,
0xffffffff
};
static unsigned int expand_bits_16[4] = {
0x00000000,
0x0000ffff,
0xffff0000,
0xffffffff
};
static void draw_byte_32(unsigned char *font, unsigned int *base, int rb)
{
int l, bits;
int fg = 0xFFFFFFFFUL;
int bg = 0x00000000UL;
for (l = 0; l < 16; ++l)
{
bits = *font++;
base[0] = (-(bits >> 7) & fg) ^ bg;
base[1] = (-((bits >> 6) & 1) & fg) ^ bg;
base[2] = (-((bits >> 5) & 1) & fg) ^ bg;
base[3] = (-((bits >> 4) & 1) & fg) ^ bg;
base[4] = (-((bits >> 3) & 1) & fg) ^ bg;
base[5] = (-((bits >> 2) & 1) & fg) ^ bg;
base[6] = (-((bits >> 1) & 1) & fg) ^ bg;
base[7] = (-(bits & 1) & fg) ^ bg;
base = (unsigned int *) ((char *)base + rb);
}
}
static void draw_byte_16(unsigned char *font, unsigned int *base, int rb)
{
int l, bits;
int fg = 0xFFFFFFFFUL;
int bg = 0x00000000UL;
unsigned int *eb = (int *)expand_bits_16;
for (l = 0; l < 16; ++l)
{
bits = *font++;
base[0] = (eb[bits >> 6] & fg) ^ bg;
base[1] = (eb[(bits >> 4) & 3] & fg) ^ bg;
base[2] = (eb[(bits >> 2) & 3] & fg) ^ bg;
base[3] = (eb[bits & 3] & fg) ^ bg;
base = (unsigned int *) ((char *)base + rb);
}
}
static void draw_byte_8(unsigned char *font, unsigned int *base, int rb)
void __init udbg_init_btext(void)
{
int l, bits;
int fg = 0x0F0F0F0FUL;
int bg = 0x00000000UL;
unsigned int *eb = (int *)expand_bits_8;
for (l = 0; l < 16; ++l)
{
bits = *font++;
base[0] = (eb[bits >> 4] & fg) ^ bg;
base[1] = (eb[bits & 0xf] & fg) ^ bg;
base = (unsigned int *) ((char *)base + rb);
}
/* If btext is enabled, we might have a BAT setup for early display,
* thus we do enable some very basic udbg output
*/
udbg_putc = btext_drawchar;
}
static unsigned char vga_font[cmapsz] = {
......@@ -913,10 +944,3 @@ static unsigned char vga_font[cmapsz] = {
0x00, 0x00, 0x00, 0x00,
};
void __init udbg_init_btext(void)
{
/* If btext is enabled, we might have a BAT setup for early display,
* thus we do enable some very basic udbg output
*/
udbg_putc = btext_drawchar;
}
arch/powerpc/kernel/cacheinfo.c
View file @ 39eda2ab
......@@ -196,7 +196,7 @@ static void cache_cpu_set(struct cache *cache, int cpu)
static int cache_size(const struct cache *cache, unsigned int *ret)
{
const char *propname;
const u32 *cache_size;
const __be32 *cache_size;
propname = cache_type_info[cache->type].size_prop;
......@@ -204,7 +204,7 @@ static int cache_size(const struct cache *cache, unsigned int *ret)
if (!cache_size)
return -ENODEV;
*ret = *cache_size;
*ret = of_read_number(cache_size, 1);
return 0;
}
......@@ -222,7 +222,7 @@ static int cache_size_kb(const struct cache *cache, unsigned int *ret)
/* not cache_line_size() because that's a macro in include/linux/cache.h */
static int cache_get_line_size(const struct cache *cache, unsigned int *ret)
{
const u32 *line_size;
const __be32 *line_size;
int i, lim;
lim = ARRAY_SIZE(cache_type_info[cache->type].line_size_props);
......@@ -239,14 +239,14 @@ static int cache_get_line_size(const struct cache *cache, unsigned int *ret)
if (!line_size)
return -ENODEV;
*ret = *line_size;
*ret = of_read_number(line_size, 1);
return 0;
}
static int cache_nr_sets(const struct cache *cache, unsigned int *ret)
{
const char *propname;
const u32 *nr_sets;
const __be32 *nr_sets;
propname = cache_type_info[cache->type].nr_sets_prop;
......@@ -254,7 +254,7 @@ static int cache_nr_sets(const struct cache *cache, unsigned int *ret)
if (!nr_sets)
return -ENODEV;
*ret = *nr_sets;
*ret = of_read_number(nr_sets, 1);
return 0;
}
......
arch/powerpc/kernel/cpu_setup_fsl_booke.S
View file @ 39eda2ab
......@@ -75,7 +75,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
#ifdef CONFIG_FSL_RIO
#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr r3,SPRN_HID1
oris r3,r3,HID1_RFXE@h
......
arch/powerpc/kernel/cputable.c
View file @ 39eda2ab
......@@ -2105,7 +2105,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,
.dcache_bsize = 64,
.num_pmcs = 4,
.num_pmcs = 6,
.oprofile_cpu_type = "ppc/e6500",
.oprofile_type = PPC_OPROFILE_FSL_EMB,
.cpu_setup = __setup_cpu_e6500,
......
arch/powerpc/kernel/entry_64.S
View file @ 39eda2ab
......@@ -102,7 +102,8 @@ BEGIN_FW_FTR_SECTION
/* if from user, see if there are any DTL entries to process */
ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
ld r11,PACA_DTL_RIDX(r13) /* get log read index */
ld r10,LPPACA_DTLIDX(r10) /* get log write index */
addi r10,r10,LPPACA_DTLIDX
LDX_BE r10,0,r10 /* get log write index */
cmpd cr1,r11,r10
beq+ cr1,33f
bl .accumulate_stolen_time
......@@ -522,9 +523,11 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
*/
ld r9,PACA_SLBSHADOWPTR(r13)
li r12,0
std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
li r12,SLBSHADOW_STACKVSID
STDX_BE r7,r12,r9 /* Save VSID */
li r12,SLBSHADOW_STACKESID
STDX_BE r0,r12,r9 /* Save ESID */
/* No need to check for MMU_FTR_NO_SLBIE_B here, since when
* we have 1TB segments, the only CPUs known to have the errata
......@@ -575,34 +578,15 @@ BEGIN_FTR_SECTION
ld r7,DSCR_DEFAULT@toc(2)
ld r0,THREAD_DSCR(r4)
cmpwi r6,0
li r8, FSCR_DSCR
bne 1f
ld r0,0(r7)
b 3f
1:
BEGIN_FTR_SECTION_NESTED(70)
mfspr r6, SPRN_FSCR
or r6, r6, r8
mtspr SPRN_FSCR, r6
BEGIN_FTR_SECTION_NESTED(69)
mfspr r6, SPRN_HFSCR
or r6, r6, r8
mtspr SPRN_HFSCR, r6
END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
b 4f
END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
3:
BEGIN_FTR_SECTION_NESTED(70)
mfspr r6, SPRN_FSCR
andc r6, r6, r8
mtspr SPRN_FSCR, r6
BEGIN_FTR_SECTION_NESTED(69)
mfspr r6, SPRN_HFSCR
andc r6, r6, r8
mtspr SPRN_HFSCR, r6
END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
4: cmpd r0,r25
BEGIN_FTR_SECTION_NESTED(70)
mfspr r8, SPRN_FSCR
rldimi r8, r6, FSCR_DSCR_LG, (63 - FSCR_DSCR_LG)
mtspr SPRN_FSCR, r8
END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
cmpd r0,r25
beq 2f
mtspr SPRN_DSCR,r0
2:
......@@ -737,9 +721,9 @@ resume_kernel:
/*
* Here we are preempting the current task. We want to make
* sure we are soft-disabled first
* sure we are soft-disabled first and reconcile irq state.
*/
SOFT_DISABLE_INTS(r3,r4)
RECONCILE_IRQ_STATE(r3,r4)
1: bl .preempt_schedule_irq
/* Re-test flags and eventually loop */
......
arch/powerpc/kernel/epapr_paravirt.c
View file @ 39eda2ab
......@@ -30,22 +30,20 @@ extern u32 epapr_ev_idle_start[];
bool epapr_paravirt_enabled;
static int __init epapr_paravirt_init(void)
static int __init early_init_dt_scan_epapr(unsigned long node,
const char *uname,
int depth, void *data)
{
struct device_node *hyper_node;
const u32 *insts;
int len, i;
unsigned long len;
int i;
hyper_node = of_find_node_by_path("/hypervisor");
if (!hyper_node)
return -ENODEV;
insts = of_get_property(hyper_node, "hcall-instructions", &len);
insts = of_get_flat_dt_prop(node, "hcall-instructions", &len);
if (!insts)
return -ENODEV;
return 0;
if (len % 4 || len > (4 * 4))
return -ENODEV;
return -1;
for (i = 0; i < (len / 4); i++) {
patch_instruction(epapr_hypercall_start + i, insts[i]);
......@@ -55,13 +53,19 @@ static int __init epapr_paravirt_init(void)
}
#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
if (of_get_property(hyper_node, "has-idle", NULL))
if (of_get_flat_dt_prop(node, "has-idle", NULL))
ppc_md.power_save = epapr_ev_idle;
#endif
epapr_paravirt_enabled = true;
return 1;
}
int __init epapr_paravirt_early_init(void)
{
of_scan_flat_dt(early_init_dt_scan_epapr, NULL);
return 0;
}
early_initcall(epapr_paravirt_init);
arch/powerpc/kernel/exceptions-64e.S
View file @ 39eda2ab
......@@ -198,9 +198,9 @@ exc_##n##_common: \
/* This second version is meant for exceptions that don't immediately
* hard-enable. We set a bit in paca->irq_happened to ensure that
* a subsequent call to arch_local_irq_restore() will properly
* hard-enable and avoid the fast-path
* hard-enable and avoid the fast-path, and then reconcile irq state.
*/
#define INTS_DISABLE SOFT_DISABLE_INTS(r3,r4)
#define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4)
/* This is called by exceptions that used INTS_KEEP (that did not touch
* irq indicators in the PACA). This will restore MSR:EE to it's previous
......
arch/powerpc/kernel/exceptions-64s.S
View file @ 39eda2ab
......@@ -293,27 +293,31 @@ system_call_pSeries:
* out of line to handle them
*/
. = 0xe00
hv_exception_trampoline:
hv_data_storage_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b h_data_storage_hv
. = 0xe20
hv_instr_storage_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b h_instr_storage_hv
. = 0xe40
emulation_assist_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b emulation_assist_hv
. = 0xe60
hv_exception_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b hmi_exception_hv
. = 0xe80
hv_doorbell_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b h_doorbell_hv
......@@ -323,32 +327,32 @@ hv_exception_trampoline:
* prolog code of the PerformanceMonitor one. A little
* trickery is thus necessary
*/
performance_monitor_pSeries_1:
. = 0xf00
performance_monitor_pseries_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b performance_monitor_pSeries
altivec_unavailable_pSeries_1:
. = 0xf20
altivec_unavailable_pseries_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b altivec_unavailable_pSeries
vsx_unavailable_pSeries_1:
. = 0xf40
vsx_unavailable_pseries_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b vsx_unavailable_pSeries
facility_unavailable_trampoline:
. = 0xf60
facility_unavailable_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b facility_unavailable_pSeries
hv_facility_unavailable_trampoline:
. = 0xf80
hv_facility_unavailable_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b facility_unavailable_hv
......@@ -367,11 +371,7 @@ denorm_exception_hv:
HMT_MEDIUM_PPR_DISCARD
mtspr SPRN_SPRG_HSCRATCH0,r13
EXCEPTION_PROLOG_0(PACA_EXGEN)
std r11,PACA_EXGEN+EX_R11(r13)
std r12,PACA_EXGEN+EX_R12(r13)
mfspr r9,SPRN_SPRG_HSCRATCH0
std r9,PACA_EXGEN+EX_R13(r13)
mfcr r9
EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
#ifdef CONFIG_PPC_DENORMALISATION
mfspr r10,SPRN_HSRR1
......@@ -381,6 +381,7 @@ denorm_exception_hv:
bne+ denorm_assist
#endif
KVMTEST(0x1500)
EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x1500)
......@@ -501,6 +502,10 @@ denorm_done:
mtcrf 0x80,r9
ld r9,PACA_EXGEN+EX_R9(r13)
RESTORE_PPR_PACA(PACA_EXGEN, r10)
BEGIN_FTR_SECTION
ld r10,PACA_EXGEN+EX_CFAR(r13)
mtspr SPRN_CFAR,r10
END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
ld r10,PACA_EXGEN+EX_R10(r13)
ld r11,PACA_EXGEN+EX_R11(r13)
ld r12,PACA_EXGEN+EX_R12(r13)
......@@ -808,6 +813,7 @@ system_call_relon_pSeries:
b . /* Can't happen, see v2.07 Book III-S section 6.5 */
. = 0x4e40
emulation_assist_relon_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b emulation_assist_relon_hv
......@@ -816,36 +822,37 @@ system_call_relon_pSeries:
b . /* Can't happen, see v2.07 Book III-S section 6.5 */
. = 0x4e80
h_doorbell_relon_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b h_doorbell_relon_hv
performance_monitor_relon_pSeries_1:
. = 0x4f00
performance_monitor_relon_pseries_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b performance_monitor_relon_pSeries
altivec_unavailable_relon_pSeries_1:
. = 0x4f20
altivec_unavailable_relon_pseries_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b altivec_unavailable_relon_pSeries
vsx_unavailable_relon_pSeries_1:
. = 0x4f40
vsx_unavailable_relon_pseries_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b vsx_unavailable_relon_pSeries
facility_unavailable_relon_trampoline:
. = 0x4f60
facility_unavailable_relon_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b facility_unavailable_relon_pSeries
hv_facility_unavailable_relon_trampoline:
. = 0x4f80
hv_facility_unavailable_relon_trampoline:
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN)
b hv_facility_unavailable_relon_hv
......
arch/powerpc/kernel/head_40x.S
View file @ 39eda2ab
......@@ -822,14 +822,6 @@ finish_tlb_load:
rfi /* Should sync shadow TLBs */
b . /* prevent prefetch past rfi */
/* extern void giveup_fpu(struct task_struct *prev)
*
* The PowerPC 4xx family of processors do not have an FPU, so this just
* returns.
*/
_ENTRY(giveup_fpu)
blr
/* This is where the main kernel code starts.
*/
start_here:
......
arch/powerpc/kernel/head_44x.S
View file @ 39eda2ab
......@@ -784,16 +784,6 @@ _GLOBAL(__fixup_440A_mcheck)
sync
blr
/*
* extern void giveup_fpu(struct task_struct *prev)
*
* The 44x core does not have an FPU.
*/
#ifndef CONFIG_PPC_FPU
_GLOBAL(giveup_fpu)
blr
#endif
_GLOBAL(set_context)
#ifdef CONFIG_BDI_SWITCH
......
arch/powerpc/kernel/head_64.S
View file @ 39eda2ab
......@@ -703,6 +703,7 @@ _GLOBAL(relative_toc)
mtlr r0
blr
.balign 8
p_toc: .llong __toc_start + 0x8000 - 0b
/*
......
arch/powerpc/kernel/head_8xx.S
View file @ 39eda2ab
......@@ -691,10 +691,6 @@ modified_instr:
b 151b
#endif
.globl giveup_fpu
giveup_fpu:
blr
/*
* This is where the main kernel code starts.
*/
......
arch/powerpc/kernel/head_fsl_booke.S
View file @ 39eda2ab
......@@ -947,16 +947,6 @@ _GLOBAL(giveup_spe)
blr
#endif /* CONFIG_SPE */
/*
* extern void giveup_fpu(struct task_struct *prev)
*
* Not all FSL Book-E cores have an FPU
*/
#ifndef CONFIG_PPC_FPU
_GLOBAL(giveup_fpu)
blr
#endif
/*
* extern void abort(void)
*
......
arch/powerpc/kernel/io-workarounds.c
View file @ 39eda2ab
......@@ -53,6 +53,7 @@ static struct iowa_bus *iowa_pci_find(unsigned long vaddr, unsigned long paddr)
return NULL;
}
#ifdef CONFIG_PPC_INDIRECT_MMIO
struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
{
unsigned hugepage_shift;
......@@ -90,13 +91,25 @@ struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
return bus;
}
#else /* CONFIG_PPC_INDIRECT_MMIO */
struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
{
return NULL;
}
#endif /* !CONFIG_PPC_INDIRECT_MMIO */
#ifdef CONFIG_PPC_INDIRECT_PIO
struct iowa_bus *iowa_pio_find_bus(unsigned long port)
{
unsigned long vaddr = (unsigned long)pci_io_base + port;
return iowa_pci_find(vaddr, 0);
}
#else
struct iowa_bus *iowa_pio_find_bus(unsigned long port)
{
return NULL;
}
#endif
#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
static ret iowa_##name at \
......@@ -137,6 +150,7 @@ static const struct ppc_pci_io iowa_pci_io = {
};
#ifdef CONFIG_PPC_INDIRECT_MMIO
static void __iomem *iowa_ioremap(phys_addr_t addr, unsigned long size,
unsigned long flags, void *caller)
{
......@@ -151,6 +165,9 @@ static void __iomem *iowa_ioremap(phys_addr_t addr, unsigned long size,
}
return res;
}
#else /* CONFIG_PPC_INDIRECT_MMIO */
#define iowa_ioremap NULL
#endif /* !CONFIG_PPC_INDIRECT_MMIO */
/* Enable IO workaround */
static void io_workaround_init(void)
......
arch/powerpc/kernel/io.c
View file @ 39eda2ab
......@@ -25,6 +25,9 @@
#include <asm/firmware.h>
#include <asm/bug.h>
/* See definition in io.h */
bool isa_io_special;
void _insb(const volatile u8 __iomem *port, void *buf, long count)
{
u8 *tbuf = buf;
......
arch/powerpc/kernel/legacy_serial.c
View file @ 39eda2ab
......@@ -99,7 +99,7 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
legacy_serial_count = index + 1;
/* Check if there is a port who already claimed our slot */
if (legacy_serial_infos[index].np != 0) {
if (legacy_serial_infos[index].np != NULL) {
/* if we still have some room, move it, else override */
if (legacy_serial_count < MAX_LEGACY_SERIAL_PORTS) {
printk(KERN_DEBUG "Moved legacy port %d -> %d\n",
......@@ -152,7 +152,7 @@ static int __init add_legacy_soc_port(struct device_node *np,
struct device_node *soc_dev)
{
u64 addr;
const u32 *addrp;
const __be32 *addrp;
upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ
| UPF_FIXED_PORT;
struct device_node *tsi = of_get_parent(np);
......@@ -221,14 +221,19 @@ static int __init add_legacy_isa_port(struct device_node *np,
/* Translate ISA address. If it fails, we still register the port
* with no translated address so that it can be picked up as an IO
* port later by the serial driver
*
* Note: Don't even try on P8 lpc, we know it's not directly mapped
*/
taddr = of_translate_address(np, reg);
if (taddr == OF_BAD_ADDR)
if (!of_device_is_compatible(isa_brg, "ibm,power8-lpc")) {
taddr = of_translate_address(np, reg);
if (taddr == OF_BAD_ADDR)
taddr = 0;
} else
taddr = 0;
/* Add port, irq will be dealt with later */
return add_legacy_port(np, index, UPIO_PORT, be32_to_cpu(reg[1]), taddr,
NO_IRQ, UPF_BOOT_AUTOCONF, 0);
return add_legacy_port(np, index, UPIO_PORT, be32_to_cpu(reg[1]),
taddr, NO_IRQ, UPF_BOOT_AUTOCONF, 0);
}
......@@ -237,7 +242,7 @@ static int __init add_legacy_pci_port(struct device_node *np,
struct device_node *pci_dev)
{
u64 addr, base;
const u32 *addrp;
const __be32 *addrp;
unsigned int flags;
int iotype, index = -1, lindex = 0;
......@@ -270,7 +275,7 @@ static int __init add_legacy_pci_port(struct device_node *np,
if (iotype == UPIO_MEM)
base = addr;
else
base = addrp[2];
base = of_read_number(&addrp[2], 1);
/* Try to guess an index... If we have subdevices of the pci dev,
* we get to their "reg" property
......@@ -307,19 +312,31 @@ static int __init add_legacy_pci_port(struct device_node *np,
static void __init setup_legacy_serial_console(int console)
{
struct legacy_serial_info *info =
&legacy_serial_infos[console];
struct legacy_serial_info *info = &legacy_serial_infos[console];
struct plat_serial8250_port *port = &legacy_serial_ports[console];
void __iomem *addr;
if (info->taddr == 0)
return;
addr = ioremap(info->taddr, 0x1000);
if (addr == NULL)
return;
/* Check if a translated MMIO address has been found */
if (info->taddr) {
addr = ioremap(info->taddr, 0x1000);
if (addr == NULL)
return;
udbg_uart_init_mmio(addr, 1);
} else {
/* Check if it's PIO and we support untranslated PIO */
if (port->iotype == UPIO_PORT && isa_io_special)
udbg_uart_init_pio(port->iobase, 1);
else
return;
}
/* Try to query the current speed */
if (info->speed == 0)
info->speed = udbg_probe_uart_speed(addr, info->clock);
info->speed = udbg_probe_uart_speed(info->clock);
/* Set it up */
DBG("default console speed = %d\n", info->speed);
udbg_init_uart(addr, info->speed, info->clock);
udbg_uart_setup(info->speed, info->clock);
}
/*
......@@ -367,10 +384,13 @@ void __init find_legacy_serial_ports(void)
/* Next, fill our array with ISA ports */
for_each_node_by_type(np, "serial") {
struct device_node *isa = of_get_parent(np);
if (isa && !strcmp(isa->name, "isa")) {
index = add_legacy_isa_port(np, isa);
if (index >= 0 && np == stdout)
legacy_serial_console = index;
if (isa && (!strcmp(isa->name, "isa") ||
!strcmp(isa->name, "lpc"))) {
if (of_device_is_available(np)) {
index = add_legacy_isa_port(np, isa);
if (index >= 0 && np == stdout)
legacy_serial_console = index;
}
}
of_node_put(isa);
}
......
arch/powerpc/kernel/misc_32.S
View file @ 39eda2ab
......@@ -327,8 +327,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
*
* flush_icache_range(unsigned long start, unsigned long stop)
*/
_KPROBE(__flush_icache_range)
_KPROBE(flush_icache_range)
BEGIN_FTR_SECTION
isync
blr /* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
li r5,L1_CACHE_BYTES-1
......
arch/powerpc/kernel/misc_64.S
View file @ 39eda2ab
......@@ -67,8 +67,10 @@ PPC64_CACHES:
* flush all bytes from start through stop-1 inclusive
*/
_KPROBE(__flush_icache_range)
_KPROBE(flush_icache_range)
BEGIN_FTR_SECTION
blr
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
/*
* Flush the data cache to memory
*
......@@ -247,6 +249,37 @@ _GLOBAL(__bswapdi2)
blr
#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
_GLOBAL(rmci_on)
sync
isync
li r3,0x100
rldicl r3,r3,32,0
mfspr r5,SPRN_HID4
or r5,r5,r3
sync
mtspr SPRN_HID4,r5
isync
slbia
isync
sync
blr
_GLOBAL(rmci_off)
sync
isync
li r3,0x100
rldicl r3,r3,32,0
mfspr r5,SPRN_HID4
andc r5,r5,r3
sync
mtspr SPRN_HID4,r5
isync
slbia
isync
sync
blr
/*
* Do an IO access in real mode
*/
......@@ -416,19 +449,6 @@ _GLOBAL(scom970_write)
blr
#endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
/*
* disable_kernel_fp()
* Disable the FPU.
*/
_GLOBAL(disable_kernel_fp)
mfmsr r3
rldicl r0,r3,(63-MSR_FP_LG),1
rldicl r3,r0,(MSR_FP_LG+1),0
mtmsrd r3 /* disable use of fpu now */
isync
blr
/* kexec_wait(phys_cpu)
*
* wait for the flag to change, indicating this kernel is going away but
......
arch/powerpc/kernel/paca.c
View file @ 39eda2ab
......@@ -34,10 +34,10 @@ extern unsigned long __toc_start;
*/
struct lppaca lppaca[] = {
[0 ... (NR_LPPACAS-1)] = {
.desc = 0xd397d781, /* "LpPa" */
.size = sizeof(struct lppaca),
.desc = cpu_to_be32(0xd397d781), /* "LpPa" */
.size = cpu_to_be16(sizeof(struct lppaca)),
.fpregs_in_use = 1,
.slb_count = 64,
.slb_count = cpu_to_be16(64),
.vmxregs_in_use = 0,
.page_ins = 0,
},
......@@ -101,8 +101,8 @@ static inline void free_lppacas(void) { }
*/
struct slb_shadow slb_shadow[] __cacheline_aligned = {
[0 ... (NR_CPUS-1)] = {
.persistent = SLB_NUM_BOLTED,
.buffer_length = sizeof(struct slb_shadow),
.persistent = cpu_to_be32(SLB_NUM_BOLTED),
.buffer_length = cpu_to_be32(sizeof(struct slb_shadow)),
},
};
......
arch/powerpc/kernel/pci-common.c
View file @ 39eda2ab
......@@ -306,7 +306,7 @@ static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
unsigned long io_offset = 0;
int i, res_bit;
if (hose == 0)
if (hose == NULL)
return NULL; /* should never happen */
/* If memory, add on the PCI bridge address offset */
......@@ -667,7 +667,7 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
void pci_process_bridge_OF_ranges(struct pci_controller *hose,
struct device_node *dev, int primary)
{
const u32 *ranges;
const __be32 *ranges;
int rlen;
int pna = of_n_addr_cells(dev);
int np = pna + 5;
......@@ -687,7 +687,7 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
/* Parse it */
while ((rlen -= np * 4) >= 0) {
/* Read next ranges element */
pci_space = ranges[0];
pci_space = of_read_number(ranges, 1);
pci_addr = of_read_number(ranges + 1, 2);
cpu_addr = of_translate_address(dev, ranges + 3);
size = of_read_number(ranges + pna + 3, 2);
......@@ -704,7 +704,7 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
/* Now consume following elements while they are contiguous */
for (; rlen >= np * sizeof(u32);
ranges += np, rlen -= np * 4) {
if (ranges[0] != pci_space)
if (of_read_number(ranges, 1) != pci_space)
break;
pci_next = of_read_number(ranges + 1, 2);
cpu_next = of_translate_address(dev, ranges + 3);
......@@ -1055,8 +1055,7 @@ void pcibios_fixup_bus(struct pci_bus *bus)
* bases. This is -not- called when generating the PCI tree from
* the OF device-tree.
*/
if (bus->self != NULL)
pci_read_bridge_bases(bus);
pci_read_bridge_bases(bus);
/* Now fixup the bus bus */
pcibios_setup_bus_self(bus);
......@@ -1578,7 +1577,7 @@ fake_pci_bus(struct pci_controller *hose, int busnr)
{
static struct pci_bus bus;
if (hose == 0) {
if (hose == NULL) {
printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
}
bus.number = busnr;
......
arch/powerpc/kernel/pci_64.c
View file @ 39eda2ab
......@@ -109,7 +109,7 @@ int pcibios_unmap_io_space(struct pci_bus *bus)
hose = pci_bus_to_host(bus);
/* Check if we have IOs allocated */
if (hose->io_base_alloc == 0)
if (hose->io_base_alloc == NULL)
return 0;
pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
......@@ -272,7 +272,7 @@ static void quirk_radeon_32bit_msi(struct pci_dev *dev)
struct pci_dn *pdn = pci_get_pdn(dev);
if (pdn)
pdn->force_32bit_msi = 1;
pdn->force_32bit_msi = true;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon_32bit_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon_32bit_msi);
arch/powerpc/kernel/pci_dn.c
View file @ 39eda2ab
......@@ -47,9 +47,8 @@ struct pci_dn *pci_get_pdn(struct pci_dev *pdev)
void *update_dn_pci_info(struct device_node *dn, void *data)
{
struct pci_controller *phb = data;
const int *type =
of_get_property(dn, "ibm,pci-config-space-type", NULL);
const u32 *regs;
const __be32 *type = of_get_property(dn, "ibm,pci-config-space-type", NULL);
const __be32 *regs;
struct pci_dn *pdn;
pdn = zalloc_maybe_bootmem(sizeof(*pdn), GFP_KERNEL);
......@@ -63,12 +62,14 @@ void *update_dn_pci_info(struct device_node *dn, void *data)
#endif
regs = of_get_property(dn, "reg", NULL);
if (regs) {
u32 addr = of_read_number(regs, 1);
/* First register entry is addr (00BBSS00) */
pdn->busno = (regs[0] >> 16) & 0xff;
pdn->devfn = (regs[0] >> 8) & 0xff;
pdn->busno = (addr >> 16) & 0xff;
pdn->devfn = (addr >> 8) & 0xff;
}
pdn->pci_ext_config_space = (type && *type == 1);
pdn->pci_ext_config_space = (type && of_read_number(type, 1) == 1);
return NULL;
}
......@@ -98,12 +99,13 @@ void *traverse_pci_devices(struct device_node *start, traverse_func pre,
/* We started with a phb, iterate all childs */
for (dn = start->child; dn; dn = nextdn) {
const u32 *classp;
u32 class;
const __be32 *classp;
u32 class = 0;
nextdn = NULL;
classp = of_get_property(dn, "class-code", NULL);
class = classp ? *classp : 0;
if (classp)
class = of_read_number(classp, 1);
if (pre && ((ret = pre(dn, data)) != NULL))
return ret;
......
arch/powerpc/kernel/pci_of_scan.c
View file @ 39eda2ab
......@@ -24,12 +24,12 @@
*/
static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
{
const u32 *prop;
const __be32 *prop;
int len;
prop = of_get_property(np, name, &len);
if (prop && len >= 4)
return *prop;
return of_read_number(prop, 1);
return def;
}
......@@ -77,7 +77,7 @@ static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
unsigned int flags;
struct pci_bus_region region;
struct resource *res;
const u32 *addrs;
const __be32 *addrs;
u32 i;
int proplen;
......@@ -86,14 +86,14 @@ static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
return;
pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
for (; proplen >= 20; proplen -= 20, addrs += 5) {
flags = pci_parse_of_flags(addrs[0], 0);
flags = pci_parse_of_flags(of_read_number(addrs, 1), 0);
if (!flags)
continue;
base = of_read_number(&addrs[1], 2);
size = of_read_number(&addrs[3], 2);
if (!size)
continue;
i = addrs[0] & 0xff;
i = of_read_number(addrs, 1) & 0xff;
pr_debug(" base: %llx, size: %llx, i: %x\n",
(unsigned long long)base,
(unsigned long long)size, i);
......@@ -207,7 +207,7 @@ void of_scan_pci_bridge(struct pci_dev *dev)
{
struct device_node *node = dev->dev.of_node;
struct pci_bus *bus;
const u32 *busrange, *ranges;
const __be32 *busrange, *ranges;
int len, i, mode;
struct pci_bus_region region;
struct resource *res;
......@@ -230,9 +230,11 @@ void of_scan_pci_bridge(struct pci_dev *dev)
return;
}
bus = pci_find_bus(pci_domain_nr(dev->bus), busrange[0]);
bus = pci_find_bus(pci_domain_nr(dev->bus),
of_read_number(busrange, 1));
if (!bus) {
bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
bus = pci_add_new_bus(dev->bus, dev,
of_read_number(busrange, 1));
if (!bus) {
printk(KERN_ERR "Failed to create pci bus for %s\n",
node->full_name);
......@@ -241,7 +243,8 @@ void of_scan_pci_bridge(struct pci_dev *dev)
}
bus->primary = dev->bus->number;
pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
pci_bus_insert_busn_res(bus, of_read_number(busrange, 1),
of_read_number(busrange+1, 1));
bus->bridge_ctl = 0;
/* parse ranges property */
......@@ -254,7 +257,7 @@ void of_scan_pci_bridge(struct pci_dev *dev)
}
i = 1;
for (; len >= 32; len -= 32, ranges += 8) {
flags = pci_parse_of_flags(ranges[0], 1);
flags = pci_parse_of_flags(of_read_number(ranges, 1), 1);
size = of_read_number(&ranges[6], 2);
if (flags == 0 || size == 0)
continue;
......
arch/powerpc/kernel/ppc_ksyms.c
View file @ 39eda2ab
......@@ -96,7 +96,9 @@ EXPORT_SYMBOL(pci_dram_offset);
EXPORT_SYMBOL(start_thread);
#ifdef CONFIG_PPC_FPU
EXPORT_SYMBOL(giveup_fpu);
#endif
#ifdef CONFIG_ALTIVEC
EXPORT_SYMBOL(giveup_altivec);
#endif /* CONFIG_ALTIVEC */
......@@ -111,7 +113,6 @@ EXPORT_SYMBOL(giveup_spe);
#ifndef CONFIG_PPC64
EXPORT_SYMBOL(flush_instruction_cache);
#endif
EXPORT_SYMBOL(__flush_icache_range);
EXPORT_SYMBOL(flush_dcache_range);
#ifdef CONFIG_SMP
......
arch/powerpc/kernel/process.c
View file @ 39eda2ab
......@@ -74,6 +74,7 @@ struct task_struct *last_task_used_vsx = NULL;
struct task_struct *last_task_used_spe = NULL;
#endif
#ifdef CONFIG_PPC_FPU
/*
* Make sure the floating-point register state in the
* the thread_struct is up to date for task tsk.
......@@ -107,6 +108,7 @@ void flush_fp_to_thread(struct task_struct *tsk)
}
}
EXPORT_SYMBOL_GPL(flush_fp_to_thread);
#endif
void enable_kernel_fp(void)
{
......
arch/powerpc/kernel/prom.c
View file @ 39eda2ab
......@@ -215,16 +215,16 @@ static void __init check_cpu_pa_features(unsigned long node)
#ifdef CONFIG_PPC_STD_MMU_64
static void __init check_cpu_slb_size(unsigned long node)
{
u32 *slb_size_ptr;
__be32 *slb_size_ptr;
slb_size_ptr = of_get_flat_dt_prop(node, "slb-size", NULL);
if (slb_size_ptr != NULL) {
mmu_slb_size = *slb_size_ptr;
mmu_slb_size = be32_to_cpup(slb_size_ptr);
return;
}
slb_size_ptr = of_get_flat_dt_prop(node, "ibm,slb-size", NULL);
if (slb_size_ptr != NULL) {
mmu_slb_size = *slb_size_ptr;
mmu_slb_size = be32_to_cpup(slb_size_ptr);
}
}
#else
......@@ -279,11 +279,11 @@ static void __init check_cpu_feature_properties(unsigned long node)
{
unsigned long i;
struct feature_property *fp = feature_properties;
const u32 *prop;
const __be32 *prop;
for (i = 0; i < ARRAY_SIZE(feature_properties); ++i, ++fp) {
prop = of_get_flat_dt_prop(node, fp->name, NULL);
if (prop && *prop >= fp->min_value) {
if (prop && be32_to_cpup(prop) >= fp->min_value) {
cur_cpu_spec->cpu_features |= fp->cpu_feature;
cur_cpu_spec->cpu_user_features |= fp->cpu_user_ftr;
}
......@@ -295,8 +295,8 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
void *data)
{
char *type = of_get_flat_dt_prop(node, "device_type", NULL);
const u32 *prop;
const u32 *intserv;
const __be32 *prop;
const __be32 *intserv;
int i, nthreads;
unsigned long len;
int found = -1;
......@@ -324,8 +324,9 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
* version 2 of the kexec param format adds the phys cpuid of
* booted proc.
*/
if (initial_boot_params->version >= 2) {
if (intserv[i] == initial_boot_params->boot_cpuid_phys) {
if (be32_to_cpu(initial_boot_params->version) >= 2) {
if (be32_to_cpu(intserv[i]) ==
be32_to_cpu(initial_boot_params->boot_cpuid_phys)) {
found = boot_cpu_count;
found_thread = i;
}
......@@ -347,9 +348,10 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
if (found >= 0) {
DBG("boot cpu: logical %d physical %d\n", found,
intserv[found_thread]);
be32_to_cpu(intserv[found_thread]));
boot_cpuid = found;
set_hard_smp_processor_id(found, intserv[found_thread]);
set_hard_smp_processor_id(found,
be32_to_cpu(intserv[found_thread]));
/*
* PAPR defines "logical" PVR values for cpus that
......@@ -366,8 +368,8 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
* it uses 0x0f000001.
*/
prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
if (prop && (*prop & 0xff000000) == 0x0f000000)
identify_cpu(0, *prop);
if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000)
identify_cpu(0, be32_to_cpup(prop));
identical_pvr_fixup(node);
}
......@@ -389,7 +391,7 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
int __init early_init_dt_scan_chosen_ppc(unsigned long node, const char *uname,
int depth, void *data)
{
unsigned long *lprop;
unsigned long *lprop; /* All these set by kernel, so no need to convert endian */
/* Use common scan routine to determine if this is the chosen node */
if (early_init_dt_scan_chosen(node, uname, depth, data) == 0)
......@@ -454,7 +456,7 @@ static int __init early_init_dt_scan_drconf_memory(unsigned long node)
if (dm == NULL || l < sizeof(__be32))
return 0;
n = *dm++; /* number of entries */
n = of_read_number(dm++, 1); /* number of entries */
if (l < (n * (dt_root_addr_cells + 4) + 1) * sizeof(__be32))
return 0;
......@@ -466,7 +468,7 @@ static int __init early_init_dt_scan_drconf_memory(unsigned long node)
for (; n != 0; --n) {
base = dt_mem_next_cell(dt_root_addr_cells, &dm);
flags = dm[3];
flags = of_read_number(&dm[3], 1);
/* skip DRC index, pad, assoc. list index, flags */
dm += 4;
/* skip this block if the reserved bit is set in flags (0x80)
......@@ -591,16 +593,16 @@ static void __init early_reserve_mem_dt(void)
static void __init early_reserve_mem(void)
{
u64 base, size;
u64 *reserve_map;
__be64 *reserve_map;
unsigned long self_base;
unsigned long self_size;
reserve_map = (u64 *)(((unsigned long)initial_boot_params) +
initial_boot_params->off_mem_rsvmap);
reserve_map = (__be64 *)(((unsigned long)initial_boot_params) +
be32_to_cpu(initial_boot_params->off_mem_rsvmap));
/* before we do anything, lets reserve the dt blob */
self_base = __pa((unsigned long)initial_boot_params);
self_size = initial_boot_params->totalsize;
self_size = be32_to_cpu(initial_boot_params->totalsize);
memblock_reserve(self_base, self_size);
/* Look for the new "reserved-regions" property in the DT */
......@@ -620,15 +622,15 @@ static void __init early_reserve_mem(void)
* Handle the case where we might be booting from an old kexec
* image that setup the mem_rsvmap as pairs of 32-bit values
*/
if (*reserve_map > 0xffffffffull) {
if (be64_to_cpup(reserve_map) > 0xffffffffull) {
u32 base_32, size_32;
u32 *reserve_map_32 = (u32 *)reserve_map;
__be32 *reserve_map_32 = (__be32 *)reserve_map;
DBG("Found old 32-bit reserve map\n");
while (1) {
base_32 = *(reserve_map_32++);
size_32 = *(reserve_map_32++);
base_32 = be32_to_cpup(reserve_map_32++);
size_32 = be32_to_cpup(reserve_map_32++);
if (size_32 == 0)
break;
/* skip if the reservation is for the blob */
......@@ -644,8 +646,8 @@ static void __init early_reserve_mem(void)
/* Handle the reserve map in the fdt blob if it exists */
while (1) {
base = *(reserve_map++);
size = *(reserve_map++);
base = be64_to_cpup(reserve_map++);
size = be64_to_cpup(reserve_map++);
if (size == 0)
break;
DBG("reserving: %llx -> %llx\n", base, size);
......@@ -795,6 +797,32 @@ struct device_node *of_find_next_cache_node(struct device_node *np)
return NULL;
}
/**
* of_get_ibm_chip_id - Returns the IBM "chip-id" of a device
* @np: device node of the device
*
* This looks for a property "ibm,chip-id" in the node or any
* of its parents and returns its content, or -1 if it cannot
* be found.
*/
int of_get_ibm_chip_id(struct device_node *np)
{
of_node_get(np);
while(np) {
struct device_node *old = np;
const __be32 *prop;
prop = of_get_property(np, "ibm,chip-id", NULL);
if (prop) {
of_node_put(np);
return be32_to_cpup(prop);
}
np = of_get_parent(np);
of_node_put(old);
}
return -1;
}
#ifdef CONFIG_PPC_PSERIES
/*
* Fix up the uninitialized fields in a new device node:
......@@ -878,7 +906,7 @@ static int __init export_flat_device_tree(void)
struct dentry *d;
flat_dt_blob.data = initial_boot_params;
flat_dt_blob.size = initial_boot_params->totalsize;
flat_dt_blob.size = be32_to_cpu(initial_boot_params->totalsize);
d = debugfs_create_blob("flat-device-tree", S_IFREG | S_IRUSR,
powerpc_debugfs_root, &flat_dt_blob);
......
arch/powerpc/kernel/prom_init.c
View file @ 39eda2ab
This diff is collapsed.
arch/powerpc/kernel/prom_init_check.sh
View file @ 39eda2ab
......@@ -22,7 +22,8 @@ __secondary_hold_acknowledge __secondary_hold_spinloop __start
strcmp strcpy strlcpy strlen strncmp strstr logo_linux_clut224
reloc_got2 kernstart_addr memstart_addr linux_banner _stext
opal_query_takeover opal_do_takeover opal_enter_rtas opal_secondary_entry
boot_command_line __prom_init_toc_start __prom_init_toc_end"
boot_command_line __prom_init_toc_start __prom_init_toc_end
btext_setup_display"
NM="$1"
OBJ="$2"
......
arch/powerpc/kernel/prom_parse.c
View file @ 39eda2ab
......@@ -7,28 +7,27 @@
#include <linux/of_address.h>
#include <asm/prom.h>
void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
unsigned long *busno, unsigned long *phys, unsigned long *size)
void of_parse_dma_window(struct device_node *dn, const __be32 *dma_window,
unsigned long *busno, unsigned long *phys,
unsigned long *size)
{
const u32 *dma_window;
u32 cells;
const unsigned char *prop;
dma_window = dma_window_prop;
const __be32 *prop;
/* busno is always one cell */
*busno = *(dma_window++);
*busno = of_read_number(dma_window, 1);
dma_window++;
prop = of_get_property(dn, "ibm,#dma-address-cells", NULL);
if (!prop)
prop = of_get_property(dn, "#address-cells", NULL);
cells = prop ? *(u32 *)prop : of_n_addr_cells(dn);
cells = prop ? of_read_number(prop, 1) : of_n_addr_cells(dn);
*phys = of_read_number(dma_window, cells);
dma_window += cells;
prop = of_get_property(dn, "ibm,#dma-size-cells", NULL);
cells = prop ? *(u32 *)prop : of_n_size_cells(dn);
cells = prop ? of_read_number(prop, 1) : of_n_size_cells(dn);
*size = of_read_number(dma_window, cells);
}
arch/powerpc/kernel/rtas.c
View file @ 39eda2ab
This diff is collapsed.
arch/powerpc/kernel/setup-common.c
View file @ 39eda2ab
......@@ -436,7 +436,8 @@ void __init smp_setup_cpu_maps(void)
DBG("smp_setup_cpu_maps()\n");
while ((dn = of_find_node_by_type(dn, "cpu")) && cpu < nr_cpu_ids) {
const int *intserv;
const __be32 *intserv;
__be32 cpu_be;
int j, len;
DBG(" * %s...\n", dn->full_name);
......@@ -450,15 +451,17 @@ void __init smp_setup_cpu_maps(void)
} else {
DBG(" no ibm,ppc-interrupt-server#s -> 1 thread\n");
intserv = of_get_property(dn, "reg", NULL);
if (!intserv)
intserv = &cpu; /* assume logical == phys */
if (!intserv) {
cpu_be = cpu_to_be32(cpu);
intserv = &cpu_be; /* assume logical == phys */
}
}
for (j = 0; j < nthreads && cpu < nr_cpu_ids; j++) {
DBG(" thread %d -> cpu %d (hard id %d)\n",
j, cpu, intserv[j]);
j, cpu, be32_to_cpu(intserv[j]));
set_cpu_present(cpu, true);
set_hard_smp_processor_id(cpu, intserv[j]);
set_hard_smp_processor_id(cpu, be32_to_cpu(intserv[j]));
set_cpu_possible(cpu, true);
cpu++;
}
......
arch/powerpc/kernel/setup_32.c
View file @ 39eda2ab
......@@ -38,6 +38,7 @@
#include <asm/serial.h>
#include <asm/udbg.h>
#include <asm/mmu_context.h>
#include <asm/epapr_hcalls.h>
#include "setup.h"
......@@ -128,6 +129,8 @@ notrace void __init machine_init(u64 dt_ptr)
/* Do some early initialization based on the flat device tree */
early_init_devtree(__va(dt_ptr));
epapr_paravirt_early_init();
early_init_mmu();
probe_machine();
......@@ -326,5 +329,4 @@ void __init setup_arch(char **cmdline_p)
/* Initialize the MMU context management stuff */
mmu_context_init();
}
arch/powerpc/kernel/setup_64.c
View file @ 39eda2ab
This diff is collapsed.
arch/powerpc/kernel/signal_32.c
View file @ 39eda2ab
......@@ -436,7 +436,10 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
* use altivec. Since VSCR only contains 32 bits saved in the least
* significant bits of a vector, we "cheat" and stuff VRSAVE in the
* most significant bits of that same vector. --BenH
* Note that the current VRSAVE value is in the SPR at this point.
*/
if (cpu_has_feature(CPU_FTR_ALTIVEC))
current->thread.vrsave = mfspr(SPRN_VRSAVE);
if (__put_user(current->thread.vrsave, (u32 __user *)&frame->mc_vregs[32]))
return 1;
#endif /* CONFIG_ALTIVEC */
......@@ -557,6 +560,8 @@ static int save_tm_user_regs(struct pt_regs *regs,
* significant bits of a vector, we "cheat" and stuff VRSAVE in the
* most significant bits of that same vector. --BenH
*/
if (cpu_has_feature(CPU_FTR_ALTIVEC))
current->thread.vrsave = mfspr(SPRN_VRSAVE);
if (__put_user(current->thread.vrsave,
(u32 __user *)&frame->mc_vregs[32]))
return 1;
......@@ -696,6 +701,8 @@ static long restore_user_regs(struct pt_regs *regs,
/* Always get VRSAVE back */
if (__get_user(current->thread.vrsave, (u32 __user *)&sr->mc_vregs[32]))
return 1;
if (cpu_has_feature(CPU_FTR_ALTIVEC))
mtspr(SPRN_VRSAVE, current->thread.vrsave);
#endif /* CONFIG_ALTIVEC */
if (copy_fpr_from_user(current, &sr->mc_fregs))
return 1;
......@@ -809,6 +816,8 @@ static long restore_tm_user_regs(struct pt_regs *regs,
__get_user(current->thread.transact_vrsave,
(u32 __user *)&tm_sr->mc_vregs[32]))
return 1;
if (cpu_has_feature(CPU_FTR_ALTIVEC))
mtspr(SPRN_VRSAVE, current->thread.vrsave);
#endif /* CONFIG_ALTIVEC */
regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1);
......
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