Merge bk://gkernel.bkbits.net/net-drivers-2.6

into ppc970.osdl.org:/home/torvalds/v2.6/linux

Documentation/fb/pxafb.txt

+Driver for PXA25x LCD controller
+================================
+
+The driver supports the following options, either via
+options=<OPTIONS> when modular or video=pxafb:<OPTIONS> when built in.
+
+For example:
+	modprobe pxafb options=mode:640x480-8,passive
+or on the kernel command line
+	video=pxafb:mode:640x480-8,passive
+
+mode:XRESxYRES[-BPP]
+	XRES == LCCR1_PPL + 1
+	YRES == LLCR2_LPP + 1
+		The resolution of the display in pixels
+	BPP == The bit depth. Valid values are 1, 2, 4, 8 and 16.
+
+pixclock:PIXCLOCK
+	Pixel clock in picoseconds
+
+left:LEFT == LCCR1_BLW + 1
+right:RIGHT == LCCR1_ELW + 1
+hsynclen:HSYNC == LCCR1_HSW + 1
+upper:UPPER == LCCR2_BFW
+lower:LOWER == LCCR2_EFR
+vsynclen:VSYNC == LCCR2_VSW + 1
+	Display margins and sync times
+
+color | mono => LCCR0_CMS
+	umm...
+
+active | passive => LCCR0_PAS
+	Active (TFT) or Passive (STN) display
+
+single | dual => LCCR0_SDS
+	Single or dual panel passive display
+
+4pix | 8pix => LCCR0_DPD
+	4 or 8 pixel monochrome single panel data
+
+hsync:HSYNC
+vsync:VSYNC
+	Horizontal and vertical sync. 0 => active low, 1 => active
+	high.
+
+dpc:DPC
+	Double pixel clock. 1=>true, 0=>false
+
+outputen:POLARITY
+	Output Enable Polarity. 0 => active low, 1 => active high
+
+pixclockpol:POLARITY
+	pixel clock polarity
+	0 => falling edge, 1 => rising edge

arch/alpha/kernel/module.c

@@ -234,6 +234,10 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab,
 			   value was resolved from somewhere else.  */
 			if (sym->st_shndx == SHN_UNDEF)
 				goto reloc_overflow;
+			if ((sym->st_other & STO_ALPHA_STD_GPLOAD) ==
+			    STO_ALPHA_STD_GPLOAD)
+				/* Omit the prologue. */
+				value += 8;
 			/* FALLTHRU */
 		case R_ALPHA_BRADDR:
 			value -= (u64)location + 4;

arch/arm/Kconfig

@@ -111,6 +111,9 @@ config ARCH_INTEGRATOR
 config ARCH_IOP3XX
 	bool "IOP3xx-based"
 
+config ARCH_IXP4XX
+	bool "IXP4xx-based"
+
 config ARCH_L7200
 	bool "LinkUp-L7200"
 	help
@@ -170,6 +173,8 @@ source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-iop3xx/Kconfig"
 
+source "arch/arm/mach-ixp4xx/Kconfig"
+
 source "arch/arm/mach-pxa/Kconfig"
 
 source "arch/arm/mach-sa1100/Kconfig"
@@ -222,7 +227,7 @@ config FORCE_MAX_ZONEORDER
 
 config DMABOUNCE
 	bool
-	depends on SA1111
+	depends on SA1111 || ARCH_IXP4XX
 	default y
 
 source arch/arm/mm/Kconfig
@@ -252,7 +257,7 @@ config DISCONTIGMEM
 # Now handle the bus types
 config PCI
 	bool "PCI support" if ARCH_INTEGRATOR_AP
-	default y if ARCH_FTVPCI || ARCH_SHARK || FOOTBRIDGE_HOST || ARCH_IOP3XX
+	default y if ARCH_FTVPCI || ARCH_SHARK || FOOTBRIDGE_HOST || ARCH_IOP3XX || ARCH_IXP4XX
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
 	  bus system, i.e. the way the CPU talks to the other stuff inside
@@ -791,8 +796,8 @@ config DEBUG_S3C2410_PORT
 	  before it is used.
 
 config DEBUG_S3C2410_UART
-	int
 	depends on DEBUG_LL && ARCH_S3C2410
+	int "S3C2410 UART to use for low-level debug"
 	default "0"
 	help
 	  Choice for UART for kernel low-level using S3C2410 UARTS,

arch/arm/Makefile

@@ -92,6 +92,7 @@ textaddr-$(CONFIG_ARCH_CLPS711X)   := 0xc0028000
 textaddr-$(CONFIG_ARCH_FORTUNET)   := 0xc0008000
  machine-$(CONFIG_ARCH_IOP3XX)	   := iop3xx
  machine-$(CONFIG_ARCH_ADIFCC)	   := adifcc
+ machine-$(CONFIG_ARCH_IXP4XX)	   := ixp4xx
  machine-$(CONFIG_ARCH_OMAP)	   := omap
  machine-$(CONFIG_ARCH_S3C2410)	   := s3c2410
  machine-$(CONFIG_ARCH_LH7A40X)	   := lh7a40x

arch/arm/boot/Makefile

@@ -51,6 +51,8 @@ initrd_phys-$(CONFIG_ARCH_SA1100)	:= 0xc0800000
 params_phys-$(CONFIG_ARCH_IOP3XX)	:= 0xa0000100
    zreladdr-$(CONFIG_ARCH_ADIFCC)	:= 0xc0008000
 params_phys-$(CONFIG_ARCH_ADIFCC)	:= 0xc0000100
+   zreladdr-$(CONFIG_ARCH_IXP4XX)	:= 0x00008000
+params-phys-$(CONFIG_ARCH_IXP4XX)	:= 0x00000100
    zreladdr-$(CONFIG_ARCH_OMAP)		:= 0x10008000
 params_phys-$(CONFIG_ARCH_OMAP)		:= 0x10000100
 initrd_phys-$(CONFIG_ARCH_OMAP)		:= 0x10800000

arch/arm/boot/compressed/head.S

@@ -73,6 +73,12 @@
 		.macro	writeb, rb
 		str	\rb, [r3, #0x14]	@ UTDR
 		.endm
+#elif defined(CONFIG_ARCH_IXP4XX)
+		.macro	loadsp, rb
+		mov	\rb, #0xc8000000
+		.endm
+		.macro	writeb, rb
+		str	\rb, [r3, #0]
 #elif defined(CONFIG_ARCH_LH7A40X)
 		.macro	loadsp, rb
 		ldr	\rb, =0x80000700	@ UART2 UARTBASE
@@ -176,7 +182,7 @@ not_angel:
 		ldmia	r0, {r1, r2, r3, r4, r5, r6, ip, sp}
 		subs	r0, r0, r1		@ calculate the delta offset
 
-						@ if delta is zero, we're
+						@ if delta is zero, we are
 		beq	not_relocated		@ running at the address we
 						@ were linked at.
 

arch/arm/kernel/bios32.c

@@ -155,6 +155,30 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
 	}
 }
 
+/*
+ * Same as above. The PrPMC800 carrier board for the PrPMC1100 
+ * card maps the host-bridge @ 00:01:00 for some reason and it
+ * ends up getting scanned. Note that we only want to do this
+ * fixup when we find the IXP4xx on a PrPMC system, which is why
+ * we check the machine type. We could be running on a board
+ * with an IXP4xx target device and we don't want to kill the
+ * resources in that case.
+ */
+static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev)
+{
+	int i;
+
+	if (machine_is_prpmc1100()) {
+		dev->class &= 0xff;
+		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
+		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+			dev->resource[i].start = 0;
+			dev->resource[i].end   = 0;
+			dev->resource[i].flags = 0;
+		}
+	}
+}
+
 /*
  * PCI IDE controllers use non-standard I/O port decoding, respect it.
  */
@@ -273,6 +297,10 @@ struct pci_fixup pcibios_fixups[] = {
 		PCI_FIXUP_HEADER,
 		PCI_ANY_ID,		PCI_ANY_ID,
 		pci_fixup_ide_bases
+	}, {
+		PCI_FIXUP_HEADER,
+		PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_IXP4XX,
+		pci_fixup_prpmc1100
 	}, { 0 }
 };
 

arch/arm/kernel/debug.S

@@ -465,13 +465,53 @@
 		beq	1001b
 		.endm
 
+#elif defined(CONFIG_ARCH_IXP4XX)
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0xc8000000
+                movne   \rx, #0xff000000
+                add     \rx,\rx,#3              @ Uart regs are at off set of 3 if
+						@ byte writes used - Big Endian.
+                .endm
+
+               .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  waituart,rd,rx
+1002:           ldrb    \rd, [\rx, #0x14]
+                and     \rd, \rd, #0x60		@ check THRE and TEMT bits
+                teq     \rd, #0x60
+                bne     1002b
+                .endm
+
+                .macro  busyuart,rd,rx
+                .endm
+
 #elif defined(CONFIG_ARCH_OMAP)
 
 #include <asm/arch/serial.h>
 
+#ifdef CONFIG_ARCH_OMAP730
+#define OMAP_SERIAL_REG_SHIFT	0
+#else
+#define OMAP_SERIAL_REG_SHIFT	2
+#endif
+		/* See also __create_page_tables in head.S */
 		.macro	addruart,rx
-		mov	\rx, #0xff000000
+		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1			@ MMU enabled?
+		moveq	\rx, #0xff000000	@ physical base address
+		movne	\rx, #0xfe000000	@ virtual base
 		orr	\rx, \rx, #0x00fb0000
+#ifdef CONFIG_OMAP_LL_DEBUG_UART3
+		orr	\rx, \rx, #0x00009000	@ UART 3
+#endif
+#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
+		orr	\rx, \rx, #0x00000800	@ UART 2 & 3
+#endif
 		.endm
 
 		.macro	senduart,rd,rx
@@ -486,9 +526,6 @@
 		.endm
 
 		.macro	waituart,rd,rx
-1001:		ldrb	\rd, [\rx, #(0x6 << OMAP_SERIAL_REG_SHIFT)]
-		tst	\rd, #0x10
-		beq	1001b
 		.endm
 
 #elif defined(CONFIG_ARCH_S3C2410)
@@ -551,7 +588,7 @@
 		.endm
 
 #elif defined(CONFIG_ARCH_LH7A40X)
-	@ It isn't known if this will be appropriate for every 40x
+	@ It is not known if this will be appropriate for every 40x
 	@ board.
 
 		.macro  addruart,rx

arch/arm/kernel/entry-armv.S

@@ -623,10 +623,15 @@ ENTRY(soft_irq_mask)
 		.endm
 
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+#ifdef CONFIG_PXA27x
+		mrc	p6, 0, \irqstat, c0, c0, 0		@ ICIP
+		mrc	p6, 0, \irqnr, c1, c0, 0		@ ICMR
+#else
 		mov	\base, #io_p2v(0x40000000)	@ IIR Ctl = 0x40d00000
 		add	\base, \base, #0x00d00000
 		ldr	\irqstat, [\base, #0]		@ ICIP
 		ldr	\irqnr, [\base, #4]		@ ICMR
+#endif
 		ands	\irqnr, \irqstat, \irqnr
 		beq	1001f
 		rsb	\irqstat, \irqnr, #0
@@ -639,6 +644,34 @@ ENTRY(soft_irq_mask)
 		.macro	irq_prio_table
 		.endm
 
+#elif defined (CONFIG_ARCH_IXP4XX)
+
+		.macro	disable_fiq
+		.endm
+		
+		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+		ldr	\irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
+		ldr	\irqstat, [\irqstat]		@ get interrupts
+		cmp	\irqstat, #0
+		beq	1002f
+		clz     \irqnr, \irqstat
+		mov     \base, #31
+		subs    \irqnr, \base, \irqnr
+		
+/*
+1001:		tst	\irqstat, #1
+		addeq	\irqnr, \irqnr, #1
+		moveq	\irqstat, \irqstat, lsr #1
+		tsteq	\irqnr, #32
+		beq	1001b
+		teq	\irqnr, #32
+*/
+1002:
+		.endm
+
+                .macro  irq_prio_table
+                .endm
+
 #elif defined(CONFIG_ARCH_OMAP)
 
 		.macro	disable_fiq
@@ -1219,7 +1252,7 @@ ENTRY(ret_from_exception)
 
 /*
  * Register switch for ARMv3 and ARMv4 processors
- * r0 = previous thread_info, r1 = next thread_info
+ * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
  * previous and next are guaranteed not to be the same.
  */
 ENTRY(__switch_to)

arch/arm/mach-ixp4xx/Kconfig

+
+config ARCH_SUPPORTS_BIG_ENDIAN
+	bool
+	depends on ARCH_IXP4XX
+	default y
+
+menu "Intel IXP4xx Implementation Options"
+
+comment "IXP4xx Platforms"
+
+config ARCH_IXDP425
+	bool "Support for Intel IXDP425 (Richfield) Development Platform"
+	depends on ARCH_IXP4XX
+	help
+#
+# IXCDP1100 is the exact same HW as IXDP425, but with a different machine 
+# number from the bootloader due to marketing monkeys, so we just enable it 
+# by default if IXDP425 is enabled.
+#
+config ARCH_IXCDP1100
+	bool 
+	depends on ARCH_IXDP425
+	default y
+
+config ARCH_PRPMC1100
+	bool "Support for Motorola PrPMC 1100 Platform"
+	depends on ARCH_IXP4XX
+
+config ARCH_ADI_COYOTE
+	bool "Support for ADI Engineering Coyote Gateway Reference Platform"
+	depends on ARCH_IXP4XX
+
+config ARCH_AVILA
+	bool "Support for Gateworks Avila Network Platform"
+	depends on ARCH_IXP4XX
+
+#
+# Avila and IXDP share the same source for now. Will change in future
+#
+config	ARCH_IXDP4XX
+	bool
+	depends on ARCH_IXDP425 || ARCH_AVILA
+	default y
+
+comment "IXP4xx Options"
+
+config IXP4XX_INDIRECT_PCI
+	bool "Use indirect PCI memory access"
+	depends on ARCH_IXP4XX
+	help
+          IXP4xx provides two methods of accessing PCI memory space:
+
+          1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+             To access PCI via this space, we simply ioremap() the BAR
+             into the kernel and we can use the standard read[bwl]/write[bwl]
+             macros. This is the preffered method due to speed but it
+             limits the system to just 64MB of PCI memory. This can be 
+             problamatic if using video cards and other memory-heavy devices.
+          
+          2) If > 64MB of memory space is required, the IXP4xx can be 
+	     configured to use indirect registers to access PCI This allows 
+	     for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 
+	     The disadvantadge of this is that every PCI access requires 
+	     three local register accesses plus a spinlock, but in some 
+	     cases the performance hit is acceptable. In addition, you cannot 
+	     mmap() PCI devices in this case due to the indirect nature
+	     of the PCI window.
+
+	  By default, the direct method is used. Choose this option if you
+	  need to use the indirect method instead. If you don't know
+	  what you need, leave this option unselected.
+
+endmenu

arch/arm/mach-ixp4xx/Makefile

+#
+# Makefile for the linux kernel.
+#
+
+obj-y	+= common.o common-pci.o 
+
+obj-$(CONFIG_ARCH_IXDP4XX)	+= ixdp425-pci.o ixdp425-setup.o
+obj-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-pci.o coyote-setup.o
+obj-$(CONFIG_ARCH_PRPMC1100)	+= prpmc1100-pci.o prpmc1100-setup.o
+

arch/arm/mach-ixp4xx/common.c

+/*
+ * arch/arm/mach-ixp4xx/common.c
+ *
+ * Generic code shared across all IXP4XX platforms
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2002 (c) Intel Corporation
+ * Copyright 2003-2004 (c) MontaVista, Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/sched.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+#include <linux/bootmem.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+
+#include <asm/hardware.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/irq.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+
+/*************************************************************************
+ * GPIO acces functions
+ *************************************************************************/
+
+/*
+ * Configure GPIO line for input, interrupt, or output operation
+ *
+ * TODO: Enable/disable the irq_desc based on interrupt or output mode.
+ * TODO: Should these be named ixp4xx_gpio_?
+ */
+void gpio_line_config(u8 line, u32 style)
+{
+	u32 enable;
+	volatile u32 *int_reg;
+	u32 int_style;
+
+	enable = *IXP4XX_GPIO_GPOER;
+
+	if (style & IXP4XX_GPIO_OUT) {
+		enable &= ~((1) << line);
+	} else if (style & IXP4XX_GPIO_IN) {
+		enable |= ((1) << line);
+
+		switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
+		{
+		case (IXP4XX_GPIO_ACTIVE_HIGH):
+			int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
+			break;
+		case (IXP4XX_GPIO_ACTIVE_LOW):
+			int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
+			break;
+		case (IXP4XX_GPIO_RISING_EDGE):
+			int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
+			break;
+		case (IXP4XX_GPIO_FALLING_EDGE):
+			int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
+			break;
+		case (IXP4XX_GPIO_TRANSITIONAL):
+			int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
+			break;
+		default:
+			int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
+			break;
+		}
+
+		if (line >= 8) {	/* pins 8-15 */ 
+			line -= 8;
+			int_reg = IXP4XX_GPIO_GPIT2R;
+		}
+		else {			/* pins 0-7 */
+			int_reg = IXP4XX_GPIO_GPIT1R;
+		}
+
+		/* Clear the style for the appropriate pin */
+		*int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << 
+		    		(line * IXP4XX_GPIO_STYLE_SIZE));
+
+		/* Set the new style */
+		*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
+	}
+
+	*IXP4XX_GPIO_GPOER = enable;
+}
+
+EXPORT_SYMBOL(gpio_line_config);
+
+/*************************************************************************
+ * IXP4xx chipset I/O mapping
+ *************************************************************************/
+static struct map_desc ixp4xx_io_desc[] __initdata = {
+	{	/* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
+		.virtual	= IXP4XX_PERIPHERAL_BASE_VIRT,
+		.physical	= IXP4XX_PERIPHERAL_BASE_PHYS,
+		.length		= IXP4XX_PERIPHERAL_REGION_SIZE,
+		.type		= MT_DEVICE
+	}, {	/* Expansion Bus Config Registers */
+		.virtual	= IXP4XX_EXP_CFG_BASE_VIRT,
+		.physical	= IXP4XX_EXP_CFG_BASE_PHYS,
+		.length		= IXP4XX_EXP_CFG_REGION_SIZE,
+		.type		= MT_DEVICE
+	}, {	/* PCI Registers */
+		.virtual	= IXP4XX_PCI_CFG_BASE_VIRT,
+		.physical	= IXP4XX_PCI_CFG_BASE_PHYS,
+		.length		= IXP4XX_PCI_CFG_REGION_SIZE,
+		.type		= MT_DEVICE
+	}
+};
+
+void __init ixp4xx_map_io(void)
+{
+  	iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
+}
+
+
+/*************************************************************************
+ * IXP4xx chipset IRQ handling
+ *
+ * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
+ *       (be it PCI or something else) configures that GPIO line
+ *       as an IRQ. Also, we should use a different chip structure for 
+ *       level-based GPIO vs edge-based GPIO. Currently nobody needs this as 
+ *       all HW that's publically available uses level IRQs, so we'll
+ *       worry about it if/when we have HW to test.
+ **************************************************************************/
+static void ixp4xx_irq_mask(unsigned int irq)
+{
+	*IXP4XX_ICMR &= ~(1 << irq);
+}
+
+static void ixp4xx_irq_mask_ack(unsigned int irq)
+{
+	ixp4xx_irq_mask(irq);
+}
+
+static void ixp4xx_irq_unmask(unsigned int irq)
+{
+	static int irq2gpio[NR_IRQS] = {
+		-1, -1, -1, -1, -1, -1,  0,  1,
+		-1, -1, -1, -1, -1, -1, -1, -1,
+		-1, -1, -1,  2,  3,  4,  5,  6,
+		 7,  8,  9, 10, 11, 12, -1, -1,
+	};
+	int line = irq2gpio[irq];
+
+	/*
+	 * This only works for LEVEL gpio IRQs as per the IXP4xx developer's
+	 * manual. If edge-triggered, need to move it to the mask_ack.
+	 * Nobody seems to be using the edge-triggered mode on the GPIOs. 
+	 */
+	if (line > 0)
+		gpio_line_isr_clear(line);
+
+	*IXP4XX_ICMR |= (1 << irq);
+}
+
+static struct irqchip ixp4xx_irq_chip = {
+	.ack	= ixp4xx_irq_mask_ack,
+	.mask	= ixp4xx_irq_mask,
+	.unmask	= ixp4xx_irq_unmask,
+};
+
+void __init ixp4xx_init_irq(void)
+{
+	int i = 0;
+
+	/* Route all sources to IRQ instead of FIQ */
+	*IXP4XX_ICLR = 0x0;
+
+	/* Disable all interrupt */
+	*IXP4XX_ICMR = 0x0; 
+
+	for(i = 0; i < NR_IRQS; i++)
+	{
+		set_irq_chip(i, &ixp4xx_irq_chip);
+		set_irq_handler(i, do_level_IRQ);
+		set_irq_flags(i, IRQF_VALID);
+	}
+}
+
+
+/*************************************************************************
+ * IXP4xx timer tick
+ * We use OS timer1 on the CPU for the timer tick and the timestamp 
+ * counter as a source of real clock ticks to account for missed jiffies.
+ *************************************************************************/
+
+static unsigned volatile last_jiffy_time;
+
+#define CLOCK_TICKS_PER_USEC	(CLOCK_TICK_RATE / USEC_PER_SEC)
+
+/* IRQs are disabled before entering here from do_gettimeofday() */
+static unsigned long ixp4xx_gettimeoffset(void)
+{
+	u32 elapsed;
+
+	elapsed = *IXP4XX_OSTS - last_jiffy_time;
+
+	return elapsed / CLOCK_TICKS_PER_USEC;
+}
+
+static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	/* Clear Pending Interrupt by writing '1' to it */
+	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
+
+	/*
+	 * Catch up with the real idea of time
+	 */
+	do {	
+		do_timer(regs);
+		last_jiffy_time += LATCH;
+	} while((*IXP4XX_OSTS - last_jiffy_time) > LATCH);
+
+	return IRQ_HANDLED;
+}
+
+extern unsigned long (*gettimeoffset)(void);
+
+static struct irqaction timer_irq = {
+	.name	= "IXP4xx Timer Tick",
+	.flags	= SA_INTERRUPT
+};
+
+void __init time_init(void)
+{
+	gettimeoffset = ixp4xx_gettimeoffset;
+	timer_irq.handler = ixp4xx_timer_interrupt;
+
+	/* Clear Pending Interrupt by writing '1' to it */
+	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
+
+	/* Setup the Timer counter value */
+	*IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
+
+	/* Reset time-stamp counter */
+	*IXP4XX_OSTS = 0;
+	last_jiffy_time = 0;
+
+	/* Connect the interrupt handler and enable the interrupt */
+	setup_irq(IRQ_IXP4XX_TIMER1, &timer_irq);
+}
+
+

arch/arm/mach-ixp4xx/coyote-pci.c

+/*
+ * arch/arch/mach-ixp4xx/coyote-pci.c
+ *
+ * PCI setup routines for ADI Engineering Coyote platform
+ *
+ * Copyright (C) 2002 Jungo Software Technologies.
+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
+ *
+ * Maintainer: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/pci.h>
+
+extern void ixp4xx_pci_preinit(void);
+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
+
+void __init coyote_pci_preinit(void)
+{
+	gpio_line_config(COYOTE_PCI_SLOT0_PIN,
+			IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+
+	gpio_line_config(COYOTE_PCI_SLOT1_PIN,
+			IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+
+	gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN);
+	gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN);
+
+	ixp4xx_pci_preinit();
+}
+
+static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	if (slot == COYOTE_PCI_SLOT0_DEVID)
+		return IRQ_COYOTE_PCI_SLOT0;
+	else if (slot == COYOTE_PCI_SLOT1_DEVID)
+		return IRQ_COYOTE_PCI_SLOT1;
+	else return -1;
+}
+
+struct hw_pci coyote_pci __initdata = {
+	.nr_controllers = 1,
+	.preinit =        coyote_pci_preinit,
+	.swizzle =        pci_std_swizzle,
+	.setup =          ixp4xx_setup,
+	.scan =           ixp4xx_scan_bus,
+	.map_irq =        coyote_map_irq,
+};
+
+int __init coyote_pci_init(void)
+{
+	if (machine_is_adi_coyote())
+		pci_common_init(&coyote_pci);
+	return 0;
+}
+
+subsys_initcall(coyote_pci_init);

arch/arm/mach-ixp4xx/coyote-setup.c

+/*
+ * arch/arm/mach-ixp4xx/coyote-setup.c
+ *
+ * ADI Engineering Coyote board-setup 
+ *
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ */
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+#ifdef	__ARMEB__
+#define	REG_OFFSET	3
+#else
+#define	REG_OFFSET	0
+#endif
+
+/*
+ * Only one serial port is connected on the Coyote.
+ */
+static struct uart_port coyote_serial_port = {
+	.membase	= (char*)(IXP4XX_UART2_BASE_VIRT + REG_OFFSET),
+	.mapbase	= (IXP4XX_UART2_BASE_PHYS),
+	.irq		= IRQ_IXP4XX_UART2,
+	.flags		= UPF_SKIP_TEST,
+	.iotype		= UPIO_MEM,	
+	.regshift	= 2,
+	.uartclk	= IXP4XX_UART_XTAL,
+	.line		= 0,
+	.type		= PORT_XSCALE,
+	.fifosize	= 32
+};
+
+void __init coyote_map_io(void)
+{
+	early_serial_setup(&coyote_serial_port);
+
+	ixp4xx_map_io();
+}
+
+static struct flash_platform_data coyote_flash_data = {
+	.map_name	= "cfi_probe",
+	.width		= 2,
+};
+
+static struct resource coyote_flash_resource = {
+	.start		= COYOTE_FLASH_BASE,
+	.end		= COYOTE_FLASH_BASE + COYOTE_FLASH_SIZE,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device coyote_flash_device = {
+	.name		= "IXP4XX-Flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data = &coyote_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &coyote_flash_resource,
+};
+
+static void __init coyote_init(void)
+{
+	platform_add_device(&coyote_flash_device);
+}
+
+MACHINE_START(ADI_COYOTE, "ADI Engineering IXP4XX Coyote Development Platform")
+        MAINTAINER("MontaVista Software, Inc.")
+        BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
+                IXP4XX_PERIPHERAL_BASE_VIRT)
+        MAPIO(coyote_map_io)
+        INITIRQ(ixp4xx_init_irq)
+        BOOT_PARAMS(0x0100)
+	INIT_MACHINE(coyote_init)
+MACHINE_END
+

arch/arm/mach-ixp4xx/ixdp425-pci.c

+/*
+ * arch/arm/mach-ixp4xx/ixdp425-pci.c 
+ *
+ * IXDP425 board-level PCI initialization
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+
+#include <asm/mach/pci.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+void __init ixdp425_pci_preinit(void)
+{
+	gpio_line_config(IXDP425_PCI_INTA_PIN,
+				IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+	gpio_line_config(IXDP425_PCI_INTB_PIN, 
+				IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+	gpio_line_config(IXDP425_PCI_INTC_PIN, 
+				IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+	gpio_line_config(IXDP425_PCI_INTD_PIN, 
+				IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+
+	gpio_line_isr_clear(IXDP425_PCI_INTA_PIN);
+	gpio_line_isr_clear(IXDP425_PCI_INTB_PIN);
+	gpio_line_isr_clear(IXDP425_PCI_INTC_PIN);
+	gpio_line_isr_clear(IXDP425_PCI_INTD_PIN);
+
+	ixp4xx_pci_preinit();
+}
+
+static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	static int pci_irq_table[IXDP425_PCI_IRQ_LINES] = {
+		IRQ_IXDP425_PCI_INTA,
+		IRQ_IXDP425_PCI_INTB,
+		IRQ_IXDP425_PCI_INTC,
+		IRQ_IXDP425_PCI_INTD
+	};
+
+	int irq = -1;
+
+	if (slot >= 1 && slot <= IXDP425_PCI_MAX_DEV && 
+		pin >= 1 && pin <= IXDP425_PCI_IRQ_LINES) {
+		irq = pci_irq_table[(slot + pin - 2) % 4];
+	}
+
+	return irq;
+}
+
+struct hw_pci ixdp425_pci __initdata = {
+	.nr_controllers = 1,
+	.preinit	= ixdp425_pci_preinit,
+	.swizzle	= pci_std_swizzle,
+	.setup		= ixp4xx_setup,
+	.scan		= ixp4xx_scan_bus,
+	.map_irq	= ixdp425_map_irq,
+};
+
+int __init ixdp425_pci_init(void)
+{
+	if (machine_is_ixdp425() || 
+		machine_is_ixcdp1100() || 
+		machine_is_avila())
+		pci_common_init(&ixdp425_pci);
+	return 0;
+}
+
+subsys_initcall(ixdp425_pci_init);
+

arch/arm/mach-ixp4xx/ixdp425-setup.c

+/*
+ * arch/arm/mach-ixp4xx/ixdp425-setup.c
+ *
+ * IXDP425/IXCDP1100 board-setup 
+ *
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ */
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+#ifdef	__ARMEB__
+#define	REG_OFFSET	3
+#else
+#define	REG_OFFSET	0
+#endif
+
+/*
+ * IXDP425 uses both chipset serial ports
+ */
+static struct uart_port ixdp425_serial_ports[] = {
+	{
+		.membase	= (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET),
+		.mapbase	= (IXP4XX_UART1_BASE_PHYS),
+		.irq		= IRQ_IXP4XX_UART1,
+		.flags		= UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,	
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+		.line		= 0,
+		.type		= PORT_XSCALE,
+		.fifosize	= 32
+	} , {
+		.membase	= (char*)(IXP4XX_UART2_BASE_VIRT + REG_OFFSET),
+		.mapbase	= (IXP4XX_UART2_BASE_PHYS),
+		.irq		= IRQ_IXP4XX_UART2,
+		.flags		= UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,	
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+		.line		= 1,
+		.type		= PORT_XSCALE,
+		.fifosize	= 32
+	}
+};
+
+void __init ixdp425_map_io(void) 
+{
+	early_serial_setup(&ixdp425_serial_ports[0]);
+	early_serial_setup(&ixdp425_serial_ports[1]);
+
+	ixp4xx_map_io();
+}
+
+static struct flash_platform_data ixdp425_flash_data = {
+	.map_name	= "cfi_probe",
+	.width		= 2,
+};
+
+static struct resource ixdp425_flash_resource = {
+	.start		= IXDP425_FLASH_BASE,
+	.end		= IXDP425_FLASH_BASE + IXDP425_FLASH_SIZE,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device ixdp425_flash_device = {
+	.name		= "IXP4XX-Flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data = &ixdp425_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &ixdp425_flash_resource,
+};
+
+static struct ixp4xx_i2c_pins ixdp425_i2c_gpio_pins = {
+	.sda_pin	= IXDP425_SDA_PIN,
+	.scl_pin	= IXDP425_SCL_PIN,
+};
+
+static struct platform_device ixdp425_i2c_controller = {
+	.name		= "IXP4XX-I2C",
+	.id		= 0,
+	.dev		= {
+		.platform_data = &ixdp425_i2c_gpio_pins,
+	},
+	.num_resources	= 0
+};
+
+static void __init ixdp425_init(void)
+{
+	platform_add_device(&ixdp425_flash_device);
+	platform_add_device(&ixdp425_i2c_controller);
+}
+
+MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
+	MAINTAINER("MontaVista Software, Inc.")
+	BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
+		IXP4XX_PERIPHERAL_BASE_VIRT)
+	MAPIO(ixdp425_map_io)
+	INITIRQ(ixp4xx_init_irq)
+	BOOT_PARAMS(0x0100)
+	INIT_MACHINE(ixdp425_init)
+MACHINE_END
+
+MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
+	MAINTAINER("MontaVista Software, Inc.")
+	BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
+		IXP4XX_PERIPHERAL_BASE_VIRT)
+	MAPIO(ixdp425_map_io)
+	INITIRQ(ixp4xx_init_irq)
+	BOOT_PARAMS(0x0100)
+	INIT_MACHINE(ixdp425_init)
+MACHINE_END
+
+/*
+ * Avila is functionally equivalent to IXDP425 except that it adds
+ * a CF IDE slot hanging off the expansion bus. When we have a 
+ * driver for IXP4xx CF IDE with driver model support we'll move
+ * Avila to it's own setup file.
+ */
+#ifdef CONFIG_ARCH_AVILA
+MACHINE_START(AVILA, "Gateworks Avila Network Platform")
+	MAINTAINER("Deepak Saxena <dsaxena@plexity.net>")
+	BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
+		IXP4XX_PERIPHERAL_BASE_VIRT)
+	MAPIO(ixdp425_map_io)
+	INITIRQ(ixp4xx_init_irq)
+	BOOT_PARAMS(0x0100)
+	INIT_MACHINE(ixdp425_init)
+MACHINE_END
+#endif
+

arch/arm/mach-ixp4xx/prpmc1100-pci.c

+/*
+ * arch/arm/mach-ixp4xx/prpmc1100-pci.c 
+ *
+ * PrPMC1100 PCI initialization
+ *
+ * Copyright (C) 2003-2004 MontaVista Sofwtare, Inc. 
+ * Based on IXDP425 code originally (C) Intel Corporation
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * PrPMC1100 PCI init code.  GPIO usage is similar to that on 
+ * IXDP425, but the IRQ routing is completely different and
+ * depends on what carrier you are using. This code is written
+ * to work on the Motorola PrPMC800 ATX carrier board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+
+#include <asm/mach/pci.h>
+
+
+void __init prpmc1100_pci_preinit(void)
+{
+	gpio_line_config(PRPMC1100_PCI_INTA_PIN, 
+				IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+	gpio_line_config(PRPMC1100_PCI_INTB_PIN, 
+				IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+	gpio_line_config(PRPMC1100_PCI_INTC_PIN, 
+				IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+	gpio_line_config(PRPMC1100_PCI_INTD_PIN, 
+				IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+
+	gpio_line_isr_clear(PRPMC1100_PCI_INTA_PIN);
+	gpio_line_isr_clear(PRPMC1100_PCI_INTB_PIN);
+	gpio_line_isr_clear(PRPMC1100_PCI_INTC_PIN);
+	gpio_line_isr_clear(PRPMC1100_PCI_INTD_PIN);
+
+	ixp4xx_pci_preinit();
+}
+
+
+static int __init prpmc1100_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq = -1;
+
+	static int pci_irq_table[][4] = { 
+		{	/* IDSEL 16 - PMC A1 */
+			IRQ_PRPMC1100_PCI_INTD, 
+			IRQ_PRPMC1100_PCI_INTA, 
+			IRQ_PRPMC1100_PCI_INTB, 
+			IRQ_PRPMC1100_PCI_INTC
+		}, {	/* IDSEL 17 - PRPMC-A-B */
+			IRQ_PRPMC1100_PCI_INTD, 
+			IRQ_PRPMC1100_PCI_INTA, 
+			IRQ_PRPMC1100_PCI_INTB, 
+			IRQ_PRPMC1100_PCI_INTC
+		}, { 	/* IDSEL 18 - PMC A1-B */
+			IRQ_PRPMC1100_PCI_INTA, 
+			IRQ_PRPMC1100_PCI_INTB, 
+			IRQ_PRPMC1100_PCI_INTC, 
+			IRQ_PRPMC1100_PCI_INTD
+		}, {	/* IDSEL 19 - Unused */
+			0, 0, 0, 0 
+		}, {	/* IDSEL 20 - P2P Bridge */
+			IRQ_PRPMC1100_PCI_INTA, 
+			IRQ_PRPMC1100_PCI_INTB, 
+			IRQ_PRPMC1100_PCI_INTC, 
+			IRQ_PRPMC1100_PCI_INTD
+		}, {	/* IDSEL 21 - PMC A2 */
+			IRQ_PRPMC1100_PCI_INTC, 
+			IRQ_PRPMC1100_PCI_INTD, 
+			IRQ_PRPMC1100_PCI_INTA, 
+			IRQ_PRPMC1100_PCI_INTB
+		}, {	/* IDSEL 22 - PMC A2-B */
+			IRQ_PRPMC1100_PCI_INTD, 
+			IRQ_PRPMC1100_PCI_INTA, 
+			IRQ_PRPMC1100_PCI_INTB, 
+			IRQ_PRPMC1100_PCI_INTC
+		},
+	};
+
+	if (slot >= PRPMC1100_PCI_MIN_DEVID && slot <= PRPMC1100_PCI_MAX_DEVID 
+		&& pin >= 1 && pin <= PRPMC1100_PCI_IRQ_LINES) {
+		irq = pci_irq_table[slot - PRPMC1100_PCI_MIN_DEVID][pin - 1];
+	}
+
+	return irq;
+}
+
+
+struct hw_pci prpmc1100_pci __initdata = {
+	.nr_controllers = 1,
+	.preinit =	  prpmc1100_pci_preinit,
+	.swizzle =	  pci_std_swizzle,
+	.setup =	  ixp4xx_setup,
+	.scan =		  ixp4xx_scan_bus,
+	.map_irq =	  prpmc1100_map_irq,
+};
+
+int __init prpmc1100_pci_init(void)
+{
+	if (machine_is_prpmc1100())
+		pci_common_init(&prpmc1100_pci);
+	return 0;
+}
+
+subsys_initcall(prpmc1100_pci_init);
+

arch/arm/mach-ixp4xx/prpmc1100-setup.c

+/*
+ * arch/arm/mach-ixp4xx/prpmc1100-setup.c
+ *
+ * Motorola PrPMC1100 board setup
+ *
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ */
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+#ifdef	__ARMEB__
+#define	REG_OFFSET	3
+#else
+#define	REG_OFFSET	0
+#endif
+
+/*
+ * Only one serial port is connected on the PrPMC1100
+ */
+static struct uart_port prpmc1100_serial_port = {
+	.membase	= (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET),
+	.mapbase	= (IXP4XX_UART1_BASE_PHYS),
+	.irq		= IRQ_IXP4XX_UART1,
+	.flags		= UPF_SKIP_TEST,
+	.iotype		= UPIO_MEM,	
+	.regshift	= 2,
+	.uartclk	= IXP4XX_UART_XTAL,
+	.line		= 0,
+	.type		= PORT_XSCALE,
+	.fifosize	= 32
+};
+
+void __init prpmc1100_map_io(void)
+{
+	early_serial_setup(&prpmc1100_serial_port);
+
+	ixp4xx_map_io();
+}
+
+static struct flash_platform_data prpmc1100_flash_data = {
+	.map_name	= "cfi_probe",
+	.width		= 2,
+};
+
+static struct resource prpmc1100_flash_resource = {
+	.start		= PRPMC1100_FLASH_BASE,
+	.end		= PRPMC1100_FLASH_BASE + PRPMC1100_FLASH_SIZE,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device prpmc1100_flash_device = {
+	.name		= "IXP4XX-Flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data = &prpmc1100_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &prpmc1100_flash_resource,
+};
+
+static void __init prpmc1100_init(void)
+{
+	platform_add_device(&prpmc1100_flash_device);
+}
+
+MACHINE_START(PRPMC1100, "Motorola PrPMC1100")
+        MAINTAINER("MontaVista Software, Inc.")
+        BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
+                IXP4XX_PERIPHERAL_BASE_VIRT)
+        MAPIO(prpmc1100_map_io)
+        INITIRQ(ixp4xx_init_irq)
+        BOOT_PARAMS(0x0100)
+	INIT_MACHINE(prpmc1100_init)
+MACHINE_END
+

arch/arm/mach-omap/innovator1510.c

-/*
- * linux/arch/arm/mach-omap/innovator1510.c
- *
- * Board specific inits for OMAP-1510 Innovator
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
- * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/hardware.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/clocks.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/fpga.h>
-
-#include "common.h"
-
-extern int omap_gpio_init(void);
-
-void innovator_init_irq(void)
-{
-	omap_init_irq();
-	omap_gpio_init();
-	fpga_init_irq();
-}
-
-static struct resource smc91x_resources[] = {
-	[0] = {
-		.start	= OMAP1510P1_FPGA_ETHR_START,	/* Physical */
-		.end	= OMAP1510P1_FPGA_ETHR_START + 16,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_ETHER,
-		.end	= INT_ETHER,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smc91x_device = {
-	.name		= "smc91x",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(smc91x_resources),
-	.resource	= smc91x_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&smc91x_device,
-};
-
-static void __init innovator_init(void)
-{
-	if (!machine_is_innovator())
-		return;
-
-	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-/* Only FPGA needs to be mapped here. All others are done with ioremap */
-static struct map_desc innovator_io_desc[] __initdata = {
-{ OMAP1510P1_FPGA_BASE, OMAP1510P1_FPGA_START, OMAP1510P1_FPGA_SIZE,
-	MT_DEVICE },
-};
-
-static void __init innovator_map_io(void)
-{
-	omap_map_io();
-	iotable_init(innovator_io_desc, ARRAY_SIZE(innovator_io_desc));
-
-	/* Dump the Innovator FPGA rev early - useful info for support. */
-	printk("Innovator FPGA Rev %d.%d Board Rev %d\n",
-	       fpga_read(OMAP1510P1_FPGA_REV_HIGH),
-	       fpga_read(OMAP1510P1_FPGA_REV_LOW),
-	       fpga_read(OMAP1510P1_FPGA_BOARD_REV));
-}
-
-MACHINE_START(INNOVATOR, "TI-Innovator/OMAP1510")
-	MAINTAINER("MontaVista Software, Inc.")
-	BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
-	BOOT_PARAMS(0x10000100)
-	MAPIO(innovator_map_io)
-	INITIRQ(innovator_init_irq)
-	INIT_MACHINE(innovator_init)
-MACHINE_END

arch/arm/mach-omap/innovator1610.c

-/*
- * linux/arch/arm/mach-omap/innovator1610.c
- *
- * This file contains Innovator-specific code.
- *
- * Copyright (C) 2002 MontaVista Software, Inc.
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: Greg Lonnon <glonnon@ridgerun.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/config.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/major.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/hardware.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/arch/irqs.h>
-
-#include "common.h"
-
-void
-innovator_init_irq(void)
-{
-	omap_init_irq();
-}
-
-static struct resource smc91x_resources[] = {
-	[0] = {
-		.start	= OMAP1610_ETHR_START,		/* Physical */
-		.end	= OMAP1610_ETHR_START + SZ_4K,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= 0,				/* Really GPIO 0 */
-		.end	= 0,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smc91x_device = {
-	.name		= "smc91x",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(smc91x_resources),
-	.resource	= smc91x_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&smc91x_device,
-};
-
-static void __init innovator_init(void)
-{
-	if (!machine_is_innovator())
-		return;
-
-	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static struct map_desc innovator_io_desc[] __initdata = {
-{ OMAP1610_ETHR_BASE, OMAP1610_ETHR_START, OMAP1610_ETHR_SIZE,MT_DEVICE },
-{ OMAP1610_NOR_FLASH_BASE, OMAP1610_NOR_FLASH_START, OMAP1610_NOR_FLASH_SIZE,
-	MT_DEVICE },
-};
-
-static void __init innovator_map_io(void)
-{
-	omap_map_io();
-	iotable_init(innovator_io_desc, ARRAY_SIZE(innovator_io_desc));
-}
-
-MACHINE_START(INNOVATOR, "TI-Innovator/OMAP1610")
-	MAINTAINER("MontaVista Software, Inc.")
-	BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
-	BOOT_PARAMS(0x10000100)
-	MAPIO(innovator_map_io)
-	INITIRQ(innovator_init_irq)
-	INIT_MACHINE(innovator_init)
-MACHINE_END
-

arch/arm/mach-omap/omap-generic.c

-/*
- * linux/arch/arm/mach-omap/generic.c
- *
- * Modified from innovator.c
- *
- * Code for generic OMAP board. Should work on many OMAP systems where
- * the device drivers take care of all the necessary hardware initialization.
- * Do not put any board specific code to this file; create a new machine
- * type if you need custom low-level initializations.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/hardware.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/clocks.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-
-#include "common.h"
-
-static void __init omap_generic_init_irq(void)
-{
-	omap_init_irq();
-}
-
-/*
- * Muxes the serial ports on
- */
-static void __init omap_early_serial_init(void)
-{
-	omap_cfg_reg(UART1_TX);
-	omap_cfg_reg(UART1_RTS);
-
-	omap_cfg_reg(UART2_TX);
-	omap_cfg_reg(UART2_RTS);
-
-	omap_cfg_reg(UART3_TX);
-	omap_cfg_reg(UART3_RX);
-}
-
-static void __init omap_generic_init(void)
-{
-	if (!machine_is_omap_generic())
-		return;
-
-	/*
-	 * Make sure the serial ports are muxed on at this point.
-	 * You have to mux them off in device drivers later on
-	 * if not needed.
-	 */
-	if (cpu_is_omap1510()) {
-		omap_early_serial_init();
-	}
-}
-
-static void __init omap_generic_map_io(void)
-{
-	omap_map_io();
-}
-
-MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610")
-	MAINTAINER("Tony Lindgren <tony@atomide.com>")
-	BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
-	BOOT_PARAMS(0x10000100)
-	MAPIO(omap_generic_map_io)
-	INITIRQ(omap_generic_init_irq)
-	INIT_MACHINE(omap_generic_init)
-MACHINE_END

arch/arm/mach-omap/omap-perseus2.c

-/*
- * linux/arch/arm/mach-omap/omap-perseus2.c
- *
- * Modified from omap-generic.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/hardware.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <asm/arch/clocks.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-
-#include <asm/arch/omap-perseus2.h>
-
-#include "common.h"
-
-void omap_perseus2_init_irq(void)
-{
-	omap_init_irq();
-}
-
-static struct resource smc91x_resources[] = {
-	[0] = {
-		.start	= OMAP730_FPGA_ETHR_START,	/* Physical */
-		.end	= OMAP730_FPGA_ETHR_START + SZ_4K,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= 0,
-		.end	= 0,
-		.flags	= INT_ETHER,
-	},
-};
-
-static struct platform_device smc91x_device = {
-	.name		= "smc91x",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(smc91x_resources),
-	.resource	= smc91x_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&smc91x_device,
-};
-
-static void __init omap_perseus2_init(void)
-{
-	if (!machine_is_omap_perseus2())
-		return;
-
-	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-/* Only FPGA needs to be mapped here. All others are done with ioremap */
-static struct map_desc omap_perseus2_io_desc[] __initdata = {
-	{OMAP730_FPGA_BASE, OMAP730_FPGA_START, OMAP730_FPGA_SIZE,
-	 MT_DEVICE},
-};
-
-static void __init omap_perseus2_map_io(void)
-{
-	omap_map_io();
-	iotable_init(omap_perseus2_io_desc,
-		     ARRAY_SIZE(omap_perseus2_io_desc));
-
-	/* Early, board-dependent init */
-
-	/*
-	 * Hold GSM Reset until needed
-	 */
-	*DSP_M_CTL &= ~1;
-
-	/*
-	 * UARTs -> done automagically by 8250 driver
-	 */
-
-	/*
-	 * CSx timings, GPIO Mux ... setup
-	 */
-
-	/* Flash: CS0 timings setup */
-	*((volatile __u32 *) OMAP_FLASH_CFG_0) = 0x0000fff3;
-	*((volatile __u32 *) OMAP_FLASH_ACFG_0) = 0x00000088;
-
-	/*
-	 * Ethernet support trough the debug board
-	 * CS1 timings setup
-	 */
-	*((volatile __u32 *) OMAP_FLASH_CFG_1) = 0x0000fff3;
-	*((volatile __u32 *) OMAP_FLASH_ACFG_1) = 0x00000000;
-
-	/*
-	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
-	 * It is used as the Ethernet controller interrupt
-	 */
-	*((volatile __u32 *) PERSEUS2_IO_CONF_9) &= 0x1FFFFFFF;
-}
-
-MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
-	MAINTAINER("Kevin Hilman <k-hilman@ti.com>")
-	BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000)
-	BOOT_PARAMS(0x10000100)
-	MAPIO(omap_perseus2_map_io)
-	INITIRQ(omap_perseus2_init_irq)
-	INIT_MACHINE(omap_perseus2_init)
-MACHINE_END

arch/arm/mach-pxa/Kconfig

 
-menu "Intel PXA250/210 Implementations"
+menu "Intel PXA2xx Implementations"
 
 config ARCH_LUBBOCK
 	bool "Intel DBPXA250 Development Platform"
 	depends on ARCH_PXA
+	select PXA25x
 
 config ARCH_PXA_IDP
 	bool "Accelent Xscale IDP"
 	depends on ARCH_PXA
+	select PXA25x
 
 endmenu
 
+config PXA25x
+	bool
+	help
+	  Select code specific to PXA21x/25x/26x variants
+
+config PXA27x
+	bool
+	help
+	  Select code specific to PXA27x variants
+

arch/arm/mach-pxa/Makefile

@@ -4,6 +4,8 @@
 
 # Common support (must be linked before board specific support)
 obj-y += generic.o irq.o dma.o
+obj-$(CONFIG_PXA25x) += pxa25x.o
+obj-$(CONFIG_PXA27x) += pxa27x.o
 
 # Specific board support
 obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o

arch/arm/mach-pxa/dma.c

@@ -28,7 +28,7 @@ static struct dma_channel {
 	char *name;
 	void (*irq_handler)(int, void *, struct pt_regs *);
 	void *data;
-} dma_channels[16];
+} dma_channels[PXA_DMA_CHANNELS];
 
 
 int pxa_request_dma (char *name, pxa_dma_prio prio,
@@ -45,7 +45,7 @@ int pxa_request_dma (char *name, pxa_dma_prio prio,
 	local_irq_save(flags);
 
 	/* try grabbing a DMA channel with the requested priority */
-	for (i = prio; i < prio + (prio == DMA_PRIO_LOW) ? 8 : 4; i++) {
+	for (i = prio; i < prio + PXA_DMA_NBCH(prio); i++) {
 		if (!dma_channels[i].name) {
 			found = 1;
 			break;
@@ -97,7 +97,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 {
 	int i, dint = DINT;
 
-	for (i = 0; i < 16; i++) {
+	for (i = 0; i < PXA_DMA_CHANNELS; i++) {
 		if (dint & (1 << i)) {
 			struct dma_channel *channel = &dma_channels[i];
 			if (channel->name && channel->irq_handler) {

arch/arm/mach-pxa/generic.c

@@ -31,76 +31,10 @@
 #include <asm/mach/map.h>
 
 #include <asm/arch/udc.h>
+#include <asm/arch/pxafb.h>
 
 #include "generic.h"
 
-/*
- * Various clock factors driven by the CCCR register.
- */
-
-/* Crystal Frequency to Memory Frequency Multiplier (L) */
-static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
-
-/* Memory Frequency to Run Mode Frequency Multiplier (M) */
-static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
-
-/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
-/* Note: we store the value N * 2 here. */
-static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
-
-/* Crystal clock */
-#define BASE_CLK	3686400
-
-/*
- * Get the clock frequency as reflected by CCCR and the turbo flag.
- * We assume these values have been applied via a fcs.
- * If info is not 0 we also display the current settings.
- */
-unsigned int get_clk_frequency_khz(int info)
-{
-	unsigned long cccr, turbo;
-	unsigned int l, L, m, M, n2, N;
-
-	cccr = CCCR;
-	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
-
-	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
-	m  =  M_clk_mult[(cccr >> 5) & 0x03];
-	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
-
-	L = l * BASE_CLK;
-	M = m * L;
-	N = n2 * M / 2;
-
-	if(info)
-	{
-		L += 5000;
-		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
-			L / 1000000, (L % 1000000) / 10000, l );
-		M += 5000;
-		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
-			M / 1000000, (M % 1000000) / 10000, m );
-		N += 5000;
-		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
-			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
-			(turbo & 1) ? "" : "in" );
-	}
-
-	return (turbo & 1) ? (N/1000) : (M/1000);
-}
-
-EXPORT_SYMBOL(get_clk_frequency_khz);
-
-/*
- * Return the current lclk requency in units of 10kHz
- */
-unsigned int get_lclk_frequency_10khz(void)
-{
-	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
-}
-
-EXPORT_SYMBOL(get_lclk_frequency_10khz);
-
 /*
  * Handy function to set GPIO alternate functions
  */
@@ -125,16 +59,21 @@ void pxa_gpio_mode(int gpio_mode)
 EXPORT_SYMBOL(pxa_gpio_mode);
 
 /*
- * Note that 0xfffe0000-0xffffffff is reserved for the vector table and
- * cache flush area.
+ * Intel PXA2xx internal register mapping.
+ *
+ * Note 1: not all PXA2xx variants implement all those addresses.
+ *
+ * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
+ *         and cache flush area.
  */
 static struct map_desc standard_io_desc[] __initdata = {
  /* virtual     physical    length      type */
-  { 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */
-  { 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */
-  { 0xf8000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */
-  { 0xfa000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
-  { 0xfc000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
+  { 0xf2000000, 0x40000000, 0x01800000, MT_DEVICE }, /* Devs */
+  { 0xf4000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
+  { 0xf6000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
+  { 0xf8000000, 0x4c000000, 0x00100000, MT_DEVICE }, /* USB host */
+  { 0xfa000000, 0x50000000, 0x00100000, MT_DEVICE }, /* Camera */
+  { 0xfe000000, 0x58000000, 0x00100000, MT_DEVICE }, /* IMem ctl */
   { 0xff000000, 0x00000000, 0x00100000, MT_DEVICE }  /* UNCACHED_PHYS_0 */
 };
 
@@ -205,9 +144,45 @@ static struct platform_device udc_device = {
 	}
 };
 
+static struct pxafb_mach_info pxa_fb_info;
+
+void __init set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info)
+{
+	memcpy(&pxa_fb_info,hard_pxa_fb_info,sizeof(struct pxafb_mach_info));
+}
+EXPORT_SYMBOL(set_pxa_fb_info);
+
+static struct resource pxafb_resources[] = {
+	[0] = {
+		.start	= 0x44000000,
+		.end	= 0x4400ffff,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_LCD,
+		.end	= IRQ_LCD,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static u64 fb_dma_mask = ~(u64)0;
+
+static struct platform_device pxafb_device = {
+	.name		= "pxafb",
+	.id		= 0,
+	.dev		= {
+ 		.platform_data	= &pxa_fb_info,
+		.dma_mask	= &fb_dma_mask,
+		.coherent_dma_mask = 0xffffffff,
+	},
+	.num_resources	= ARRAY_SIZE(pxafb_resources),
+	.resource	= pxafb_resources,
+};
+
 static struct platform_device *devices[] __initdata = {
 	&pxamci_device,
 	&udc_device,
+	&pxafb_device,
 };
 
 static int __init pxa_init(void)

arch/arm/mach-pxa/pm.c

@@ -32,6 +32,11 @@ extern void pxa_cpu_resume(void);
 #define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
 #define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]
 
+#define RESTORE_GPLEVEL(n) do { \
+	GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
+	GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
+} while (0)
+
 /*
  * List of global PXA peripheral registers to preserve.
  * More ones like CP and general purpose register values are preserved
@@ -42,16 +47,13 @@ enum {	SLEEP_SAVE_START = 0,
 	SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER,
 	SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3,
 
+	SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
 	SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
 	SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
 	SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
 	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L,
 	SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U,
 
-	SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR,
-	SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR,
-	SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,
-
 	SLEEP_SAVE_ICMR,
 	SLEEP_SAVE_CKEN,
 
@@ -74,21 +76,6 @@ static int pxa_pm_enter(u32 state)
 	/* preserve current time */
 	delta = xtime.tv_sec - RCNR;
 
-	/*
-	 * Temporary solution.  This won't be necessary once
-	 * we move pxa support into the serial driver
-	 * Save the FF UART
-	 */
-	SAVE(FFIER);
-	SAVE(FFLCR);
-	SAVE(FFMCR);
-	SAVE(FFSPR);
-	SAVE(FFISR);
-	FFLCR |= 0x80;
-	SAVE(FFDLL);
-	SAVE(FFDLH);
-	FFLCR &= 0xef;
-
 	/* save vital registers */
 	SAVE(OSCR);
 	SAVE(OSMR0);
@@ -97,6 +84,7 @@ static int pxa_pm_enter(u32 state)
 	SAVE(OSMR3);
 	SAVE(OIER);
 
+	SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
 	SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
 	SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
 	SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
@@ -146,14 +134,15 @@ static int pxa_pm_enter(u32 state)
 	PSPR = 0;
 
 	/* restore registers */
-	RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
-	RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
-	RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
 	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
 	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
 	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
+	RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
+	RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
+	RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
+	RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
 
-	PSSR = PSSR_PH;
+	PSSR = PSSR_RDH | PSSR_PH;
 
 	RESTORE(OSMR0);
 	RESTORE(OSMR1);
@@ -168,22 +157,6 @@ static int pxa_pm_enter(u32 state)
 	ICCR = 1;
 	RESTORE(ICMR);
 
-	/*
-	 * Temporary solution.  This won't be necessary once
-	 * we move pxa support into the serial driver.
-	 * Restore the FF UART.
-	 */
-	RESTORE(FFMCR);
-	RESTORE(FFSPR);
-	RESTORE(FFLCR);
-	FFLCR |= 0x80;
-	RESTORE(FFDLH);
-	RESTORE(FFDLL);
-	RESTORE(FFLCR);
-	RESTORE(FFISR);
-	FFFCR = 0x07;
-	RESTORE(FFIER);
-
 	/* restore current time */
 	xtime.tv_sec = RCNR + delta;
 

arch/arm/mach-pxa/pxa25x.c

+/*
+ *  linux/arch/arm/mach-pxa/pxa25x.c
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Jun 15, 2001
+ *  Copyright:	MontaVista Software Inc.
+ *
+ * Code specific to PXA21x/25x/26x variants.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Since this file should be linked before any other machine specific file,
+ * the __initcall() here will be executed first.  This serves as default
+ * initialization stuff for PXA machines which can be overridden later if
+ * need be.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+
+#include <asm/hardware.h>
+
+#include "generic.h"
+
+/*
+ * Various clock factors driven by the CCCR register.
+ */
+
+/* Crystal Frequency to Memory Frequency Multiplier (L) */
+static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
+
+/* Memory Frequency to Run Mode Frequency Multiplier (M) */
+static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
+
+/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
+/* Note: we store the value N * 2 here. */
+static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
+
+/* Crystal clock */
+#define BASE_CLK	3686400
+
+/*
+ * Get the clock frequency as reflected by CCCR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int get_clk_frequency_khz(int info)
+{
+	unsigned long cccr, turbo;
+	unsigned int l, L, m, M, n2, N;
+
+	cccr = CCCR;
+	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
+
+	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
+	m  =  M_clk_mult[(cccr >> 5) & 0x03];
+	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
+
+	L = l * BASE_CLK;
+	M = m * L;
+	N = n2 * M / 2;
+
+	if(info)
+	{
+		L += 5000;
+		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
+			L / 1000000, (L % 1000000) / 10000, l );
+		M += 5000;
+		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
+			M / 1000000, (M % 1000000) / 10000, m );
+		N += 5000;
+		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
+			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
+			(turbo & 1) ? "" : "in" );
+	}
+
+	return (turbo & 1) ? (N/1000) : (M/1000);
+}
+
+EXPORT_SYMBOL(get_clk_frequency_khz);
+
+/*
+ * Return the current lclk requency in units of 10kHz
+ */
+unsigned int get_lclk_frequency_10khz(void)
+{
+	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
+}
+
+EXPORT_SYMBOL(get_lclk_frequency_10khz);
+

arch/arm/mach-pxa/pxa27x.c

+/*
+ *  linux/arch/arm/mach-pxa/pxa27x.c
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Nov 05, 2002
+ *  Copyright:	MontaVista Software Inc.
+ *
+ * Code specific to PXA27x aka Bulverde.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+
+#include <asm/hardware.h>
+
+#include "generic.h"
+
+/* Crystal clock : 13-MHZ*/
+#define BASE_CLK	13000000
+
+/*
+ * Get the clock frequency as reflected by CCSR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ *
+ * For more details, refer to Bulverde Manual, section 3.8.2.1
+ */
+unsigned int get_clk_frequency_khz( int info)
+{
+	unsigned long ccsr, turbo, b, ht;
+	unsigned int l, L, m, M, n2, N, S, cccra;
+
+	ccsr = CCSR;
+	cccra = CCCR & (0x1 << 25);
+
+	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
+	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
+	b = (turbo & (0x1 << 3));
+	ht = (turbo & (0x1 << 2));
+
+	l  = ccsr & 0x1f;
+	n2 = (ccsr>>7) & 0xf;
+	if (l == 31) {
+		/* The calculation from the Yellow Book is incorrect:
+		   it says M=4 for L=21-30 (which is easy to calculate
+		   by subtracting 1 and then dividing by 10, but not
+		   with 31, so we'll do it manually */
+		m = 1 << 2;
+	} else {
+		m = 1 << ((l-1)/10);
+	}
+
+	L = l * BASE_CLK;
+	N = (n2 * L) / 2;
+	S = (b) ? L : (L/2);
+	if (cccra == 0)
+		M = L/m;
+	else
+		M = (b) ? L : (L/2);
+
+	if (info) {
+		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
+			L / 1000000, (L % 1000000) / 10000, l );
+		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
+			M / 1000000, (M % 1000000) / 10000, m );
+		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
+			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
+			(turbo & 1) ? "" : "in" );
+		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
+			S / 1000000, (S % 1000000) / 10000 );
+	}
+
+	return (turbo & 1) ? (N/1000) : (L/1000);
+}
+
+/*
+ * Return the current mem clock frequency in units of 10kHz as
+ * reflected by CCCR[A], B, and L
+ */
+unsigned int get_lclk_frequency_10khz(void)
+{
+	unsigned long ccsr, clkcfg, b;
+	unsigned int l, L, m, M, cccra;
+
+	cccra = CCCR & (0x1 << 25);
+
+	/* Read clkcfg register to obtain b */
+	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
+	b = (clkcfg & (0x1 << 3));
+
+	ccsr = CCSR;
+	l  =  ccsr & 0x1f;
+	if (l == 31) {
+		/* The calculation from the Yellow Book is incorrect:
+		   it says M=4 for L=21-30 (which is easy to calculate
+		   by subtracting 1 and then dividing by 10, but not
+		   with 31, so we'll do it manually */
+		m = 1 << 2;
+	} else {
+		m = 1 << ((l-1)/10);
+	}
+
+	L = l * BASE_CLK;
+	if (cccra == 0)
+		M = L/m;
+	else
+		M = (b) ? L : L/2;
+
+	return (M / 10000);
+}
+
+EXPORT_SYMBOL(get_clk_frequency_khz);
+EXPORT_SYMBOL(get_lclk_frequency_10khz);
+

arch/arm/mach-s3c2410/Kconfig

@@ -16,6 +16,13 @@ config ARCH_H1940
 	  Say Y here if you are using the HP IPAQ H1940
 	  <http://www.handhelds.org/projects/h1940.html>.
 
+config ARCH_SMDK2410
+	bool "SMDK2410/A9M2410"
+	depends on ARCH_S3C2410
+	help
+	   Say Y here if you are using the SMDK2410 or the derived module A9M2410
+           <http://www.fsforth.de>
+
 config MACH_VR1000
 	bool "Simtec VR1000"
 	depends on ARCH_S3C2410

arch/arm/mach-s3c2410/Makefile

@@ -12,6 +12,7 @@ obj-			:=
 obj-$(CONFIG_ARCH_BAST)    += mach-bast.o
 obj-$(CONFIG_MACH_H1940)   += mach-h1940.o
 obj-$(CONFIG_ARCH_H1940)   += mach-h1940.o
+obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
 obj-$(CONFIG_MACH_VR1000)  += mach-vr1000.o
 
 #obj-$(CONFIG_PCI)	+=$(pci-y)

arch/arm/mach-s3c2410/mach-smdk2410.c

+/***********************************************************************
+ *
+ * linux/arch/arm/mach-s3c2410/mach-smdk2410.c
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH
+ * All rights reserved.
+ *
+ * $Id: mach-smdk2410.c,v 1.1 2004/05/11 14:15:38 mpietrek Exp $
+ * @Author: Jonas Dietsche
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * @History:
+ * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
+ * Ben Dooks <ben@simtec.co.uk>
+ ***********************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/regs-serial.h>
+
+#include "s3c2410.h"
+
+
+static struct map_desc smdk2410_iodesc[] __initdata = {
+  /* nothing here yet */
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+/* base baud rate for all our UARTs */
+static unsigned long smdk2410_serial_clock = 24*1000*1000;
+
+static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
+	[0] = {
+		.hwport	     = 0,
+		.flags	     = 0,
+		.clock	     = &smdk2410_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	},
+	[1] = {
+		.hwport	     = 1,
+		.flags	     = 0,
+		.clock	     = &smdk2410_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	},
+	[2] = {
+		.hwport	     = 2,
+		.flags	     = 0,
+		.clock	     = &smdk2410_serial_clock,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
+	}
+};
+
+
+void __init smdk2410_map_io(void)
+{
+	s3c2410_map_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
+	s3c2410_uartcfgs = smdk2410_uartcfgs;
+}
+
+void __init smdk2410_init_irq(void)
+{
+	s3c2410_init_irq();
+}
+
+MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch
+				    * to SMDK2410 */
+     MAINTAINER("Jonas Dietsche")
+     BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
+     BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
+     MAPIO(smdk2410_map_io)
+     INITIRQ(smdk2410_init_irq)
+MACHINE_END

arch/arm/mm/Kconfig

@@ -220,7 +220,7 @@ config CPU_SA1100
 # XScale
 config CPU_XSCALE
 	bool
-	depends on ARCH_IOP3XX || ARCH_ADIFCC || ARCH_PXA
+	depends on ARCH_IOP3XX || ARCH_ADIFCC || ARCH_PXA || ARCH_IXP4XX
 	default y
 	select CPU_32v5
 	select CPU_ABRT_EV5T

arch/arm/mm/blockops.c

@@ -133,7 +133,7 @@ static int __init blockops_check(void)
 	unsigned int cache_type;
 	int i;
 
-	asm("mcr p15, 0, %0, c0, c0, 1" : "=r" (cache_type));
+	asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (cache_type));
 
 	printk("Checking V6 block cache operations:\n");
 	register_undef_hook(&blockops_hook);

arch/arm/mm/cache-v6.S

@@ -151,6 +151,7 @@ ENTRY(v6_dma_inv_range)
 	add	r0, r0, #D_CACHE_LINE_SIZE
 	cmp	r0, r1
 	blo	1b
+	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
 	mov	pc, lr
 
@@ -188,6 +189,7 @@ ENTRY(v6_dma_flush_range)
 	mcr	p15, 0, r0, c7, c15, 1		@ clean & invalidate line
 #endif
 	add	r0, r0, #D_CACHE_LINE_SIZE
+	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer

drivers/pcmcia/Kconfig

@@ -120,6 +120,13 @@ config PCMCIA_SA1111
 
 	  This driver is also available as a module called sa1111_cs.
 
+config PCMCIA_PXA2XX
+	tristate "PXA2xx support"
+	depends on ARM && ARCH_PXA && PCMCIA
+	help
+	  Say Y here to include support for the PXA2xx PCMCIA controller
+
+
 config PCMCIA_PROBE
 	bool
 	default y if ISA && !ARCH_SA1100 && !ARCH_CLPS711X

drivers/pcmcia/pxa2xx_base.h

+/* temporary measure */
+extern int pxa2xx_drv_pcmcia_probe(struct device *);
+